io.h

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    1 enum {
    2         IrqCLOCK        = 0,
    3         IrqKBD          = 1,
    4         IrqUART1        = 3,
    5         IrqUART0        = 4,
    6         IrqPCMCIA       = 5,
    7         IrqFLOPPY       = 6,
    8         IrqLPT          = 7,
    9         IrqIRQ7         = 7,
   10         IrqAUX          = 12,           /* PS/2 port */
   11         IrqIRQ13        = 13,           /* coprocessor on 386 */
   12         IrqATA0         = 14,
   13         IrqATA1         = 15,
   14         MaxIrqPIC       = 15,
   15 
   16         VectorPIC       = 64,
   17         MaxVectorPIC    = VectorPIC+MaxIrqPIC,
   18         VectorPCI       = 16,           /* PCI bus (PLD) */
   19 };
   20 
   21 typedef struct Vctl {
   22         Vctl*   next;                   /* handlers on this vector */
   23 
   24         char    name[KNAMELEN]; /* of driver */
   25         int     isintr;                 /* interrupt or fault/trap */
   26         int     irq;
   27         int     tbdf;
   28         int     (*isr)(int);            /* get isr bit for this irq */
   29         int     (*eoi)(int);            /* eoi */
   30 
   31         void    (*f)(Ureg*, void*);     /* handler to call */
   32         void*   a;                      /* argument to call it with */
   33 } Vctl;
   34 
   35 enum {
   36         BusCBUS         = 0,            /* Corollary CBUS */
   37         BusCBUSII,                      /* Corollary CBUS II */
   38         BusEISA,                        /* Extended ISA */
   39         BusFUTURE,                      /* IEEE Futurebus */
   40         BusINTERN,                      /* Internal bus */
   41         BusISA,                         /* Industry Standard Architecture */
   42         BusMBI,                         /* Multibus I */
   43         BusMBII,                        /* Multibus II */
   44         BusMCA,                         /* Micro Channel Architecture */
   45         BusMPI,                         /* MPI */
   46         BusMPSA,                        /* MPSA */
   47         BusNUBUS,                       /* Apple Macintosh NuBus */
   48         BusPCI,                         /* Peripheral Component Interconnect */
   49         BusPCMCIA,                      /* PC Memory Card International Association */
   50         BusTC,                          /* DEC TurboChannel */
   51         BusVL,                          /* VESA Local bus */
   52         BusVME,                         /* VMEbus */
   53         BusXPRESS,                      /* Express System Bus */
   54 };
   55 
   56 #define MKBUS(t,b,d,f)  (((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
   57 #define BUSFNO(tbdf)    (((tbdf)>>8)&0x07)
   58 #define BUSDNO(tbdf)    (((tbdf)>>11)&0x1F)
   59 #define BUSBNO(tbdf)    (((tbdf)>>16)&0xFF)
   60 #define BUSTYPE(tbdf)   ((tbdf)>>24)
   61 #define BUSDF(tbdf)             ((tbdf)&0x000FF00)
   62 #define BUSBDF(tbdf)    ((tbdf)&0x0FFFF00)
   63 #define BUSUNKNOWN      (-1)
   64 
   65 enum {
   66         MaxEISA         = 16,
   67         EISAconfig      = 0xC80,
   68 };
   69 
   70 /*
   71  * PCI support code.
   72  */
   73 enum {                                  /* type 0 and type 1 pre-defined header */
   74         PciVID          = 0x00,         /* vendor ID */
   75         PciDID          = 0x02,         /* device ID */
   76         PciPCR          = 0x04,         /* command */
   77         PciPSR          = 0x06,         /* status */
   78         PciRID          = 0x08,         /* revision ID */
   79         PciCCRp         = 0x09,         /* programming interface class code */
   80         PciCCRu         = 0x0A,         /* sub-class code */
   81         PciCCRb         = 0x0B,         /* base class code */
   82         PciCLS          = 0x0C,         /* cache line size */
   83         PciLTR          = 0x0D,         /* latency timer */
   84         PciHDT          = 0x0E,         /* header type */
   85         PciBST          = 0x0F,         /* BIST */
   86 
   87         PciBAR0         = 0x10,         /* base address */
   88         PciBAR1         = 0x14,
   89         PciROM          = 0x30,
   90 
   91         PciINTL         = 0x3C,         /* interrupt line */
   92         PciINTP         = 0x3D,         /* interrupt pin */
   93 };
   94 
   95 enum {                                  /* type 0 pre-defined header */
   96         PciCIS          = 0x28,         /* cardbus CIS pointer */
   97         PciSVID         = 0x2C,         /* subsystem vendor ID */
   98         PciSID          = 0x2E,         /* cardbus CIS pointer */
   99         PciEBAR0        = 0x30,         /* xpansion ROM base address */
  100         PciMGNT         = 0x3E,         /* burst period length */
  101         PciMLT          = 0x3F,         /* maximum latency between bursts */
  102 };
  103 
  104 enum {                                  /* type 1 pre-defined header */
  105         PciPBN          = 0x18,         /* primary bus number */
  106         PciSBN          = 0x19,         /* secondary bus number */
  107         PciUBN          = 0x1A,         /* subordinate bus number */
  108         PciSLTR         = 0x1B,         /* secondary latency timer */
  109         PciIBR          = 0x1C,         /* I/O base */
  110         PciILR          = 0x1D,         /* I/O limit */
  111         PciSPSR         = 0x1E,         /* secondary status */
  112         PciMBR          = 0x20,         /* memory base */
  113         PciMLR          = 0x22,         /* memory limit */
  114         PciPMBR         = 0x24,         /* prefetchable memory base */
  115         PciPMLR         = 0x26,         /* prefetchable memory limit */
  116         PciPUBR         = 0x28,         /* prefetchable base upper 32 bits */
  117         PciPULR         = 0x2C,         /* prefetchable limit upper 32 bits */
  118         PciIUBR         = 0x30,         /* I/O base upper 16 bits */
  119         PciIULR         = 0x32,         /* I/O limit upper 16 bits */
  120         PciEBAR1        = 0x28,         /* expansion ROM base address */
  121         PciBCR          = 0x3E,         /* bridge control register */
  122 };
  123 
  124 typedef struct Pcidev Pcidev;
  125 typedef struct Pcidev {
  126         int     tbdf;                   /* type+bus+device+function */
  127         ushort  vid;                    /* vendor ID */
  128         ushort  did;                    /* device ID */
  129 
  130         ushort  pcr;
  131 
  132         uchar   rid;
  133         uchar   ccrp;
  134         uchar   ccru;
  135         uchar   ccrb;
  136         uchar   cls;
  137         uchar   ltr;
  138 
  139         struct {
  140                 ulong   bar;            /* base address */
  141                 int     size;
  142         } mem[6];
  143 
  144         uchar   intl;                   /* interrupt line */
  145 
  146         Pcidev* list;
  147         Pcidev* link;                   /* next device on this bno */
  148 
  149         Pcidev* bridge;                 /* down a bus */
  150         struct {
  151                 ulong   bar;
  152                 int     size;
  153         } ioa, mema;
  154 
  155         int     pmrb;                   /* power management register block */
  156 };
  157 
  158 #define PCIWINDOW       0x40000000
  159 #define PCIWADDR(va)    (PADDR(va)+PCIWINDOW)
  160 #define ISAWINDOW       0x00800000
  161 #define ISAWADDR(va)    (PADDR(va)+ISAWINDOW)
  162 
  163 /*
  164  * PCMCIA support code.
  165  */
  166 /*
  167  * Map between ISA memory space and PCMCIA card memory space.
  168  */
  169 struct PCMmap {
  170         ulong   ca;                     /* card address */
  171         ulong   cea;                    /* card end address */
  172         ulong   isa;                    /* ISA address */
  173         int     len;                    /* length of the ISA area */
  174         int     attr;                   /* attribute memory */
  175         int     ref;
  176 };

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FreeBSD/Linux Kernel Cross Reference sys/alphapc/io.h

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sys/alphapc/io.h