sd53c8xx.c

Version: - FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
    1 /*
    2  * NCR/Symbios/LSI Logic 53c8xx driver for Plan 9
    3  * Nigel Roles (nigel@9fs.org)
    4  *
    5  * 27/5/02      Fixed problems with transfers >= 256 * 512
    6  *
    7  * 13/3/01      Fixed microcode to support targets > 7
    8  *
    9  * 01/12/00     Removed previous comments. Fixed a small problem in
   10  *                      mismatch recovery for targets with synchronous offsets of >=16
   11  *                      connected to >=875s. Thanks, Jean.
   12  *
   13  * Known problems
   14  *
   15  * Read/write mismatch recovery may fail on 53c1010s. Really need to get a manual.
   16  */
   17 
   18 #define MAXTARGET       16              /* can be 8 or 16 */
   19 
   20 #include "u.h"
   21 #include "../port/lib.h"
   22 #include "mem.h"
   23 #include "dat.h"
   24 #include "fns.h"
   25 #include "io.h"
   26 
   27 #include "../port/sd.h"
   28 extern SDifc sd53c8xxifc;
   29 
   30 /**********************************/
   31 /* Portable configuration macros  */
   32 /**********************************/
   33 
   34 //#define BOOTDEBUG
   35 //#define ASYNC_ONLY
   36 //#define       INTERNAL_SCLK
   37 //#define ALWAYS_DO_WDTR
   38 #define WMR_DEBUG
   39 
   40 /**********************************/
   41 /* CPU specific macros            */
   42 /**********************************/
   43 
   44 #define PRINTPREFIX "sd53c8xx: "
   45 
   46 #ifdef BOOTDEBUG
   47 
   48 #define KPRINT oprint
   49 #define IPRINT intrprint
   50 #define DEBUG(n) 1
   51 #define IFLUSH() iflush()
   52 
   53 #else
   54 
   55 static int idebug = 1;
   56 #define KPRINT  if(0) iprint
   57 #define IPRINT  if(idebug) iprint
   58 #define DEBUG(n)        (0)
   59 #define IFLUSH()
   60 
   61 #endif /* BOOTDEBUG */
   62 
   63 /*******************************/
   64 /* General                     */
   65 /*******************************/
   66 
   67 #ifndef DMASEG
   68 #define DMASEG(x) PCIWADDR(x)
   69 #define legetl(x) (*(ulong*)(x))
   70 #define lesetl(x,v) (*(ulong*)(x) = (v))
   71 #define swabl(a,b,c)
   72 #else
   73 #endif /*DMASEG */
   74 #define DMASEG_TO_KADDR(x) KADDR((x)-PCIWINDOW)
   75 #define KPTR(x) ((x) == 0 ? 0 : DMASEG_TO_KADDR(x))
   76 
   77 #define MEGA 1000000L
   78 #ifdef INTERNAL_SCLK
   79 #define SCLK (33 * MEGA)
   80 #else
   81 #define SCLK (40 * MEGA)
   82 #endif /* INTERNAL_SCLK */
   83 #define ULTRA_NOCLOCKDOUBLE_SCLK (80 * MEGA)
   84 
   85 #define MAXSYNCSCSIRATE (5 * MEGA)
   86 #define MAXFASTSYNCSCSIRATE (10 * MEGA)
   87 #define MAXULTRASYNCSCSIRATE (20 * MEGA)
   88 #define MAXULTRA2SYNCSCSIRATE (40 * MEGA)
   89 #define MAXASYNCCORERATE (25 * MEGA)
   90 #define MAXSYNCCORERATE (25 * MEGA)
   91 #define MAXFASTSYNCCORERATE (50 * MEGA)
   92 #define MAXULTRASYNCCORERATE (80 * MEGA)
   93 #define MAXULTRA2SYNCCORERATE (160 * MEGA)
   94 
   95 
   96 #define X_MSG   1
   97 #define X_MSG_SDTR 1
   98 #define X_MSG_WDTR 3
   99 
  100 struct na_patch {
  101         unsigned lwoff;
  102         unsigned char type;
  103 };
  104 
  105 typedef struct Ncr {
  106         uchar scntl0;   /* 00 */
  107         uchar scntl1;
  108         uchar scntl2;
  109         uchar scntl3;
  110 
  111         uchar scid;     /* 04 */
  112         uchar sxfer;
  113         uchar sdid;
  114         uchar gpreg;
  115 
  116         uchar sfbr;     /* 08 */
  117         uchar socl;
  118         uchar ssid;
  119         uchar sbcl;
  120 
  121         uchar dstat;    /* 0c */
  122         uchar sstat0;
  123         uchar sstat1;
  124         uchar sstat2;
  125 
  126         uchar dsa[4];   /* 10 */
  127 
  128         uchar istat;    /* 14 */
  129         uchar istatpad[3];
  130 
  131         uchar ctest0;   /* 18 */
  132         uchar ctest1;
  133         uchar ctest2;
  134         uchar ctest3;
  135 
  136         uchar temp[4];  /* 1c */
  137 
  138         uchar dfifo;    /* 20 */
  139         uchar ctest4;
  140         uchar ctest5;
  141         uchar ctest6;
  142 
  143         uchar dbc[3];   /* 24 */
  144         uchar dcmd;     /* 27 */
  145 
  146         uchar dnad[4];  /* 28 */
  147         uchar dsp[4];   /* 2c */
  148         uchar dsps[4];  /* 30 */
  149 
  150         uchar scratcha[4];      /* 34 */
  151 
  152         uchar dmode;    /* 38 */
  153         uchar dien;
  154         uchar dwt;
  155         uchar dcntl;
  156 
  157         uchar adder[4]; /* 3c */
  158 
  159         uchar sien0;    /* 40 */
  160         uchar sien1;
  161         uchar sist0;
  162         uchar sist1;
  163 
  164         uchar slpar;    /* 44 */
  165         uchar slparpad0;
  166         uchar macntl;
  167         uchar gpcntl;
  168 
  169         uchar stime0;   /* 48 */
  170         uchar stime1;
  171         uchar respid;
  172         uchar respidpad0;
  173 
  174         uchar stest0;   /* 4c */
  175         uchar stest1;
  176         uchar stest2;
  177         uchar stest3;
  178 
  179         uchar sidl;     /* 50 */
  180         uchar sidlpad[3];
  181 
  182         uchar sodl;     /* 54 */
  183         uchar sodlpad[3];
  184 
  185         uchar sbdl;     /* 58 */
  186         uchar sbdlpad[3];
  187 
  188         uchar scratchb[4];      /* 5c */
  189 } Ncr;
  190 
  191 typedef struct Movedata {
  192         uchar dbc[4];
  193         uchar pa[4];
  194 } Movedata;
  195 
  196 typedef enum NegoState {
  197         NeitherDone, WideInit, WideResponse, WideDone,
  198         SyncInit, SyncResponse, BothDone
  199 } NegoState;
  200 
  201 typedef enum State {
  202         Allocated, Queued, Active, Done
  203 } State;
  204 
  205 typedef struct Dsa {
  206         uchar stateb;
  207         uchar result;
  208         uchar dmablks;
  209         uchar flag;     /* setbyte(state,3,...) */
  210 
  211         union {
  212                 ulong dmancr;           /* For block transfer: NCR order (little-endian) */
  213                 uchar dmaaddr[4];
  214         };
  215 
  216         uchar target;                   /* Target */
  217         uchar pad0[3];
  218 
  219         uchar lun;                      /* Logical Unit Number */
  220         uchar pad1[3];
  221 
  222         uchar scntl3;
  223         uchar sxfer;
  224         uchar pad2[2];
  225 
  226         uchar next[4];                  /* chaining for SCRIPT (NCR byte order) */
  227         struct Dsa *freechain;          /* chaining for freelist */
  228         Rendez;
  229         uchar scsi_id_buf[4];
  230         Movedata msg_out_buf;
  231         Movedata cmd_buf;
  232         Movedata data_buf;
  233         Movedata status_buf;
  234         uchar msg_out[10];              /* enough to include SDTR */
  235         uchar status;
  236         int p9status;
  237         uchar parityerror;
  238 } Dsa;
  239 
  240 typedef enum Feature {
  241         BigFifo = 1,                    /* 536 byte fifo */
  242         BurstOpCodeFetch = 2,           /* burst fetch opcodes */
  243         Prefetch = 4,                   /* prefetch 8 longwords */
  244         LocalRAM = 8,                   /* 4K longwords of local RAM */
  245         Differential = 16,              /* Differential support */
  246         Wide = 32,                      /* Wide capable */
  247         Ultra = 64,                     /* Ultra capable */
  248         ClockDouble = 128,              /* Has clock doubler */
  249         ClockQuad = 256,                /* Has clock quadrupler (same as Ultra2) */
  250         Ultra2 = 256,
  251 } Feature;
  252 
  253 typedef enum Burst {
  254         Burst2 = 0,
  255         Burst4 = 1,
  256         Burst8 = 2,
  257         Burst16 = 3,
  258         Burst32 = 4,
  259         Burst64 = 5,
  260         Burst128 = 6
  261 } Burst;
  262 
  263 typedef struct Variant {
  264         ushort did;
  265         uchar maxrid;                   /* maximum allowed revision ID */
  266         char *name;
  267         Burst burst;                    /* codings for max burst */
  268         uchar maxsyncoff;               /* max synchronous offset */
  269         uchar registers;                /* number of 32 bit registers */
  270         unsigned feature;
  271 } Variant;
  272 
  273 static unsigned char cf2[] = { 6, 2, 3, 4, 6, 8, 12, 16 };
  274 #define NULTRA2SCF (sizeof(cf2)/sizeof(cf2[0]))
  275 #define NULTRASCF (NULTRA2SCF - 2)
  276 #define NSCF (NULTRASCF - 1)
  277 
  278 typedef struct Controller {
  279         Lock;
  280         struct {
  281                 uchar scntl3;
  282                 uchar stest2;
  283         } bios;
  284         uchar synctab[NULTRA2SCF - 1][8];/* table of legal tpfs */
  285         NegoState s[MAXTARGET];
  286         uchar scntl3[MAXTARGET];
  287         uchar sxfer[MAXTARGET];
  288         uchar cap[MAXTARGET];           /* capabilities byte from Identify */
  289         ushort capvalid;                /* bit per target for validity of cap[] */
  290         ushort wide;                    /* bit per target set if wide negotiated */
  291         ulong sclk;                     /* clock speed of controller */
  292         uchar clockmult;                /* set by synctabinit */
  293         uchar ccf;                      /* CCF bits */
  294         uchar tpf;                      /* best tpf value for this controller */
  295         uchar feature;                  /* requested features */
  296         int running;                    /* is the script processor running? */
  297         int ssm;                        /* single step mode */
  298         Ncr *n;                         /* pointer to registers */
  299         Variant *v;                     /* pointer to variant type */
  300         ulong *script;                  /* where the real script is */
  301         ulong scriptpa;                 /* where the real script is */
  302         Pcidev* pcidev;
  303         SDev*   sdev;
  304 
  305         struct {
  306                 Lock;
  307                 uchar head[4];          /* head of free list (NCR byte order) */
  308                 Dsa     *freechain;
  309         } dsalist;
  310 
  311         QLock q[MAXTARGET];             /* queues for each target */
  312 } Controller;
  313 
  314 #define SYNCOFFMASK(c)          (((c)->v->maxsyncoff * 2) - 1)
  315 #define SSIDMASK(c)             (((c)->v->feature & Wide) ? 15 : 7)
  316 
  317 /* ISTAT */
  318 enum { Abrt = 0x80, Srst = 0x40, Sigp = 0x20, Sem = 0x10, Con = 0x08, Intf = 0x04, Sip = 0x02, Dip = 0x01 };
  319 
  320 /* DSTAT */
  321 enum { Dfe = 0x80, Mdpe = 0x40, Bf = 0x20, Abrted = 0x10, Ssi = 0x08, Sir = 0x04, Iid = 0x01 };
  322 
  323 /* SSTAT */
  324 enum { DataOut, DataIn, Cmd, Status, ReservedOut, ReservedIn, MessageOut, MessageIn };
  325 
  326 static void setmovedata(Movedata*, ulong, ulong);
  327 static void advancedata(Movedata*, long);
  328 static int bios_set_differential(Controller *c);
  329 
  330 static char *phase[] = {
  331         "data out", "data in", "command", "status",
  332         "reserved out", "reserved in", "message out", "message in"
  333 };
  334 
  335 #ifdef BOOTDEBUG
  336 #define DEBUGSIZE 10240
  337 char debugbuf[DEBUGSIZE];
  338 char *debuglast;
  339 
  340 static void
  341 intrprint(char *format, ...)
  342 {
  343         if (debuglast == 0)
  344                 debuglast = debugbuf;
  345         debuglast = vseprint(debuglast, debugbuf + (DEBUGSIZE - 1), format, (&format + 1));
  346 }
  347 
  348 static void
  349 iflush()
  350 {
  351         int s;
  352         char *endp;
  353         s = splhi();
  354         if (debuglast == 0)
  355                 debuglast = debugbuf;
  356         if (debuglast == debugbuf) {
  357                 splx(s);
  358                 return;
  359         }
  360         endp = debuglast;
  361         splx(s);
  362         screenputs(debugbuf, endp - debugbuf);
  363         s = splhi();
  364         memmove(debugbuf, endp, debuglast - endp);
  365         debuglast -= endp - debugbuf;
  366         splx(s);
  367 }
  368 
  369 static void
  370 oprint(char *format, ...)
  371 {
  372         int s;
  373 
  374         iflush();
  375         s = splhi();
  376         if (debuglast == 0)
  377                 debuglast = debugbuf;
  378         debuglast = vseprint(debuglast, debugbuf + (DEBUGSIZE - 1), format, (&format + 1));
  379         splx(s);
  380         iflush();       
  381 }
  382 #endif
  383 
  384 #include "sd53c8xx.i"
  385 
  386 /*
  387  * We used to use a linked list of Dsas with nil as the terminator,
  388  * but occasionally the 896 card seems not to notice that the 0
  389  * is really a 0, and then it tries to reference the Dsa at address 0.
  390  * To address this, we use a sentinel dsa that links back to itself
  391  * and has state A_STATE_END.  If the card takes an iteration or
  392  * two to notice that the state says A_STATE_END, that's no big 
  393  * deal.  Clearly this isn't the right approach, but I'm just
  394  * stumped.  Even with this, we occasionally get prints about
  395  * "WSR set", usually with about the same frequency that the
  396  * card used to walk past 0. 
  397  */
  398 static Dsa *dsaend;
  399 
  400 static Dsa*
  401 dsaallocnew(Controller *c)
  402 {
  403         Dsa *d;
  404         
  405         /* c->dsalist must be ilocked */
  406         d = xalloc(sizeof *d);
  407         lesetl(d->next, legetl(c->dsalist.head));
  408         lesetl(&d->stateb, A_STATE_FREE);
  409         coherence();
  410         lesetl(c->dsalist.head, DMASEG(d));
  411         coherence();
  412         return d;
  413 }
  414 
  415 static Dsa *
  416 dsaalloc(Controller *c, int target, int lun)
  417 {
  418         Dsa *d;
  419 
  420         ilock(&c->dsalist);
  421         if ((d = c->dsalist.freechain) != 0) {
  422                 if (DEBUG(1))
  423                         IPRINT(PRINTPREFIX "%d/%d: reused dsa %lux\n", target, lun, (ulong)d);
  424         } else {        
  425                 d = dsaallocnew(c);
  426                 if (DEBUG(1))
  427                         IPRINT(PRINTPREFIX "%d/%d: allocated dsa %lux\n", target, lun, (ulong)d);
  428         }
  429         c->dsalist.freechain = d->freechain;
  430         lesetl(&d->stateb, A_STATE_ALLOCATED);
  431         iunlock(&c->dsalist);
  432         d->target = target;
  433         d->lun = lun;
  434         return d;
  435 }
  436 
  437 static void
  438 dsafree(Controller *c, Dsa *d)
  439 {
  440         ilock(&c->dsalist);
  441         d->freechain = c->dsalist.freechain;
  442         c->dsalist.freechain = d;
  443         lesetl(&d->stateb, A_STATE_FREE);
  444         iunlock(&c->dsalist);
  445 }
  446 
  447 static void
  448 dsadump(Controller *c)
  449 {
  450         Dsa *d;
  451         u32int *a;
  452         
  453         iprint("dsa controller list: c=%p head=%.8lux\n", c, legetl(c->dsalist.head));
  454         for(d=KPTR(legetl(c->dsalist.head)); d != dsaend; d=KPTR(legetl(d->next))){
  455                 if(d == (void*)-1){
  456                         iprint("\t dsa %p\n", d);
  457                         break;
  458                 }
  459                 a = (u32int*)d;
  460                 iprint("\tdsa %p %.8ux %.8ux %.8ux %.8ux %.8ux %.8ux\n", a, a[0], a[1], a[2], a[3], a[4], a[5]);
  461         }
  462 
  463 /*
  464         a = KPTR(c->scriptpa+E_dsa_addr);
  465         iprint("dsa_addr: %.8ux %.8ux %.8ux %.8ux %.8ux\n",
  466                 a[0], a[1], a[2], a[3], a[4]);
  467         a = KPTR(c->scriptpa+E_issue_addr);
  468         iprint("issue_addr: %.8ux %.8ux %.8ux %.8ux %.8ux\n",
  469                 a[0], a[1], a[2], a[3], a[4]);
  470 
  471         a = KPTR(c->scriptpa+E_issue_test_begin);
  472         e = KPTR(c->scriptpa+E_issue_test_end);
  473         iprint("issue_test code (at offset %.8ux):\n", E_issue_test_begin);
  474         
  475         i = 0;
  476         for(; a<e; a++){
  477                 iprint(" %.8ux", *a);
  478                 if(++i%8 == 0)
  479                         iprint("\n");
  480         }
  481         if(i%8)
  482                 iprint("\n");
  483 */
  484 }
  485 
  486 static Dsa *
  487 dsafind(Controller *c, uchar target, uchar lun, uchar state)
  488 {
  489         Dsa *d;
  490         for (d = KPTR(legetl(c->dsalist.head)); d != dsaend; d = KPTR(legetl(d->next))) {
  491                 if (d->target != 0xff && d->target != target)
  492                         continue;
  493                 if (lun != 0xff && d->lun != lun)
  494                         continue;
  495                 if (state != 0xff && d->stateb != state)
  496                         continue;
  497                 break;
  498         }
  499         return d;
  500 }
  501 
  502 static void
  503 dumpncrregs(Controller *c, int intr)
  504 {
  505         int i;
  506         Ncr *n = c->n;
  507         int depth = c->v->registers / 4;
  508 
  509         if (intr) {
  510                 IPRINT("sa = %.8lux\n", c->scriptpa);
  511         }
  512         else {
  513                 KPRINT("sa = %.8lux\n", c->scriptpa);
  514         }
  515         for (i = 0; i < depth; i++) {
  516                 int j;
  517                 for (j = 0; j < 4; j++) {
  518                         int k = j * depth + i;
  519                         uchar *p;
  520 
  521                         /* display little-endian to make 32-bit values readable */
  522                         p = (uchar*)n+k*4;
  523                         if (intr) {
  524                                 IPRINT(" %.2x%.2x%.2x%.2x %.2x %.2x", p[3], p[2], p[1], p[0], k * 4, (k * 4) + 0x80);
  525                         }
  526                         else {
  527                                 KPRINT(" %.2x%.2x%.2x%.2x %.2x %.2x", p[3], p[2], p[1], p[0], k * 4, (k * 4) + 0x80);
  528                         }
  529                         USED(p);
  530                 }
  531                 if (intr) {
  532                         IPRINT("\n");
  533                 }
  534                 else {
  535                         KPRINT("\n");
  536                 }
  537         }
  538 }       
  539 
  540 static int
  541 chooserate(Controller *c, int tpf, int *scfp, int *xferpp)
  542 {
  543         /* find lowest entry >= tpf */
  544         int besttpf = 1000;
  545         int bestscfi = 0;
  546         int bestxferp = 0;
  547         int scf, xferp;
  548         int maxscf;
  549 
  550         if (c->v->feature & Ultra2)
  551                 maxscf = NULTRA2SCF;
  552         else if (c->v->feature & Ultra)
  553                 maxscf = NULTRASCF;
  554         else
  555                 maxscf = NSCF;
  556 
  557         /*
  558          * search large clock factors first since this should
  559          * result in more reliable transfers
  560          */
  561         for (scf = maxscf; scf >= 1; scf--) {
  562                 for (xferp = 0; xferp < 8; xferp++) {
  563                         unsigned char v = c->synctab[scf - 1][xferp];
  564                         if (v == 0)
  565                                 continue;
  566                         if (v >= tpf && v < besttpf) {
  567                                 besttpf = v;
  568                                 bestscfi = scf;
  569                                 bestxferp = xferp;
  570                         }
  571                 }
  572         }
  573         if (besttpf == 1000)
  574                 return 0;
  575         if (scfp)
  576                 *scfp = bestscfi;
  577         if (xferpp)
  578                 *xferpp = bestxferp;
  579         return besttpf;
  580 }
  581 
  582 static void
  583 synctabinit(Controller *c)
  584 {
  585         int scf;
  586         unsigned long scsilimit;
  587         int xferp;
  588         unsigned long cr, sr;
  589         int tpf;
  590         int fast;
  591         int maxscf;
  592 
  593         if (c->v->feature & Ultra2)
  594                 maxscf = NULTRA2SCF;
  595         else if (c->v->feature & Ultra)
  596                 maxscf = NULTRASCF;
  597         else
  598                 maxscf = NSCF;
  599 
  600         /*
  601          * for chips with no clock doubler, but Ultra capable (e.g. 860, or interestingly the
  602          * first spin of the 875), assume 80MHz
  603          * otherwise use the internal (33 Mhz) or external (40MHz) default
  604          */
  605 
  606         if ((c->v->feature & Ultra) != 0 && (c->v->feature & (ClockDouble | ClockQuad)) == 0)
  607                 c->sclk = ULTRA_NOCLOCKDOUBLE_SCLK;
  608         else
  609                 c->sclk = SCLK;
  610 
  611         /*
  612          * otherwise, if the chip is Ultra capable, but has a slow(ish) clock,
  613          * invoke the doubler
  614          */
  615 
  616         if (SCLK <= 40000000) {
  617                 if (c->v->feature & ClockDouble) {
  618                         c->sclk *= 2;
  619                         c->clockmult = 1;
  620                 }
  621                 else if (c->v->feature & ClockQuad) {
  622                         c->sclk *= 4;
  623                         c->clockmult = 1;
  624                 }
  625                 else
  626                         c->clockmult = 0;
  627         }
  628         else
  629                 c->clockmult = 0;
  630 
  631         /* derive CCF from sclk */
  632         /* woebetide anyone with SCLK < 16.7 or > 80MHz */
  633         if (c->sclk <= 25 * MEGA)
  634                 c->ccf = 1;
  635         else if (c->sclk <= 3750000)
  636                 c->ccf = 2;
  637         else if (c->sclk <= 50 * MEGA)
  638                 c->ccf = 3;
  639         else if (c->sclk <= 75 * MEGA)
  640                 c->ccf = 4;
  641         else if ((c->v->feature & ClockDouble) && c->sclk <= 80 * MEGA)
  642                 c->ccf = 5;
  643         else if ((c->v->feature & ClockQuad) && c->sclk <= 120 * MEGA)
  644                 c->ccf = 6;
  645         else if ((c->v->feature & ClockQuad) && c->sclk <= 160 * MEGA)
  646                 c->ccf = 7;
  647 
  648         for (scf = 1; scf < maxscf; scf++) {
  649                 /* check for legal core rate */
  650                 /* round up so we run slower for safety */
  651                 cr = (c->sclk * 2 + cf2[scf] - 1) / cf2[scf];
  652                 if (cr <= MAXSYNCCORERATE) {
  653                         scsilimit = MAXSYNCSCSIRATE;
  654                         fast = 0;
  655                 }
  656                 else if (cr <= MAXFASTSYNCCORERATE) {
  657                         scsilimit = MAXFASTSYNCSCSIRATE;
  658                         fast = 1;
  659                 }
  660                 else if ((c->v->feature & Ultra) && cr <= MAXULTRASYNCCORERATE) {
  661                         scsilimit = MAXULTRASYNCSCSIRATE;
  662                         fast = 2;
  663                 }
  664                 else if ((c->v->feature & Ultra2) && cr <= MAXULTRA2SYNCCORERATE) {
  665                         scsilimit = MAXULTRA2SYNCSCSIRATE;
  666                         fast = 3;
  667                 }
  668                 else
  669                         continue;
  670                 for (xferp = 11; xferp >= 4; xferp--) {
  671                         int ok;
  672                         int tp;
  673                         /* calculate scsi rate - round up again */
  674                         /* start from sclk for accuracy */
  675                         int totaldivide = xferp * cf2[scf];
  676                         sr = (c->sclk * 2 + totaldivide - 1) / totaldivide;
  677                         if (sr > scsilimit)
  678                                 break;
  679                         /*
  680                          * now work out transfer period
  681                          * round down now so that period is pessimistic
  682                          */
  683                         tp = (MEGA * 1000) / sr;
  684                         /*
  685                          * bounds check it
  686                          */
  687                         if (tp < 25 || tp > 255 * 4)
  688                                 continue;
  689                         /*
  690                          * spot stupid special case for Ultra or Ultra2
  691                          * while working out factor
  692                          */
  693                         if (tp == 25)
  694                                 tpf = 10;
  695                         else if (tp == 50)
  696                                 tpf = 12;
  697                         else if (tp < 52)
  698                                 continue;
  699                         else
  700                                 tpf = tp / 4;
  701                         /*
  702                          * now check tpf looks sensible
  703                          * given core rate
  704                          */
  705                         switch (fast) {
  706                         case 0:
  707                                 /* scf must be ccf for SCSI 1 */
  708                                 ok = tpf >= 50 && scf == c->ccf;
  709                                 break;
  710                         case 1:
  711                                 ok = tpf >= 25 && tpf < 50;
  712                                 break;
  713                         case 2:
  714                                 /*
  715                                  * must use xferp of 4, or 5 at a pinch
  716                                  * for an Ultra transfer
  717                                  */
  718                                 ok = xferp <= 5 && tpf >= 12 && tpf < 25;
  719                                 break;
  720                         case 3:
  721                                 ok = xferp == 4 && (tpf == 10 || tpf == 11);
  722                                 break;
  723                         default:
  724                                 ok = 0;
  725                         }
  726                         if (!ok)
  727                                 continue;
  728                         c->synctab[scf - 1][xferp - 4] = tpf;
  729                 }
  730         }
  731 
  732 #ifndef NO_ULTRA2
  733         if (c->v->feature & Ultra2)
  734                 tpf = 10;
  735         else
  736 #endif
  737         if (c->v->feature & Ultra)
  738                 tpf = 12;
  739         else
  740                 tpf = 25;
  741         for (; tpf < 256; tpf++) {
  742                 if (chooserate(c, tpf, &scf, &xferp) == tpf) {
  743                         unsigned tp = tpf == 10 ? 25 : (tpf == 12 ? 50 : tpf * 4);
  744                         unsigned long khz = (MEGA + tp - 1) / (tp);
  745                         KPRINT(PRINTPREFIX "tpf=%d scf=%d.%.1d xferp=%d mhz=%ld.%.3ld\n",
  746                             tpf, cf2[scf] / 2, (cf2[scf] & 1) ? 5 : 0,
  747                             xferp + 4, khz / 1000, khz % 1000);
  748                         USED(khz);
  749                         if (c->tpf == 0)
  750                                 c->tpf = tpf;   /* note lowest value for controller */
  751                 }
  752         }
  753 }
  754 
  755 static void
  756 synctodsa(Dsa *dsa, Controller *c)
  757 {
  758 /*
  759         KPRINT("synctodsa(dsa=%lux, target=%d, scntl3=%.2lx sxfer=%.2x)\n",
  760             dsa, dsa->target, c->scntl3[dsa->target], c->sxfer[dsa->target]);
  761 */
  762         dsa->scntl3 = c->scntl3[dsa->target];
  763         dsa->sxfer = c->sxfer[dsa->target];
  764 }
  765 
  766 static void
  767 setsync(Dsa *dsa, Controller *c, int target, uchar ultra, uchar scf, uchar xferp, uchar reqack)
  768 {
  769         c->scntl3[target] =
  770             (c->scntl3[target] & 0x08) | (((scf << 4) | c->ccf | (ultra << 7)) & ~0x08);
  771         c->sxfer[target] = (xferp << 5) | reqack;
  772         c->s[target] = BothDone;
  773         if (dsa) {
  774                 synctodsa(dsa, c);
  775                 c->n->scntl3 = c->scntl3[target];
  776                 c->n->sxfer = c->sxfer[target];
  777         }
  778 }
  779 
  780 static void
  781 setasync(Dsa *dsa, Controller *c, int target)
  782 {
  783         setsync(dsa, c, target, 0, c->ccf, 0, 0);
  784 }
  785 
  786 static void
  787 setwide(Dsa *dsa, Controller *c, int target, uchar wide)
  788 {
  789         c->scntl3[target] = wide ? (1 << 3) : 0;
  790         setasync(dsa, c, target);
  791         c->s[target] = WideDone;
  792 }
  793 
  794 static int
  795 buildsdtrmsg(uchar *buf, uchar tpf, uchar offset)
  796 {
  797         *buf++ = X_MSG;
  798         *buf++ = 3;
  799         *buf++ = X_MSG_SDTR;
  800         *buf++ = tpf;
  801         *buf = offset;
  802         return 5;
  803 }
  804 
  805 static int
  806 buildwdtrmsg(uchar *buf, uchar expo)
  807 {
  808         *buf++ = X_MSG;
  809         *buf++ = 2;
  810         *buf++ = X_MSG_WDTR;
  811         *buf = expo;
  812         return 4;
  813 }
  814 
  815 static void
  816 start(Controller *c, long entry)
  817 {
  818         ulong p;
  819 
  820         if (c->running)
  821                 panic(PRINTPREFIX "start called while running");
  822         c->running = 1;
  823         p = c->scriptpa + entry;
  824         lesetl(c->n->dsp, p);
  825         coherence();
  826         if (c->ssm)
  827                 c->n->dcntl |= 0x4;             /* start DMA in SSI mode */
  828 }
  829 
  830 static void
  831 ncrcontinue(Controller *c)
  832 {
  833         if (c->running)
  834                 panic(PRINTPREFIX "ncrcontinue called while running");
  835         /* set the start DMA bit to continue execution */
  836         c->running = 1;
  837         coherence();
  838         c->n->dcntl |= 0x4;
  839 }
  840 
  841 static void
  842 softreset(Controller *c)
  843 {
  844         Ncr *n = c->n;
  845 
  846         n->istat = Srst;                /* software reset */
  847         n->istat = 0;
  848         /* general initialisation */
  849         n->scid = (1 << 6) | 7;         /* respond to reselect, ID 7 */
  850         n->respid = 1 << 7;             /* response ID = 7 */
  851 
  852 #ifdef INTERNAL_SCLK
  853         n->stest1 = 0x80;               /* disable external scsi clock */
  854 #else
  855         n->stest1 = 0x00;
  856 #endif
  857 
  858         n->stime0 = 0xdd;               /* about 0.5 second timeout on each device */
  859         n->scntl0 |= 0x8;               /* Enable parity checking */
  860 
  861         /* continued setup */
  862         n->sien0 = 0x8f;
  863         n->sien1 = 0x04;
  864         n->dien = 0x7d;
  865         n->stest3 = 0x80;               /* TolerANT enable */
  866         c->running = 0;
  867 
  868         if (c->v->feature & BigFifo)
  869                 n->ctest5 = (1 << 5);
  870         n->dmode = c->v->burst << 6;    /* set burst length bits */
  871         if (c->v->burst & 4)
  872                 n->ctest5 |= (1 << 2);  /* including overflow into ctest5 bit 2 */
  873         if (c->v->feature & Prefetch)
  874                 n->dcntl |= (1 << 5);   /* prefetch enable */
  875         else if (c->v->feature & BurstOpCodeFetch)
  876                 n->dmode |= (1 << 1);   /* burst opcode fetch */
  877         if (c->v->feature & Differential) {
  878                 /* chip capable */
  879                 if ((c->feature & Differential) || bios_set_differential(c)) {
  880                         /* user enabled, or some evidence bios set differential */
  881                         if (n->sstat2 & (1 << 2))
  882                                 print(PRINTPREFIX "can't go differential; wrong cable\n");
  883                         else {
  884                                 n->stest2 = (1 << 5);
  885                                 print(PRINTPREFIX "differential mode set\n");
  886                         }
  887                 }
  888         }
  889         if (c->clockmult) {
  890                 n->stest1 |= (1 << 3);  /* power up doubler */
  891                 delay(2);
  892                 n->stest3 |= (1 << 5);  /* stop clock */
  893                 n->stest1 |= (1 << 2);  /* enable doubler */
  894                 n->stest3 &= ~(1 << 5); /* start clock */
  895                 /* pray */
  896         }
  897 }
  898 
  899 static void
  900 msgsm(Dsa *dsa, Controller *c, int msg, int *cont, int *wakeme)
  901 {
  902         uchar histpf, hisreqack;
  903         int tpf;
  904         int scf, xferp;
  905         int len;
  906 
  907         Ncr *n = c->n;
  908 
  909         switch (c->s[dsa->target]) {
  910         case SyncInit:
  911                 switch (msg) {
  912                 case A_SIR_MSG_SDTR:
  913                         /* reply to my SDTR */
  914                         histpf = n->scratcha[2];
  915                         hisreqack = n->scratcha[3];
  916                         KPRINT(PRINTPREFIX "%d: SDTN response %d %d\n",
  917                             dsa->target, histpf, hisreqack);
  918 
  919                         if (hisreqack == 0)
  920                                 setasync(dsa, c, dsa->target);
  921                         else {
  922                                 /* hisreqack should be <= c->v->maxsyncoff */
  923                                 tpf = chooserate(c, histpf, &scf, &xferp);
  924                                 KPRINT(PRINTPREFIX "%d: SDTN: using %d %d\n",
  925                                     dsa->target, tpf, hisreqack);
  926                                 setsync(dsa, c, dsa->target, tpf < 25, scf, xferp, hisreqack);
  927                         }
  928                         *cont = -2;
  929                         return;
  930                 case A_SIR_EV_PHASE_SWITCH_AFTER_ID:
  931                         /* target ignored ATN for message after IDENTIFY - not SCSI-II */
  932                         KPRINT(PRINTPREFIX "%d: illegal phase switch after ID message - SCSI-1 device?\n", dsa->target);
  933                         KPRINT(PRINTPREFIX "%d: SDTN: async\n", dsa->target);
  934                         setasync(dsa, c, dsa->target);
  935                         *cont = E_to_decisions;
  936                         return;
  937                 case A_SIR_MSG_REJECT:
  938                         /* rejection of my SDTR */
  939                         KPRINT(PRINTPREFIX "%d: SDTN: rejected SDTR\n", dsa->target);
  940                 //async:
  941                         KPRINT(PRINTPREFIX "%d: SDTN: async\n", dsa->target);
  942                         setasync(dsa, c, dsa->target);
  943                         *cont = -2;
  944                         return;
  945                 }
  946                 break;
  947         case WideInit:
  948                 switch (msg) {
  949                 case A_SIR_MSG_WDTR:
  950                         /* reply to my WDTR */
  951                         KPRINT(PRINTPREFIX "%d: WDTN: response %d\n",
  952                             dsa->target, n->scratcha[2]);
  953                         setwide(dsa, c, dsa->target, n->scratcha[2]);
  954                         *cont = -2;
  955                         return;
  956                 case A_SIR_EV_PHASE_SWITCH_AFTER_ID:
  957                         /* target ignored ATN for message after IDENTIFY - not SCSI-II */
  958                         KPRINT(PRINTPREFIX "%d: illegal phase switch after ID message - SCSI-1 device?\n", dsa->target);
  959                         setwide(dsa, c, dsa->target, 0);
  960                         *cont = E_to_decisions;
  961                         return;
  962                 case A_SIR_MSG_REJECT:
  963                         /* rejection of my SDTR */
  964                         KPRINT(PRINTPREFIX "%d: WDTN: rejected WDTR\n", dsa->target);
  965                         setwide(dsa, c, dsa->target, 0);
  966                         *cont = -2;
  967                         return;
  968                 }
  969                 break;
  970 
  971         case NeitherDone:
  972         case WideDone:
  973         case BothDone:
  974                 switch (msg) {
  975                 case A_SIR_MSG_WDTR: {
  976                         uchar hiswide, mywide;
  977                         hiswide = n->scratcha[2];
  978                         mywide = (c->v->feature & Wide) != 0;
  979                         KPRINT(PRINTPREFIX "%d: WDTN: target init %d\n",
  980                             dsa->target, hiswide);
  981                         if (hiswide < mywide)
  982                                 mywide = hiswide;
  983                         KPRINT(PRINTPREFIX "%d: WDTN: responding %d\n",
  984                             dsa->target, mywide);
  985                         setwide(dsa, c, dsa->target, mywide);
  986                         len = buildwdtrmsg(dsa->msg_out, mywide);
  987                         setmovedata(&dsa->msg_out_buf, DMASEG(dsa->msg_out), len);
  988                         *cont = E_response;
  989                         c->s[dsa->target] = WideResponse;
  990                         return;
  991                 }
  992                 case A_SIR_MSG_SDTR:
  993 #ifdef ASYNC_ONLY
  994                         *cont = E_reject;
  995                         return;
  996 #else
  997                         /* target decides to renegotiate */
  998                         histpf = n->scratcha[2];
  999                         hisreqack = n->scratcha[3];
 1000                         KPRINT(PRINTPREFIX "%d: SDTN: target init %d %d\n",
 1001                             dsa->target, histpf, hisreqack);
 1002                         if (hisreqack == 0) {
 1003                                 /* he wants asynchronous */
 1004                                 setasync(dsa, c, dsa->target);
 1005                                 tpf = 0;
 1006                         }
 1007                         else {
 1008                                 /* he wants synchronous */
 1009                                 tpf = chooserate(c, histpf, &scf, &xferp);
 1010                                 if (hisreqack > c->v->maxsyncoff)
 1011                                         hisreqack = c->v->maxsyncoff;
 1012                                 KPRINT(PRINTPREFIX "%d: using %d %d\n",
 1013                                     dsa->target, tpf, hisreqack);
 1014                                 setsync(dsa, c, dsa->target, tpf < 25, scf, xferp, hisreqack);
 1015                         }
 1016                         /* build my SDTR message */
 1017                         len = buildsdtrmsg(dsa->msg_out, tpf, hisreqack);
 1018                         setmovedata(&dsa->msg_out_buf, DMASEG(dsa->msg_out), len);
 1019                         *cont = E_response;
 1020                         c->s[dsa->target] = SyncResponse;
 1021                         return;
 1022 #endif
 1023                 }
 1024                 break;
 1025         case WideResponse:
 1026                 switch (msg) {
 1027                 case A_SIR_EV_RESPONSE_OK:
 1028                         c->s[dsa->target] = WideDone;
 1029                         KPRINT(PRINTPREFIX "%d: WDTN: response accepted\n", dsa->target);
 1030                         *cont = -2;
 1031                         return;
 1032                 case A_SIR_MSG_REJECT:
 1033                         setwide(dsa, c, dsa->target, 0);
 1034                         KPRINT(PRINTPREFIX "%d: WDTN: response REJECTed\n", dsa->target);
 1035                         *cont = -2;
 1036                         return;
 1037                 }
 1038                 break;
 1039         case SyncResponse:
 1040                 switch (msg) {
 1041                 case A_SIR_EV_RESPONSE_OK:
 1042                         c->s[dsa->target] = BothDone;
 1043                         KPRINT(PRINTPREFIX "%d: SDTN: response accepted (%s)\n",
 1044                             dsa->target, phase[n->sstat1 & 7]);
 1045                         *cont = -2;
 1046                         return; /* chf */
 1047                 case A_SIR_MSG_REJECT:
 1048                         setasync(dsa, c, dsa->target);
 1049                         KPRINT(PRINTPREFIX "%d: SDTN: response REJECTed\n", dsa->target);
 1050                         *cont = -2;
 1051                         return;
 1052                 }
 1053                 break;
 1054         }
 1055         KPRINT(PRINTPREFIX "%d: msgsm: state %d msg %d\n",
 1056             dsa->target, c->s[dsa->target], msg);
 1057         *wakeme = 1;
 1058         return;
 1059 }
 1060 
 1061 static void
 1062 calcblockdma(Dsa *d, ulong base, ulong count)
 1063 {
 1064         ulong blocks;
 1065         if (DEBUG(3))
 1066                 blocks = 0;
 1067         else {
 1068                 blocks = count / A_BSIZE;
 1069                 if (blocks > 255)
 1070                         blocks = 255;
 1071         }
 1072         d->dmablks = blocks;
 1073         d->dmaaddr[0] = base;
 1074         d->dmaaddr[1] = base >> 8;
 1075         d->dmaaddr[2] = base >> 16;
 1076         d->dmaaddr[3] = base >> 24;
 1077         setmovedata(&d->data_buf, base + blocks * A_BSIZE, count - blocks * A_BSIZE);
 1078         d->flag = legetl(d->data_buf.dbc) == 0;
 1079 }
 1080 
 1081 static ulong
 1082 read_mismatch_recover(Controller *c, Ncr *n, Dsa *dsa)
 1083 {
 1084         ulong dbc;
 1085         uchar dfifo = n->dfifo;
 1086         int inchip;
 1087 
 1088         dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
 1089         if (n->ctest5 & (1 << 5))
 1090                 inchip = ((dfifo | ((n->ctest5 & 3) << 8)) - (dbc & 0x3ff)) & 0x3ff;
 1091         else
 1092                 inchip = ((dfifo & 0x7f) - (dbc & 0x7f)) & 0x7f;
 1093         if (inchip) {
 1094                 IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: DMA FIFO = %d\n",
 1095                     dsa->target, dsa->lun, inchip);
 1096         }
 1097         if (n->sxfer & SYNCOFFMASK(c)) {
 1098                 /* SCSI FIFO */
 1099                 uchar fifo = n->sstat1 >> 4;
 1100                 if (c->v->maxsyncoff > 8)
 1101                         fifo |= (n->sstat2 & (1 << 4));
 1102                 if (fifo) {
 1103                         inchip += fifo;
 1104                         IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SCSI FIFO = %d\n",
 1105                             dsa->target, dsa->lun, fifo);
 1106                 }
 1107         }
 1108         else {
 1109                 if (n->sstat0 & (1 << 7)) {
 1110                         inchip++;
 1111                         IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SIDL full\n",
 1112                             dsa->target, dsa->lun);
 1113                 }
 1114                 if (n->sstat2 & (1 << 7)) {
 1115                         inchip++;
 1116                         IPRINT(PRINTPREFIX "%d/%d: read_mismatch_recover: SIDL msb full\n",
 1117                             dsa->target, dsa->lun);
 1118                 }
 1119         }
 1120         USED(inchip);
 1121         return dbc;
 1122 }
 1123 
 1124 static ulong
 1125 write_mismatch_recover(Controller *c, Ncr *n, Dsa *dsa)
 1126 {
 1127         ulong dbc;
 1128         uchar dfifo = n->dfifo;
 1129         int inchip;
 1130 
 1131         dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
 1132         USED(dsa);
 1133         if (n->ctest5 & (1 << 5))
 1134                 inchip = ((dfifo | ((n->ctest5 & 3) << 8)) - (dbc & 0x3ff)) & 0x3ff;
 1135         else
 1136                 inchip = ((dfifo & 0x7f) - (dbc & 0x7f)) & 0x7f;
 1137 #ifdef WMR_DEBUG
 1138         if (inchip) {
 1139                 IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: DMA FIFO = %d\n",
 1140                     dsa->target, dsa->lun, inchip);
 1141         }
 1142 #endif
 1143         if (n->sstat0 & (1 << 5)) {
 1144                 inchip++;
 1145 #ifdef WMR_DEBUG
 1146                 IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODL full\n", dsa->target, dsa->lun);
 1147 #endif
 1148         }
 1149         if (n->sstat2 & (1 << 5)) {
 1150                 inchip++;
 1151 #ifdef WMR_DEBUG
 1152                 IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODL msb full\n", dsa->target, dsa->lun);
 1153 #endif
 1154         }
 1155         if (n->sxfer & SYNCOFFMASK(c)) {
 1156                 /* synchronous SODR */
 1157                 if (n->sstat0 & (1 << 6)) {
 1158                         inchip++;
 1159 #ifdef WMR_DEBUG
 1160                         IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODR full\n",
 1161                             dsa->target, dsa->lun);
 1162 #endif
 1163                 }
 1164                 if (n->sstat2 & (1 << 6)) {
 1165                         inchip++;
 1166 #ifdef WMR_DEBUG
 1167                         IPRINT(PRINTPREFIX "%d/%d: write_mismatch_recover: SODR msb full\n",
 1168                             dsa->target, dsa->lun);
 1169 #endif
 1170                 }
 1171         }
 1172         /* clear the dma fifo */
 1173         n->ctest3 |= (1 << 2);
 1174         /* wait till done */
 1175         while ((n->dstat & Dfe) == 0)
 1176                 ;
 1177         return dbc + inchip;
 1178 }
 1179 
 1180 static void
 1181 sd53c8xxinterrupt(Ureg *ur, void *a)
 1182 {
 1183         uchar istat;
 1184         ushort sist;
 1185         uchar dstat;
 1186         int wakeme = 0;
 1187         int cont = -1;
 1188         Dsa *dsa;
 1189         ulong dsapa;
 1190         Controller *c = a;
 1191         Ncr *n = c->n;
 1192 
 1193         USED(ur);
 1194         if (DEBUG(1)) {
 1195                 IPRINT(PRINTPREFIX "int\n");
 1196         }
 1197         ilock(c);
 1198         istat = n->istat;
 1199         if (istat & Intf) {
 1200                 Dsa *d;
 1201                 int wokesomething = 0;
 1202                 if (DEBUG(1)) {
 1203                         IPRINT(PRINTPREFIX "Intfly\n");
 1204                 }
 1205                 n->istat = Intf;
 1206                 /* search for structures in A_STATE_DONE */
 1207                 for (d = KPTR(legetl(c->dsalist.head)); d != dsaend; d = KPTR(legetl(d->next))) {
 1208                         if (d->stateb == A_STATE_DONE) {
 1209                                 d->p9status = d->status;
 1210                                 if (DEBUG(1)) {
 1211                                         IPRINT(PRINTPREFIX "waking up dsa %lux\n", (ulong)d);
 1212                                 }
 1213                                 wakeup(d);
 1214                                 wokesomething = 1;
 1215                         }
 1216                 }
 1217                 if (!wokesomething) {
 1218                         IPRINT(PRINTPREFIX "nothing to wake up\n");
 1219                 }
 1220         }
 1221 
 1222         if ((istat & (Sip | Dip)) == 0) {
 1223                 if (DEBUG(1)) {
 1224                         IPRINT(PRINTPREFIX "int end %x\n", istat);
 1225                 }
 1226                 iunlock(c);
 1227                 return;
 1228         }
 1229 
 1230         sist = (n->sist1<<8)|n->sist0;  /* BUG? can two-byte read be inconsistent? */
 1231         dstat = n->dstat;
 1232         dsapa = legetl(n->dsa);
 1233 
 1234         /*
 1235          * Can't compute dsa until we know that dsapa is valid.
 1236          */
 1237         if(dsapa < -KZERO)
 1238                 dsa = (Dsa*)DMASEG_TO_KADDR(dsapa);
 1239         else{
 1240                 dsa = nil;
 1241                 /*
 1242                  * happens at startup on some cards but we 
 1243                  * don't actually deref dsa because none of the
 1244                  * flags we are about are set.
 1245                  * still, print in case that changes and we're
 1246                  * about to dereference nil.
 1247                  */
 1248                 iprint("sd53c8xxinterrupt: dsa=%.8lux istat=%ux sist=%ux dstat=%ux\n", dsapa, istat, sist, dstat);
 1249         }
 1250 
 1251         c->running = 0;
 1252         if (istat & Sip) {
 1253                 if (DEBUG(1)) {
 1254                         IPRINT("sist = %.4x\n", sist);
 1255                 }
 1256                 if (sist & 0x80) {
 1257                         ulong addr;
 1258                         ulong sa;
 1259                         ulong dbc;
 1260                         ulong tbc;
 1261                         int dmablks;
 1262                         ulong dmaaddr;
 1263 
 1264                         addr = legetl(n->dsp);
 1265                         sa = addr - c->scriptpa;
 1266                         if (DEBUG(1) || DEBUG(2)) {
 1267                                 IPRINT(PRINTPREFIX "%d/%d: Phase Mismatch sa=%.8lux\n",
 1268                                     dsa->target, dsa->lun, sa);
 1269                         }
 1270                         /*
 1271                          * now recover
 1272                          */
 1273                         if (sa == E_data_in_mismatch) {
 1274                                 /*
 1275                                  * though this is a failure in the residue, there may have been blocks
 1276                                  * as well. if so, dmablks will not have been zeroed, since the state
 1277                                  * was not saved by the microcode. 
 1278                                  */
 1279                                 dbc = read_mismatch_recover(c, n, dsa);
 1280                                 tbc = legetl(dsa->data_buf.dbc) - dbc;
 1281                                 dsa->dmablks = 0;
 1282                                 n->scratcha[2] = 0;
 1283                                 advancedata(&dsa->data_buf, tbc);
 1284                                 if (DEBUG(1) || DEBUG(2)) {
 1285                                         IPRINT(PRINTPREFIX "%d/%d: transferred = %ld residue = %ld\n",
 1286                                             dsa->target, dsa->lun, tbc, legetl(dsa->data_buf.dbc));
 1287                                 }
 1288                                 cont = E_data_mismatch_recover;
 1289                         }
 1290                         else if (sa == E_data_in_block_mismatch) {
 1291                                 dbc = read_mismatch_recover(c, n, dsa);
 1292                                 tbc = A_BSIZE - dbc;
 1293                                 /* recover current state from registers */
 1294                                 dmablks = n->scratcha[2];
 1295                                 dmaaddr = legetl(n->scratchb);
 1296                                 /* we have got to dmaaddr + tbc */
 1297                                 /* we have dmablks * A_BSIZE - tbc + residue left to do */
 1298                                 /* so remaining transfer is */
 1299                                 IPRINT("in_block_mismatch: dmaaddr = 0x%lux tbc=%lud dmablks=%d\n",
 1300                                     dmaaddr, tbc, dmablks);
 1301                                 calcblockdma(dsa, dmaaddr + tbc,
 1302                                     dmablks * A_BSIZE - tbc + legetl(dsa->data_buf.dbc));
 1303                                 /* copy changes into scratch registers */
 1304                                 IPRINT("recalc: dmablks %d dmaaddr 0x%lx pa 0x%lx dbc %ld\n",
 1305                                     dsa->dmablks, legetl(dsa->dmaaddr),
 1306                                     legetl(dsa->data_buf.pa), legetl(dsa->data_buf.dbc));
 1307                                 n->scratcha[2] = dsa->dmablks;
 1308                                 lesetl(n->scratchb, dsa->dmancr);
 1309                                 cont = E_data_block_mismatch_recover;
 1310                         }
 1311                         else if (sa == E_data_out_mismatch) {
 1312                                 dbc = write_mismatch_recover(c, n, dsa);
 1313                                 tbc = legetl(dsa->data_buf.dbc) - dbc;
 1314                                 dsa->dmablks = 0;
 1315                                 n->scratcha[2] = 0;
 1316                                 advancedata(&dsa->data_buf, tbc);
 1317                                 if (DEBUG(1) || DEBUG(2)) {
 1318                                         IPRINT(PRINTPREFIX "%d/%d: transferred = %ld residue = %ld\n",
 1319                                             dsa->target, dsa->lun, tbc, legetl(dsa->data_buf.dbc));
 1320                                 }
 1321                                 cont = E_data_mismatch_recover;
 1322                         }
 1323                         else if (sa == E_data_out_block_mismatch) {
 1324                                 dbc = write_mismatch_recover(c, n, dsa);
 1325                                 tbc = legetl(dsa->data_buf.dbc) - dbc;
 1326                                 /* recover current state from registers */
 1327                                 dmablks = n->scratcha[2];
 1328                                 dmaaddr = legetl(n->scratchb);
 1329                                 /* we have got to dmaaddr + tbc */
 1330                                 /* we have dmablks blocks - tbc + residue left to do */
 1331                                 /* so remaining transfer is */
 1332                                 IPRINT("out_block_mismatch: dmaaddr = %lux tbc=%lud dmablks=%d\n",
 1333                                     dmaaddr, tbc, dmablks);
 1334                                 calcblockdma(dsa, dmaaddr + tbc,
 1335                                     dmablks * A_BSIZE - tbc + legetl(dsa->data_buf.dbc));
 1336                                 /* copy changes into scratch registers */
 1337                                 n->scratcha[2] = dsa->dmablks;
 1338                                 lesetl(n->scratchb, dsa->dmancr);
 1339                                 cont = E_data_block_mismatch_recover;
 1340                         }
 1341                         else if (sa == E_id_out_mismatch) {
 1342                                 /*
 1343                                  * target switched phases while attention held during
 1344                                  * message out. The possibilities are:
 1345                                  * 1. It didn't like the last message. This is indicated
 1346                                  *    by the new phase being message_in. Use script to recover
 1347                                  *
 1348                                  * 2. It's not SCSI-II compliant. The new phase will be other
 1349                                  *    than message_in. We should also indicate that the device
 1350                                  *    is asynchronous, if it's the SDTR that got ignored
 1351                                  * 
 1352                                  * For now, if the phase switch is not to message_in, and
 1353                                  * and it happens after IDENTIFY and before SDTR, we
 1354                                  * notify the negotiation state machine.
 1355                                  */
 1356                                 ulong lim = legetl(dsa->msg_out_buf.dbc);
 1357                                 uchar p = n->sstat1 & 7;
 1358                                 dbc = write_mismatch_recover(c, n, dsa);
 1359                                 tbc = lim - dbc;
 1360                                 IPRINT(PRINTPREFIX "%d/%d: msg_out_mismatch: %lud/%lud sent, phase %s\n",
 1361                                     dsa->target, dsa->lun, tbc, lim, phase[p]);
 1362                                 if (p != MessageIn && tbc == 1) {
 1363                                         msgsm(dsa, c, A_SIR_EV_PHASE_SWITCH_AFTER_ID, &cont, &wakeme);
 1364                                 }
 1365                                 else
 1366                                         cont = E_id_out_mismatch_recover;
 1367                         }
 1368                         else if (sa == E_cmd_out_mismatch) {
 1369                                 /*
 1370                                  * probably the command count is longer than the device wants ...
 1371                                  */
 1372                                 ulong lim = legetl(dsa->cmd_buf.dbc);
 1373                                 uchar p = n->sstat1 & 7;
 1374                                 dbc = write_mismatch_recover(c, n, dsa);
 1375                                 tbc = lim - dbc;
 1376                                 IPRINT(PRINTPREFIX "%d/%d: cmd_out_mismatch: %lud/%lud sent, phase %s\n",
 1377                                     dsa->target, dsa->lun, tbc, lim, phase[p]);
 1378                                 USED(p, tbc);
 1379                                 cont = E_to_decisions;
 1380                         }
 1381                         else {
 1382                                 IPRINT(PRINTPREFIX "%d/%d: ma sa=%.8lux wanted=%s got=%s\n",
 1383                                     dsa->target, dsa->lun, sa,
 1384                                     phase[n->dcmd & 7],
 1385                                     phase[n->sstat1 & 7]);
 1386                                 dumpncrregs(c, 1);
 1387                                 dsa->p9status = SDeio;  /* chf */
 1388                                 wakeme = 1;
 1389                         }
 1390                 }
 1391                 /*else*/ if (sist & 0x400) {
 1392                         if (DEBUG(0)) {
 1393                                 IPRINT(PRINTPREFIX "%d/%d Sto\n", dsa->target, dsa->lun);
 1394                         }
 1395                         dsa->p9status = SDtimeout;
 1396                         dsa->stateb = A_STATE_DONE;
 1397                         coherence();
 1398                         softreset(c);
 1399                         cont = E_issue_check;
 1400                         wakeme = 1;
 1401                 }
 1402                 if (sist & 0x1) {
 1403                         IPRINT(PRINTPREFIX "%d/%d: parity error\n", dsa->target, dsa->lun);
 1404                         dsa->parityerror = 1;
 1405                 }
 1406                 if (sist & 0x4) {
 1407                         IPRINT(PRINTPREFIX "%d/%d: unexpected disconnect\n",
 1408                             dsa->target, dsa->lun);
 1409                         dumpncrregs(c, 1);
 1410                         //wakeme = 1;
 1411                         dsa->p9status = SDeio;
 1412                 }
 1413         }
 1414         if (istat & Dip) {
 1415                 if (DEBUG(1)) {
 1416                         IPRINT("dstat = %.2x\n", dstat);
 1417                 }
 1418                 /*else*/ if (dstat & Ssi) {
 1419                         ulong w = legetl(n->dsp) - c->scriptpa;
 1420                         IPRINT("[%lux]", w);
 1421                         USED(w);
 1422                         cont = -2;      /* restart */
 1423                 }
 1424                 if (dstat & Sir) {
 1425                         switch (legetl(n->dsps)) {
 1426                         case A_SIR_MSG_IO_COMPLETE:
 1427                                 dsa->p9status = dsa->status;
 1428                                 wakeme = 1;
 1429                                 break;
 1430                         case A_SIR_MSG_SDTR:
 1431                         case A_SIR_MSG_WDTR:
 1432                         case A_SIR_MSG_REJECT:
 1433                         case A_SIR_EV_RESPONSE_OK:
 1434                                 msgsm(dsa, c, legetl(n->dsps), &cont, &wakeme);
 1435                                 break;
 1436                         case A_SIR_MSG_IGNORE_WIDE_RESIDUE:
 1437                                 /* back up one in the data transfer */
 1438                                 IPRINT(PRINTPREFIX "%d/%d: ignore wide residue %d, WSR = %d\n",
 1439                                     dsa->target, dsa->lun, n->scratcha[1], n->scntl2 & 1);
 1440                                 if (dsa->flag == 2) {
 1441                                         IPRINT(PRINTPREFIX "%d/%d: transfer over; residue ignored\n",
 1442                                             dsa->target, dsa->lun);
 1443                                 }
 1444                                 else {
 1445                                         calcblockdma(dsa, legetl(dsa->dmaaddr) - 1,
 1446                                             dsa->dmablks * A_BSIZE + legetl(dsa->data_buf.dbc) + 1);
 1447                                 }
 1448                                 cont = -2;
 1449                                 break;
 1450                         case A_SIR_ERROR_NOT_MSG_IN_AFTER_RESELECT:
 1451                                 IPRINT(PRINTPREFIX "%d: not msg_in after reselect (%s)",
 1452                                     n->ssid & SSIDMASK(c), phase[n->sstat1 & 7]);
 1453                                 dsa = dsafind(c, n->ssid & SSIDMASK(c), -1, A_STATE_DISCONNECTED);
 1454                                 dumpncrregs(c, 1);
 1455                                 wakeme = 1;
 1456                                 break;
 1457                         case A_SIR_NOTIFY_LOAD_STATE:
 1458                                 IPRINT(PRINTPREFIX ": load_state dsa=%p\n", dsa);
 1459                                 if (dsa == (void*)KZERO || dsa == (void*)-1) {
 1460                                         dsadump(c);
 1461                                         dumpncrregs(c, 1);
 1462                                         panic("bad dsa in load_state");
 1463                                 }
 1464                                 cont = -2;
 1465                                 break;
 1466                         case A_SIR_NOTIFY_MSG_IN:
 1467                                 IPRINT(PRINTPREFIX "%d/%d: msg_in %d\n",
 1468                                     dsa->target, dsa->lun, n->sfbr);
 1469                                 cont = -2;
 1470                                 break;
 1471                         case A_SIR_NOTIFY_DISC:
 1472                                 IPRINT(PRINTPREFIX "%d/%d: disconnect:", dsa->target, dsa->lun);
 1473                                 goto dsadump;
 1474                         case A_SIR_NOTIFY_STATUS:
 1475                                 IPRINT(PRINTPREFIX "%d/%d: status\n", dsa->target, dsa->lun);
 1476                                 cont = -2;
 1477                                 break;
 1478                         case A_SIR_NOTIFY_COMMAND:
 1479                                 IPRINT(PRINTPREFIX "%d/%d: commands\n", dsa->target, dsa->lun);
 1480                                 cont = -2;
 1481                                 break;
 1482                         case A_SIR_NOTIFY_DATA_IN:
 1483                                 IPRINT(PRINTPREFIX "%d/%d: data in a %lx b %lx\n",
 1484                                     dsa->target, dsa->lun, legetl(n->scratcha), legetl(n->scratchb));
 1485                                 cont = -2;
 1486                                 break;
 1487                         case A_SIR_NOTIFY_BLOCK_DATA_IN:
 1488                                 IPRINT(PRINTPREFIX "%d/%d: block data in: a2 %x b %lx\n",
 1489                                     dsa->target, dsa->lun, n->scratcha[2], legetl(n->scratchb));
 1490                                 cont = -2;
 1491                                 break;
 1492                         case A_SIR_NOTIFY_DATA_OUT:
 1493                                 IPRINT(PRINTPREFIX "%d/%d: data out\n", dsa->target, dsa->lun);
 1494                                 cont = -2;
 1495                                 break;
 1496                         case A_SIR_NOTIFY_DUMP:
 1497                                 IPRINT(PRINTPREFIX "%d/%d: dump\n", dsa->target, dsa->lun);
 1498                                 dumpncrregs(c, 1);
 1499                                 cont = -2;
 1500                                 break;
 1501                         case A_SIR_NOTIFY_DUMP2:
 1502                                 IPRINT(PRINTPREFIX "%d/%d: dump2:", dsa->target, dsa->lun);
 1503                                 IPRINT(" sa %lux", legetl(n->dsp) - c->scriptpa);
 1504                                 IPRINT(" dsa %lux", legetl(n->dsa));
 1505                                 IPRINT(" sfbr %ux", n->sfbr);
 1506                                 IPRINT(" a %lux", legetl(n->scratcha));
 1507                                 IPRINT(" b %lux", legetl(n->scratchb));
 1508                                 IPRINT(" ssid %ux", n->ssid);
 1509                                 IPRINT("\n");
 1510                                 cont = -2;
 1511                                 break;
 1512                         case A_SIR_NOTIFY_WAIT_RESELECT:
 1513                                 IPRINT(PRINTPREFIX "wait reselect\n");
 1514                                 cont = -2;
 1515                                 break;
 1516                         case A_SIR_NOTIFY_RESELECT:
 1517                                 IPRINT(PRINTPREFIX "reselect: ssid %.2x sfbr %.2x at %ld\n",
 1518                                     n->ssid, n->sfbr, TK2MS(m->ticks));
 1519                                 cont = -2;
 1520                                 break;
 1521                         case A_SIR_NOTIFY_ISSUE:
 1522                                 IPRINT(PRINTPREFIX "%d/%d: issue dsa=%p end=%p:", dsa->target, dsa->lun, dsa, dsaend);
 1523                         dsadump:
 1524                                 IPRINT(" tgt=%d", dsa->target);
 1525                                 IPRINT(" time=%ld", TK2MS(m->ticks));
 1526                                 IPRINT("\n");
 1527                                 cont = -2;
 1528                                 break;
 1529                         case A_SIR_NOTIFY_ISSUE_CHECK:
 1530                                 IPRINT(PRINTPREFIX "issue check\n");
 1531                                 cont = -2;
 1532                                 break;
 1533                         case A_SIR_NOTIFY_SIGP:
 1534                                 IPRINT(PRINTPREFIX "responded to SIGP\n");
 1535                                 cont = -2;
 1536                                 break;
 1537                         case A_SIR_NOTIFY_DUMP_NEXT_CODE: {
 1538                                 ulong *dsp = c->script + (legetl(n->dsp)-c->scriptpa)/4;
 1539                                 int x;
 1540                                 IPRINT(PRINTPREFIX "code at %lux", dsp - c->script);
 1541                                 for (x = 0; x < 6; x++) {
 1542                                         IPRINT(" %.8lux", dsp[x]);
 1543                                 }
 1544                                 IPRINT("\n");
 1545                                 USED(dsp);
 1546                                 cont = -2;
 1547                                 break;
 1548                         }
 1549                         case A_SIR_NOTIFY_WSR:
 1550                                 IPRINT(PRINTPREFIX "%d/%d: WSR set\n", dsa->target, dsa->lun);
 1551                                 cont = -2;
 1552                                 break;
 1553                         case A_SIR_NOTIFY_LOAD_SYNC:
 1554                                 IPRINT(PRINTPREFIX "%d/%d: scntl=%.2x sxfer=%.2x\n",
 1555                                     dsa->target, dsa->lun, n->scntl3, n->sxfer);
 1556                                 cont = -2;
 1557                                 break;
 1558                         case A_SIR_NOTIFY_RESELECTED_ON_SELECT:
 1559                                 if (DEBUG(2)) {
 1560                                         IPRINT(PRINTPREFIX "%d/%d: reselected during select\n",
 1561                                             dsa->target, dsa->lun);
 1562                                 }
 1563                                 cont = -2;
 1564                                 break;
 1565                         case A_error_reselected:                /* dsa isn't valid here */
 1566                                 iprint(PRINTPREFIX "reselection error\n");
 1567                                 dumpncrregs(c, 1);
 1568                                 for (dsa = KPTR(legetl(c->dsalist.head)); dsa != dsaend; dsa = KPTR(legetl(dsa->next))) {
 1569                                         IPRINT(PRINTPREFIX "dsa target %d lun %d state %d\n", dsa->target, dsa->lun, dsa->stateb);
 1570                                 }
 1571                                 break;
 1572                         default:
 1573                                 IPRINT(PRINTPREFIX "%d/%d: script error %ld\n",
 1574                                         dsa->target, dsa->lun, legetl(n->dsps));
 1575                                 dumpncrregs(c, 1);
 1576                                 wakeme = 1;
 1577                         }
 1578                 }
 1579                 /*else*/ if (dstat & Iid) {
 1580                         int i, target, lun;
 1581                         ulong addr, dbc, *v;
 1582                         
 1583                         addr = legetl(n->dsp);
 1584                         if(dsa){
 1585                                 target = dsa->target;
 1586                                 lun = dsa->lun;
 1587                         }else{
 1588                                 target = -1;
 1589                                 lun = -1;
 1590                         }
 1591                         dbc = (n->dbc[2]<<16)|(n->dbc[1]<<8)|n->dbc[0];
 1592 
 1593                 //      if(dsa == nil)
 1594                                 idebug++;
 1595                         IPRINT(PRINTPREFIX "%d/%d: Iid pa=%.8lux sa=%.8lux dbc=%lux\n",
 1596                             target, lun,
 1597                             addr, addr - c->scriptpa, dbc);
 1598                         addr = (ulong)c->script + addr - c->scriptpa;
 1599                         addr -= 64;
 1600                         addr &= ~63;
 1601                         v = (ulong*)addr;
 1602                         for(i=0; i<8; i++){
 1603                                 IPRINT("%.8lux: %.8lux %.8lux %.8lux %.8lux\n", 
 1604                                         addr, v[0], v[1], v[2], v[3]);
 1605                                 addr += 4*4;
 1606                                 v += 4;
 1607                         }
 1608                         USED(addr, dbc);
 1609                         if(dsa == nil){
 1610                                 dsadump(c);
 1611                                 dumpncrregs(c, 1);
 1612                                 panic("bad dsa");
 1613                         }
 1614                         dsa->p9status = SDeio;
 1615                         wakeme = 1;
 1616                 }
 1617                 /*else*/ if (dstat & Bf) {
 1618                         IPRINT(PRINTPREFIX "%d/%d: Bus Fault\n", dsa->target, dsa->lun);
 1619                         dumpncrregs(c, 1);
 1620                         dsa->p9status = SDeio;
 1621                         wakeme = 1;
 1622                 }
 1623         }
 1624         if (cont == -2)
 1625                 ncrcontinue(c);
 1626         else if (cont >= 0)
 1627                 start(c, cont);
 1628         if (wakeme){
 1629                 if(dsa->p9status == SDnostatus)
 1630                         dsa->p9status = SDeio;
 1631                 wakeup(dsa);
 1632         }
 1633         iunlock(c);
 1634         if (DEBUG(1)) {
 1635                 IPRINT(PRINTPREFIX "int end 1\n");
 1636         }
 1637 }
 1638 
 1639 static int
 1640 done(void *arg)
 1641 {
 1642         return ((Dsa *)arg)->p9status != SDnostatus;
 1643 }
 1644 
 1645 static void
 1646 setmovedata(Movedata *d, ulong pa, ulong bc)
 1647 {
 1648         d->pa[0] = pa;
 1649         d->pa[1] = pa>>8;
 1650         d->pa[2] = pa>>16;
 1651         d->pa[3] = pa>>24;
 1652         d->dbc[0] = bc;
 1653         d->dbc[1] = bc>>8;
 1654         d->dbc[2] = bc>>16;
 1655         d->dbc[3] = bc>>24;
 1656 }
 1657 
 1658 static void
 1659 advancedata(Movedata *d, long v)
 1660 {
 1661         lesetl(d->pa, legetl(d->pa) + v);
 1662         lesetl(d->dbc, legetl(d->dbc) - v);
 1663 }
 1664 
 1665 static void
 1666 dumpwritedata(uchar *data, int datalen)
 1667 {
 1668         int i;
 1669         uchar *bp;
 1670         if (!DEBUG(0)){
 1671                 USED(data, datalen);
 1672                 return;
 1673         }
 1674 
 1675         if (datalen) {
 1676                 KPRINT(PRINTPREFIX "write:");
 1677                 for (i = 0, bp = data; i < 50 && i < datalen; i++, bp++) {
 1678                         KPRINT("%.2ux", *bp);
 1679                 }
 1680                 if (i < datalen) {
 1681                         KPRINT("...");
 1682                 }
 1683                 KPRINT("\n");
 1684         }
 1685 }
 1686 
 1687 static void
 1688 dumpreaddata(uchar *data, int datalen)
 1689 {
 1690         int i;
 1691         uchar *bp;
 1692         if (!DEBUG(0)){
 1693                 USED(data, datalen);
 1694                 return;
 1695         }
 1696 
 1697         if (datalen) {
 1698                 KPRINT(PRINTPREFIX "read:");
 1699                 for (i = 0, bp = data; i < 50 && i < datalen; i++, bp++) {
 1700                         KPRINT("%.2ux", *bp);
 1701                 }
 1702                 if (i < datalen) {
 1703                         KPRINT("...");
 1704                 }
 1705                 KPRINT("\n");
 1706         }
 1707 }
 1708 
 1709 static void
 1710 busreset(Controller *c)
 1711 {
 1712         int x, ntarget;
 1713 
 1714         /* bus reset */
 1715         c->n->scntl1 |= (1 << 3);
 1716         delay(500);
 1717         c->n->scntl1 &= ~(1 << 3);
 1718         if(!(c->v->feature & Wide))
 1719                 ntarget = 8;
 1720         else
 1721                 ntarget = MAXTARGET;
 1722         for (x = 0; x < ntarget; x++) {
 1723                 setwide(0, c, x, 0);
 1724 #ifndef ASYNC_ONLY
 1725                 c->s[x] = NeitherDone;
 1726 #endif
 1727         }
 1728         c->capvalid = 0;
 1729 }
 1730 
 1731 static void
 1732 reset(Controller *c)
 1733 {
 1734         /* should wakeup all pending tasks */
 1735         softreset(c);
 1736         busreset(c);
 1737 }
 1738 
 1739 static int
 1740 sd53c8xxrio(SDreq* r)
 1741 {
 1742         Dsa *d;
 1743         uchar *bp;
 1744         Controller *c;
 1745         uchar target_expo, my_expo;
 1746         int bc, check, i, status, target;
 1747 
 1748         if((target = r->unit->subno) == 0x07)
 1749                 return r->status = SDtimeout;   /* assign */
 1750 
 1751         c = r->unit->dev->ctlr;
 1752 
 1753         check = 0;
 1754         d = dsaalloc(c, target, r->lun);
 1755 
 1756         qlock(&c->q[target]);                   /* obtain access to target */
 1757 docheck:
 1758         /* load the transfer control stuff */
 1759         d->scsi_id_buf[0] = 0;
 1760         d->scsi_id_buf[1] = c->sxfer[target];
 1761         d->scsi_id_buf[2] = target;
 1762         d->scsi_id_buf[3] = c->scntl3[target];
 1763         synctodsa(d, c);
 1764 
 1765         bc = 0;
 1766 
 1767         d->msg_out[bc] = 0x80 | r->lun;
 1768 
 1769 #ifndef NO_DISCONNECT
 1770         d->msg_out[bc] |= (1 << 6);
 1771 #endif
 1772         bc++;
 1773 
 1774         /* work out what to do about negotiation */
 1775         switch (c->s[target]) {
 1776         default:
 1777                 KPRINT(PRINTPREFIX "%d: strange nego state %d\n", target, c->s[target]);
 1778                 c->s[target] = NeitherDone;
 1779                 /* fall through */
 1780         case NeitherDone:
 1781                 if ((c->capvalid & (1 << target)) == 0)
 1782                         break;
 1783                 target_expo = (c->cap[target] >> 5) & 3;
 1784                 my_expo = (c->v->feature & Wide) != 0;
 1785                 if (target_expo < my_expo)
 1786                         my_expo = target_expo;
 1787 #ifdef ALWAYS_DO_WDTR
 1788                 bc += buildwdtrmsg(d->msg_out + bc, my_expo);
 1789                 KPRINT(PRINTPREFIX "%d: WDTN: initiating expo %d\n", target, my_expo);
 1790                 c->s[target] = WideInit;
 1791                 break;
 1792 #else
 1793                 if (my_expo) {
 1794                         bc += buildwdtrmsg(d->msg_out + bc, (c->v->feature & Wide) ? 1 : 0);
 1795                         KPRINT(PRINTPREFIX "%d: WDTN: initiating expo %d\n", target, my_expo);
 1796                         c->s[target] = WideInit;
 1797                         break;
 1798                 }
 1799                 KPRINT(PRINTPREFIX "%d: WDTN: narrow\n", target);
 1800                 /* fall through */
 1801 #endif
 1802         case WideDone:
 1803                 if (c->cap[target] & (1 << 4)) {
 1804                         KPRINT(PRINTPREFIX "%d: SDTN: initiating %d %d\n", target, c->tpf, c->v->maxsyncoff);
 1805                         bc += buildsdtrmsg(d->msg_out + bc, c->tpf, c->v->maxsyncoff);
 1806                         c->s[target] = SyncInit;
 1807                         break;
 1808                 }
 1809                 KPRINT(PRINTPREFIX "%d: SDTN: async only\n", target);
 1810                 c->s[target] = BothDone;
 1811                 break;
 1812 
 1813         case BothDone:
 1814                 break;
 1815         }
 1816 
 1817         setmovedata(&d->msg_out_buf, DMASEG(d->msg_out), bc);
 1818         setmovedata(&d->cmd_buf, DMASEG(r->cmd), r->clen);
 1819         calcblockdma(d, r->data ? DMASEG(r->data) : 0, r->dlen);
 1820 
 1821         if (DEBUG(0)) {
 1822                 KPRINT(PRINTPREFIX "%d/%d: exec: ", target, r->lun);
 1823                 for (bp = r->cmd; bp < &r->cmd[r->clen]; bp++) {
 1824                         KPRINT("%.2ux", *bp);
 1825                 }
 1826                 KPRINT("\n");
 1827                 if (!r->write) {
 1828                         KPRINT(PRINTPREFIX "%d/%d: exec: limit=(%d)%ld\n",
 1829                           target, r->lun, d->dmablks, legetl(d->data_buf.dbc));
 1830                 }
 1831                 else
 1832                         dumpwritedata(r->data, r->dlen);
 1833         }
 1834 
 1835         setmovedata(&d->status_buf, DMASEG(&d->status), 1);     
 1836 
 1837         d->p9status = SDnostatus;
 1838         d->parityerror = 0;
 1839         coherence();
 1840         d->stateb = A_STATE_ISSUE;              /* start operation */
 1841         coherence();
 1842 
 1843         ilock(c);
 1844         if (c->ssm)
 1845                 c->n->dcntl |= 0x10;            /* single step */
 1846         if (c->running) {
 1847                 c->n->istat = Sigp;
 1848         }
 1849         else {
 1850                 start(c, E_issue_check);
 1851         }
 1852         iunlock(c);
 1853 
 1854         while(waserror())
 1855                 ;
 1856         tsleep(d, done, d, 600 * 1000);
 1857         poperror();
 1858 
 1859         if (!done(d)) {
 1860                 KPRINT(PRINTPREFIX "%d/%d: exec: Timed out\n", target, r->lun);
 1861                 dumpncrregs(c, 0);
 1862                 dsafree(c, d);
 1863                 reset(c);
 1864                 qunlock(&c->q[target]);
 1865                 r->status = SDtimeout;
 1866                 return r->status = SDtimeout;   /* assign */
 1867         }
 1868 
 1869         if((status = d->p9status) == SDeio)
 1870                 c->s[target] = NeitherDone;
 1871         if (d->parityerror) {
 1872                 status = SDeio;
 1873         }
 1874 
 1875         /*
 1876          * adjust datalen
 1877          */
 1878         r->rlen = r->dlen;
 1879         if (DEBUG(0)) {
 1880                 KPRINT(PRINTPREFIX "%d/%d: exec: before rlen adjust: dmablks %d flag %d dbc %lud\n",
 1881                     target, r->lun, d->dmablks, d->flag, legetl(d->data_buf.dbc));
 1882         }
 1883         r->rlen = r->dlen;
 1884         if (d->flag != 2) {
 1885                 r->rlen -= d->dmablks * A_BSIZE;
 1886                 r->rlen -= legetl(d->data_buf.dbc);
 1887         }
 1888         if(!r->write)
 1889                 dumpreaddata(r->data, r->rlen);
 1890         if (DEBUG(0)) {
 1891                 KPRINT(PRINTPREFIX "%d/%d: exec: p9status=%d status %d rlen %ld\n",
 1892                     target, r->lun, d->p9status, status, r->rlen);
 1893         }
 1894         /*
 1895          * spot the identify
 1896          */
 1897         if ((c->capvalid & (1 << target)) == 0
 1898          && (status == SDok || status == SDcheck)
 1899          && r->cmd[0] == 0x12 && r->dlen >= 8) {
 1900                 c->capvalid |= 1 << target;
 1901                 bp = r->data;
 1902                 c->cap[target] = bp[7];
 1903                 KPRINT(PRINTPREFIX "%d: capabilities %.2x\n", target, bp[7]);
 1904         }
 1905         if(!check && status == SDcheck && !(r->flags & SDnosense)){
 1906                 check = 1;
 1907                 r->write = 0;
 1908                 memset(r->cmd, 0, sizeof(r->cmd));
 1909                 r->cmd[0] = 0x03;
 1910                 r->cmd[1] = r->lun<<5;
 1911                 r->cmd[4] = sizeof(r->sense)-1;
 1912                 r->clen = 6;
 1913                 r->data = r->sense;
 1914                 r->dlen = sizeof(r->sense)-1;
 1915                 /*
 1916                  * Clear out the microcode state
 1917                  * so the Dsa can be re-used.
 1918                  */
 1919                 lesetl(&d->stateb, A_STATE_ALLOCATED);
 1920                 coherence();
 1921                 goto docheck;
 1922         }
 1923         qunlock(&c->q[target]);
 1924         dsafree(c, d);
 1925 
 1926         if(status == SDok && check){
 1927                 status = SDcheck;
 1928                 r->flags |= SDvalidsense;
 1929         }
 1930         if(DEBUG(0))
 1931                 KPRINT(PRINTPREFIX "%d: r flags %8.8uX status %d rlen %ld\n",
 1932                         target, r->flags, status, r->rlen);
 1933         if(r->flags & SDvalidsense){
 1934                 if(!DEBUG(0))
 1935                         KPRINT(PRINTPREFIX "%d: r flags %8.8uX status %d rlen %ld\n",
 1936                                 target, r->flags, status, r->rlen);
 1937                 for(i = 0; i < r->rlen; i++)
 1938                         KPRINT(" %2.2uX", r->sense[i]);
 1939                 KPRINT("\n");
 1940         }
 1941         return r->status = status;
 1942 }
 1943 
 1944 #define vpt ((ulong*)VPT)
 1945 #define VPTX(va)                (((ulong)(va))>>12)
 1946 static void
 1947 cribbios(Controller *c)
 1948 {
 1949         c->bios.scntl3 = c->n->scntl3;
 1950         c->bios.stest2 = c->n->stest2;
 1951         print(PRINTPREFIX "bios scntl3(%.2x) stest2(%.2x)\n", c->bios.scntl3, c->bios.stest2);
 1952 }
 1953 
 1954 static int
 1955 bios_set_differential(Controller *c)
 1956 {
 1957         /* Concept lifted from FreeBSD - thanks Gerard */
 1958         /* basically, if clock conversion factors are set, then there is
 1959          * evidence the bios had a go at the chip, and if so, it would
 1960          * have set the differential enable bit in stest2
 1961          */
 1962         return (c->bios.scntl3 & 7) != 0 && (c->bios.stest2 & 0x20) != 0;
 1963 }
 1964 
 1965 #define NCR_VID         0x1000
 1966 #define NCR_810_DID     0x0001
 1967 #define NCR_820_DID     0x0002  /* don't know enough about this one to support it */
 1968 #define NCR_825_DID     0x0003
 1969 #define NCR_815_DID     0x0004
 1970 #define SYM_810AP_DID   0x0005
 1971 #define SYM_860_DID     0x0006
 1972 #define SYM_896_DID     0x000b
 1973 #define SYM_895_DID     0x000c
 1974 #define SYM_885_DID     0x000d  /* ditto */
 1975 #define SYM_875_DID     0x000f  /* ditto */
 1976 #define SYM_1010_DID    0x0020
 1977 #define SYM_1011_DID    0x0021
 1978 #define SYM_875J_DID    0x008f
 1979 
 1980 static Variant variant[] = {
 1981 { NCR_810_DID,   0x0f, "NCR53C810",     Burst16,   8, 24, 0 },
 1982 { NCR_810_DID,   0x1f, "SYM53C810ALV",  Burst16,   8, 24, Prefetch },
 1983 { NCR_810_DID,   0xff, "SYM53C810A",    Burst16,   8, 24, Prefetch },
 1984 { SYM_810AP_DID, 0xff, "SYM53C810AP",   Burst16,   8, 24, Prefetch },
 1985 { NCR_815_DID,   0xff, "NCR53C815",     Burst16,   8, 24, BurstOpCodeFetch },
 1986 { NCR_825_DID,   0x0f, "NCR53C825",     Burst16,   8, 24, Wide|BurstOpCodeFetch|Differential },
 1987 { NCR_825_DID,   0xff, "SYM53C825A",    Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide },
 1988 { SYM_860_DID,   0x0f, "SYM53C860",     Burst16,   8, 24, Prefetch|Ultra },
 1989 { SYM_860_DID,   0xff, "SYM53C860LV",   Burst16,   8, 24, Prefetch|Ultra },
 1990 { SYM_875_DID,   0x01, "SYM53C875r1",   Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra },
 1991 { SYM_875_DID,   0xff, "SYM53C875",     Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra|ClockDouble },
 1992 { SYM_875J_DID,   0xff, "SYM53C875j",   Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Differential|Wide|Ultra|ClockDouble },
 1993 { SYM_885_DID,   0xff, "SYM53C885",     Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Wide|Ultra|ClockDouble },
 1994 { SYM_895_DID,   0xff, "SYM53C895",     Burst128, 16, 24, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
 1995 { SYM_896_DID,   0xff, "SYM53C896",     Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
 1996 { SYM_1010_DID,  0xff, "SYM53C1010",    Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
 1997 { SYM_1011_DID,   0xff, "SYM53C1010",   Burst128, 16, 64, Prefetch|LocalRAM|BigFifo|Wide|Ultra|Ultra2 },
 1998 };
 1999 
 2000 static int
 2001 xfunc(Controller *c, enum na_external x, unsigned long *v)
 2002 {
 2003         switch (x)
 2004         {
 2005         case X_scsi_id_buf:
 2006                 *v = offsetof(Dsa, scsi_id_buf[0]); return 1;
 2007         case X_msg_out_buf:
 2008                 *v = offsetof(Dsa, msg_out_buf); return 1;
 2009         case X_cmd_buf:
 2010                 *v = offsetof(Dsa, cmd_buf); return 1;
 2011         case X_data_buf:
 2012                 *v = offsetof(Dsa, data_buf); return 1;
 2013         case X_status_buf:
 2014                 *v = offsetof(Dsa, status_buf); return 1;
 2015         case X_dsa_head:
 2016                 *v = DMASEG(&c->dsalist.head[0]); return 1;
 2017         case X_ssid_mask:
 2018                 *v = SSIDMASK(c); return 1;
 2019         default:
 2020                 print("xfunc: can't find external %d\n", x);
 2021                 return 0;
 2022         }
 2023         return 1;
 2024 }
 2025 
 2026 static int
 2027 na_fixup(Controller *c, ulong pa_reg,
 2028     struct na_patch *patch, int patches,
 2029     int (*externval)(Controller*, int, ulong*))
 2030 {
 2031         int p;
 2032         int v;
 2033         ulong *script, pa_script;
 2034         unsigned long lw, lv;
 2035 
 2036         script = c->script;
 2037         pa_script = c->scriptpa;
 2038         for (p = 0; p < patches; p++) {
 2039                 switch (patch[p].type) {
 2040                 case 1:
 2041                         /* script relative */
 2042                         script[patch[p].lwoff] += pa_script;
 2043                         break;
 2044                 case 2:
 2045                         /* register i/o relative */
 2046                         script[patch[p].lwoff] += pa_reg;
 2047                         break;
 2048                 case 3:
 2049                         /* data external */
 2050                         lw = script[patch[p].lwoff];
 2051                         v = (lw >> 8) & 0xff;
 2052                         if (!(*externval)(c, v, &lv))
 2053                                 return 0;
 2054                         v = lv & 0xff;
 2055                         script[patch[p].lwoff] = (lw & 0xffff00ffL) | (v << 8);
 2056                         break;
 2057                 case 4:
 2058                         /* 32 bit external */
 2059                         lw = script[patch[p].lwoff];
 2060                         if (!(*externval)(c, lw, &lv))
 2061                                 return 0;
 2062                         script[patch[p].lwoff] = lv;
 2063                         break;
 2064                 case 5:
 2065                         /* 24 bit external */
 2066                         lw = script[patch[p].lwoff];
 2067                         if (!(*externval)(c, lw & 0xffffff, &lv))
 2068                                 return 0;
 2069                         script[patch[p].lwoff] = (lw & 0xff000000L) | (lv & 0xffffffL);
 2070                         break;
 2071                 }
 2072         }
 2073         return 1;
 2074 }
 2075 
 2076 static SDev*
 2077 sd53c8xxpnp(void)
 2078 {
 2079         char *cp;
 2080         Pcidev *p;
 2081         Variant *v;
 2082         int ba, nctlr;
 2083         void *scriptma;
 2084         Controller *ctlr;
 2085         SDev *sdev, *head, *tail;
 2086         ulong regpa, *script, scriptpa;
 2087         void *regva, *scriptva;
 2088 
 2089         if(cp = getconf("*maxsd53c8xx"))
 2090                 nctlr = strtoul(cp, 0, 0);
 2091         else
 2092                 nctlr = 32;
 2093 
 2094         p = nil;
 2095         head = tail = nil;
 2096         while((p = pcimatch(p, NCR_VID, 0)) != nil && nctlr > 0){
 2097                 for(v = variant; v < &variant[nelem(variant)]; v++){
 2098                         if(p->did == v->did && p->rid <= v->maxrid)
 2099                                 break;
 2100                 }
 2101                 if(v >= &variant[nelem(variant)]) {
 2102                         print("no match\n");
 2103                         continue;
 2104                 }
 2105                 print(PRINTPREFIX "%s rev. 0x%2.2x intr=%d command=%4.4uX\n",
 2106                         v->name, p->rid, p->intl, p->pcr);
 2107 
 2108                 regpa = p->mem[1].bar;
 2109                 ba = 2;
 2110                 if(regpa & 0x04){
 2111                         if(p->mem[2].bar)
 2112                                 continue;
 2113                         ba++;
 2114                 }
 2115                 if(regpa == 0)
 2116                         print("regpa 0\n");
 2117                 regpa &= ~0xF;
 2118                 regva = vmap(regpa, p->mem[1].size);
 2119                 if(regva == 0)
 2120                         continue;
 2121 
 2122                 script = nil;
 2123                 scriptpa = 0;
 2124                 scriptva = nil;
 2125                 scriptma = nil;
 2126                 if((v->feature & LocalRAM) && sizeof(na_script) <= 4096){
 2127                         scriptpa = p->mem[ba].bar;
 2128                         if((scriptpa & 0x04) && p->mem[ba+1].bar){
 2129                                 vunmap(regva, p->mem[1].size);
 2130                                 continue;
 2131                         }
 2132                         scriptpa &= ~0x0F;
 2133                         scriptva = vmap(scriptpa, p->mem[ba].size);
 2134                         if(scriptva)
 2135                                 script = scriptva;
 2136                 }
 2137                 if(scriptpa == 0){
 2138                         /*
 2139                          * Either the map failed, or this chip does not have
 2140                          * local RAM. It will need a copy of the microcode.
 2141                          */
 2142                         scriptma = malloc(sizeof(na_script));
 2143                         if(scriptma == nil){
 2144                                 vunmap(regva, p->mem[1].size);
 2145                                 continue;
 2146                         }
 2147                         scriptpa = DMASEG(scriptma);
 2148                         script = scriptma;
 2149                 }
 2150 
 2151                 ctlr = malloc(sizeof(Controller));
 2152                 sdev = malloc(sizeof(SDev));
 2153                 if(ctlr == nil || sdev == nil){
 2154 buggery:
 2155                         if(ctlr)
 2156                                 free(ctlr);
 2157                         if(sdev)
 2158                                 free(sdev);
 2159                         if(scriptma)
 2160                                 free(scriptma);
 2161                         else if(scriptva)
 2162                                 vunmap(scriptva, p->mem[ba].size);
 2163                         if(regva)
 2164                                 vunmap(regva, p->mem[1].size);
 2165                         continue;
 2166                 }
 2167 
 2168                 if(dsaend == nil)
 2169                         dsaend = xalloc(sizeof *dsaend);
 2170                 lesetl(&dsaend->stateb, A_STATE_END);
 2171         //      lesetl(dsaend->next, DMASEG(dsaend));
 2172                 coherence();
 2173                 lesetl(ctlr->dsalist.head, DMASEG(dsaend));
 2174                 coherence();
 2175                 ctlr->dsalist.freechain = 0;
 2176 
 2177                 ctlr->n = regva;
 2178                 ctlr->v = v;
 2179                 ctlr->script = script;
 2180                 memmove(ctlr->script, na_script, sizeof(na_script));
 2181 
 2182                 /*
 2183                  * Because we don't yet have an abstraction for the
 2184                  * addresses as seen from the controller side (and on
 2185                  * the 386 it doesn't matter), the following three lines
 2186                  * are different between the 386 and alpha copies of
 2187                  * this driver.
 2188                  */
 2189                 USED(scriptpa);
 2190                 ctlr->scriptpa = p->mem[ba].bar & ~0x0F;
 2191                 if(!na_fixup(ctlr, p->mem[1].bar & ~0x0F, na_patches, NA_PATCHES, xfunc)){
 2192                         print("script fixup failed\n");
 2193                         goto buggery;
 2194                 }
 2195                 swabl(ctlr->script, ctlr->script, sizeof(na_script));
 2196 
 2197                 ctlr->pcidev = p;
 2198 
 2199                 sdev->ifc = &sd53c8xxifc;
 2200                 sdev->ctlr = ctlr;
 2201                 sdev->idno = '';
 2202                 if(!(v->feature & Wide))
 2203                         sdev->nunit = 8;
 2204                 else
 2205                         sdev->nunit = MAXTARGET;
 2206                 ctlr->sdev = sdev;
 2207                 
 2208                 if(head != nil)
 2209                         tail->next = sdev;
 2210                 else
 2211                         head = sdev;
 2212                 tail = sdev;
 2213 
 2214                 nctlr--;
 2215         }
 2216 
 2217         return head;
 2218 }
 2219 
 2220 static int
 2221 sd53c8xxenable(SDev* sdev)
 2222 {
 2223         Pcidev *pcidev;
 2224         Controller *ctlr;
 2225         char name[32];
 2226 
 2227         ctlr = sdev->ctlr;
 2228         pcidev = ctlr->pcidev;
 2229 
 2230         pcisetbme(pcidev);
 2231 
 2232         ilock(ctlr);
 2233         synctabinit(ctlr);
 2234         cribbios(ctlr);
 2235         reset(ctlr);
 2236         snprint(name, sizeof(name), "%s (%s)", sdev->name, sdev->ifc->name);
 2237         intrenable(pcidev->intl, sd53c8xxinterrupt, ctlr, pcidev->tbdf, name);
 2238         iunlock(ctlr);
 2239 
 2240         return 1;
 2241 }
 2242 
 2243 SDifc sd53c8xxifc = {
 2244         "53c8xx",                       /* name */
 2245 
 2246         sd53c8xxpnp,                    /* pnp */
 2247         nil,                            /* legacy */
 2248         sd53c8xxenable,                 /* enable */
 2249         nil,                            /* disable */
 2250 
 2251         scsiverify,                     /* verify */
 2252         scsionline,                     /* online */
 2253         sd53c8xxrio,                    /* rio */
 2254         nil,                            /* rctl */
 2255         nil,                            /* wctl */
 2256 
 2257         scsibio,                        /* bio */
 2258         nil,                            /* probe */
 2259         nil,                            /* clear */
 2260         nil,                            /* stat */
 2261 };
Cache object: b3e681f597e259e60381aa3af04d5ed6
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.
FreeBSD/Linux Kernel Cross Reference sys/alphapc/sd53c8xx.c

FreeBSD/Linux Kernel Cross Reference
sys/alphapc/sd53c8xx.c
