amd64_mem.c

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    1 /*-
    2  * Copyright (c) 1999 Michael Smith <msmith@freebsd.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD: releng/11.0/sys/amd64/amd64/amd64_mem.c 298433 2016-04-21 19:57:40Z pfg $");
   29 
   30 #include <sys/param.h>
   31 #include <sys/kernel.h>
   32 #include <sys/systm.h>
   33 #include <sys/malloc.h>
   34 #include <sys/memrange.h>
   35 #include <sys/smp.h>
   36 #include <sys/sysctl.h>
   37 
   38 #include <vm/vm.h>
   39 #include <vm/vm_param.h>
   40 #include <vm/pmap.h>
   41 
   42 #include <machine/cputypes.h>
   43 #include <machine/md_var.h>
   44 #include <machine/specialreg.h>
   45 
   46 /*
   47  * amd64 memory range operations
   48  *
   49  * This code will probably be impenetrable without reference to the
   50  * Intel Pentium Pro documentation or x86-64 programmers manual vol 2.
   51  */
   52 
   53 static char *mem_owner_bios = "BIOS";
   54 
   55 #define MR686_FIXMTRR   (1<<0)
   56 
   57 #define mrwithin(mr, a)                                                 \
   58         (((a) >= (mr)->mr_base) && ((a) < ((mr)->mr_base + (mr)->mr_len)))
   59 #define mroverlap(mra, mrb)                                             \
   60         (mrwithin(mra, mrb->mr_base) || mrwithin(mrb, mra->mr_base))
   61 
   62 #define mrvalid(base, len)                                              \
   63         ((!(base & ((1 << 12) - 1))) && /* base is multiple of 4k */    \
   64             ((len) >= (1 << 12)) &&     /* length is >= 4k */           \
   65             powerof2((len)) &&          /* ... and power of two */      \
   66             !((base) & ((len) - 1)))    /* range is not discontiuous */
   67 
   68 #define mrcopyflags(curr, new)                                          \
   69         (((curr) & ~MDF_ATTRMASK) | ((new) & MDF_ATTRMASK))
   70 
   71 static int mtrrs_disabled;
   72 SYSCTL_INT(_machdep, OID_AUTO, disable_mtrrs, CTLFLAG_RDTUN,
   73     &mtrrs_disabled, 0, "Disable amd64 MTRRs.");
   74 
   75 static void     amd64_mrinit(struct mem_range_softc *sc);
   76 static int      amd64_mrset(struct mem_range_softc *sc,
   77                     struct mem_range_desc *mrd, int *arg);
   78 static void     amd64_mrAPinit(struct mem_range_softc *sc);
   79 static void     amd64_mrreinit(struct mem_range_softc *sc);
   80 
   81 static struct mem_range_ops amd64_mrops = {
   82         amd64_mrinit,
   83         amd64_mrset,
   84         amd64_mrAPinit,
   85         amd64_mrreinit
   86 };
   87 
   88 /* XXX for AP startup hook */
   89 static u_int64_t mtrrcap, mtrrdef;
   90 
   91 /* The bitmask for the PhysBase and PhysMask fields of the variable MTRRs. */
   92 static u_int64_t mtrr_physmask;
   93 
   94 static struct mem_range_desc *mem_range_match(struct mem_range_softc *sc,
   95                     struct mem_range_desc *mrd);
   96 static void     amd64_mrfetch(struct mem_range_softc *sc);
   97 static int      amd64_mtrrtype(int flags);
   98 static int      amd64_mrt2mtrr(int flags, int oldval);
   99 static int      amd64_mtrrconflict(int flag1, int flag2);
  100 static void     amd64_mrstore(struct mem_range_softc *sc);
  101 static void     amd64_mrstoreone(void *arg);
  102 static struct mem_range_desc *amd64_mtrrfixsearch(struct mem_range_softc *sc,
  103                     u_int64_t addr);
  104 static int      amd64_mrsetlow(struct mem_range_softc *sc,
  105                     struct mem_range_desc *mrd, int *arg);
  106 static int      amd64_mrsetvariable(struct mem_range_softc *sc,
  107                     struct mem_range_desc *mrd, int *arg);
  108 
  109 /* amd64 MTRR type to memory range type conversion */
  110 static int amd64_mtrrtomrt[] = {
  111         MDF_UNCACHEABLE,
  112         MDF_WRITECOMBINE,
  113         MDF_UNKNOWN,
  114         MDF_UNKNOWN,
  115         MDF_WRITETHROUGH,
  116         MDF_WRITEPROTECT,
  117         MDF_WRITEBACK
  118 };
  119 
  120 #define MTRRTOMRTLEN nitems(amd64_mtrrtomrt)
  121 
  122 static int
  123 amd64_mtrr2mrt(int val)
  124 {
  125 
  126         if (val < 0 || val >= MTRRTOMRTLEN)
  127                 return (MDF_UNKNOWN);
  128         return (amd64_mtrrtomrt[val]);
  129 }
  130 
  131 /*
  132  * amd64 MTRR conflicts. Writeback and uncachable may overlap.
  133  */
  134 static int
  135 amd64_mtrrconflict(int flag1, int flag2)
  136 {
  137 
  138         flag1 &= MDF_ATTRMASK;
  139         flag2 &= MDF_ATTRMASK;
  140         if ((flag1 & MDF_UNKNOWN) || (flag2 & MDF_UNKNOWN))
  141                 return (1);
  142         if (flag1 == flag2 ||
  143             (flag1 == MDF_WRITEBACK && flag2 == MDF_UNCACHEABLE) ||
  144             (flag2 == MDF_WRITEBACK && flag1 == MDF_UNCACHEABLE))
  145                 return (0);
  146         return (1);
  147 }
  148 
  149 /*
  150  * Look for an exactly-matching range.
  151  */
  152 static struct mem_range_desc *
  153 mem_range_match(struct mem_range_softc *sc, struct mem_range_desc *mrd)
  154 {
  155         struct mem_range_desc *cand;
  156         int i;
  157 
  158         for (i = 0, cand = sc->mr_desc; i < sc->mr_ndesc; i++, cand++)
  159                 if ((cand->mr_base == mrd->mr_base) &&
  160                     (cand->mr_len == mrd->mr_len))
  161                         return (cand);
  162         return (NULL);
  163 }
  164 
  165 /*
  166  * Fetch the current mtrr settings from the current CPU (assumed to
  167  * all be in sync in the SMP case).  Note that if we are here, we
  168  * assume that MTRRs are enabled, and we may or may not have fixed
  169  * MTRRs.
  170  */
  171 static void
  172 amd64_mrfetch(struct mem_range_softc *sc)
  173 {
  174         struct mem_range_desc *mrd;
  175         u_int64_t msrv;
  176         int i, j, msr;
  177 
  178         mrd = sc->mr_desc;
  179 
  180         /* Get fixed-range MTRRs. */
  181         if (sc->mr_cap & MR686_FIXMTRR) {
  182                 msr = MSR_MTRR64kBase;
  183                 for (i = 0; i < (MTRR_N64K / 8); i++, msr++) {
  184                         msrv = rdmsr(msr);
  185                         for (j = 0; j < 8; j++, mrd++) {
  186                                 mrd->mr_flags =
  187                                     (mrd->mr_flags & ~MDF_ATTRMASK) |
  188                                     amd64_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE;
  189                                 if (mrd->mr_owner[0] == 0)
  190                                         strcpy(mrd->mr_owner, mem_owner_bios);
  191                                 msrv = msrv >> 8;
  192                         }
  193                 }
  194                 msr = MSR_MTRR16kBase;
  195                 for (i = 0; i < (MTRR_N16K / 8); i++, msr++) {
  196                         msrv = rdmsr(msr);
  197                         for (j = 0; j < 8; j++, mrd++) {
  198                                 mrd->mr_flags =
  199                                     (mrd->mr_flags & ~MDF_ATTRMASK) |
  200                                     amd64_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE;
  201                                 if (mrd->mr_owner[0] == 0)
  202                                         strcpy(mrd->mr_owner, mem_owner_bios);
  203                                 msrv = msrv >> 8;
  204                         }
  205                 }
  206                 msr = MSR_MTRR4kBase;
  207                 for (i = 0; i < (MTRR_N4K / 8); i++, msr++) {
  208                         msrv = rdmsr(msr);
  209                         for (j = 0; j < 8; j++, mrd++) {
  210                                 mrd->mr_flags =
  211                                     (mrd->mr_flags & ~MDF_ATTRMASK) |
  212                                     amd64_mtrr2mrt(msrv & 0xff) | MDF_ACTIVE;
  213                                 if (mrd->mr_owner[0] == 0)
  214                                         strcpy(mrd->mr_owner, mem_owner_bios);
  215                                 msrv = msrv >> 8;
  216                         }
  217                 }
  218         }
  219 
  220         /* Get remainder which must be variable MTRRs. */
  221         msr = MSR_MTRRVarBase;
  222         for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) {
  223                 msrv = rdmsr(msr);
  224                 mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) |
  225                     amd64_mtrr2mrt(msrv & MTRR_PHYSBASE_TYPE);
  226                 mrd->mr_base = msrv & mtrr_physmask;
  227                 msrv = rdmsr(msr + 1);
  228                 mrd->mr_flags = (msrv & MTRR_PHYSMASK_VALID) ?
  229                     (mrd->mr_flags | MDF_ACTIVE) :
  230                     (mrd->mr_flags & ~MDF_ACTIVE);
  231 
  232                 /* Compute the range from the mask. Ick. */
  233                 mrd->mr_len = (~(msrv & mtrr_physmask) &
  234                     (mtrr_physmask | 0xfffL)) + 1;
  235                 if (!mrvalid(mrd->mr_base, mrd->mr_len))
  236                         mrd->mr_flags |= MDF_BOGUS;
  237 
  238                 /* If unclaimed and active, must be the BIOS. */
  239                 if ((mrd->mr_flags & MDF_ACTIVE) && (mrd->mr_owner[0] == 0))
  240                         strcpy(mrd->mr_owner, mem_owner_bios);
  241         }
  242 }
  243 
  244 /*
  245  * Return the MTRR memory type matching a region's flags
  246  */
  247 static int
  248 amd64_mtrrtype(int flags)
  249 {
  250         int i;
  251 
  252         flags &= MDF_ATTRMASK;
  253 
  254         for (i = 0; i < MTRRTOMRTLEN; i++) {
  255                 if (amd64_mtrrtomrt[i] == MDF_UNKNOWN)
  256                         continue;
  257                 if (flags == amd64_mtrrtomrt[i])
  258                         return (i);
  259         }
  260         return (-1);
  261 }
  262 
  263 static int
  264 amd64_mrt2mtrr(int flags, int oldval)
  265 {
  266         int val;
  267 
  268         if ((val = amd64_mtrrtype(flags)) == -1)
  269                 return (oldval & 0xff);
  270         return (val & 0xff);
  271 }
  272 
  273 /*
  274  * Update running CPU(s) MTRRs to match the ranges in the descriptor
  275  * list.
  276  *
  277  * XXX Must be called with interrupts enabled.
  278  */
  279 static void
  280 amd64_mrstore(struct mem_range_softc *sc)
  281 {
  282 #ifdef SMP
  283         /*
  284          * We should use ipi_all_but_self() to call other CPUs into a
  285          * locking gate, then call a target function to do this work.
  286          * The "proper" solution involves a generalised locking gate
  287          * implementation, not ready yet.
  288          */
  289         smp_rendezvous(NULL, amd64_mrstoreone, NULL, sc);
  290 #else
  291         disable_intr();                         /* disable interrupts */
  292         amd64_mrstoreone(sc);
  293         enable_intr();
  294 #endif
  295 }
  296 
  297 /*
  298  * Update the current CPU's MTRRs with those represented in the
  299  * descriptor list.  Note that we do this wholesale rather than just
  300  * stuffing one entry; this is simpler (but slower, of course).
  301  */
  302 static void
  303 amd64_mrstoreone(void *arg)
  304 {
  305         struct mem_range_softc *sc = arg;
  306         struct mem_range_desc *mrd;
  307         u_int64_t omsrv, msrv;
  308         int i, j, msr;
  309         u_long cr0, cr4;
  310 
  311         mrd = sc->mr_desc;
  312 
  313         critical_enter();
  314 
  315         /* Disable PGE. */
  316         cr4 = rcr4();
  317         load_cr4(cr4 & ~CR4_PGE);
  318 
  319         /* Disable caches (CD = 1, NW = 0). */
  320         cr0 = rcr0();
  321         load_cr0((cr0 & ~CR0_NW) | CR0_CD);
  322 
  323         /* Flushes caches and TLBs. */
  324         wbinvd();
  325         invltlb();
  326 
  327         /* Disable MTRRs (E = 0). */
  328         wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRR_DEF_ENABLE);
  329 
  330         /* Set fixed-range MTRRs. */
  331         if (sc->mr_cap & MR686_FIXMTRR) {
  332                 msr = MSR_MTRR64kBase;
  333                 for (i = 0; i < (MTRR_N64K / 8); i++, msr++) {
  334                         msrv = 0;
  335                         omsrv = rdmsr(msr);
  336                         for (j = 7; j >= 0; j--) {
  337                                 msrv = msrv << 8;
  338                                 msrv |= amd64_mrt2mtrr((mrd + j)->mr_flags,
  339                                     omsrv >> (j * 8));
  340                         }
  341                         wrmsr(msr, msrv);
  342                         mrd += 8;
  343                 }
  344                 msr = MSR_MTRR16kBase;
  345                 for (i = 0; i < (MTRR_N16K / 8); i++, msr++) {
  346                         msrv = 0;
  347                         omsrv = rdmsr(msr);
  348                         for (j = 7; j >= 0; j--) {
  349                                 msrv = msrv << 8;
  350                                 msrv |= amd64_mrt2mtrr((mrd + j)->mr_flags,
  351                                     omsrv >> (j * 8));
  352                         }
  353                         wrmsr(msr, msrv);
  354                         mrd += 8;
  355                 }
  356                 msr = MSR_MTRR4kBase;
  357                 for (i = 0; i < (MTRR_N4K / 8); i++, msr++) {
  358                         msrv = 0;
  359                         omsrv = rdmsr(msr);
  360                         for (j = 7; j >= 0; j--) {
  361                                 msrv = msrv << 8;
  362                                 msrv |= amd64_mrt2mtrr((mrd + j)->mr_flags,
  363                                     omsrv >> (j * 8));
  364                         }
  365                         wrmsr(msr, msrv);
  366                         mrd += 8;
  367                 }
  368         }
  369 
  370         /* Set remainder which must be variable MTRRs. */
  371         msr = MSR_MTRRVarBase;
  372         for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) {
  373                 /* base/type register */
  374                 omsrv = rdmsr(msr);
  375                 if (mrd->mr_flags & MDF_ACTIVE) {
  376                         msrv = mrd->mr_base & mtrr_physmask;
  377                         msrv |= amd64_mrt2mtrr(mrd->mr_flags, omsrv);
  378                 } else {
  379                         msrv = 0;
  380                 }
  381                 wrmsr(msr, msrv);
  382 
  383                 /* mask/active register */
  384                 if (mrd->mr_flags & MDF_ACTIVE) {
  385                         msrv = MTRR_PHYSMASK_VALID |
  386                             rounddown2(mtrr_physmask, mrd->mr_len);
  387                 } else {
  388                         msrv = 0;
  389                 }
  390                 wrmsr(msr + 1, msrv);
  391         }
  392 
  393         /* Flush caches and TLBs. */
  394         wbinvd();
  395         invltlb();
  396 
  397         /* Enable MTRRs. */
  398         wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | MTRR_DEF_ENABLE);
  399 
  400         /* Restore caches and PGE. */
  401         load_cr0(cr0);
  402         load_cr4(cr4);
  403 
  404         critical_exit();
  405 }
  406 
  407 /*
  408  * Hunt for the fixed MTRR referencing (addr)
  409  */
  410 static struct mem_range_desc *
  411 amd64_mtrrfixsearch(struct mem_range_softc *sc, u_int64_t addr)
  412 {
  413         struct mem_range_desc *mrd;
  414         int i;
  415 
  416         for (i = 0, mrd = sc->mr_desc; i < (MTRR_N64K + MTRR_N16K + MTRR_N4K);
  417              i++, mrd++)
  418                 if ((addr >= mrd->mr_base) &&
  419                     (addr < (mrd->mr_base + mrd->mr_len)))
  420                         return (mrd);
  421         return (NULL);
  422 }
  423 
  424 /*
  425  * Try to satisfy the given range request by manipulating the fixed
  426  * MTRRs that cover low memory.
  427  *
  428  * Note that we try to be generous here; we'll bloat the range out to
  429  * the next higher/lower boundary to avoid the consumer having to know
  430  * too much about the mechanisms here.
  431  *
  432  * XXX note that this will have to be updated when we start supporting
  433  * "busy" ranges.
  434  */
  435 static int
  436 amd64_mrsetlow(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg)
  437 {
  438         struct mem_range_desc *first_md, *last_md, *curr_md;
  439 
  440         /* Range check. */
  441         if (((first_md = amd64_mtrrfixsearch(sc, mrd->mr_base)) == NULL) ||
  442             ((last_md = amd64_mtrrfixsearch(sc, mrd->mr_base + mrd->mr_len - 1)) == NULL))
  443                 return (EINVAL);
  444 
  445         /* Check that we aren't doing something risky. */
  446         if (!(mrd->mr_flags & MDF_FORCE))
  447                 for (curr_md = first_md; curr_md <= last_md; curr_md++) {
  448                         if ((curr_md->mr_flags & MDF_ATTRMASK) == MDF_UNKNOWN)
  449                                 return (EACCES);
  450                 }
  451 
  452         /* Set flags, clear set-by-firmware flag. */
  453         for (curr_md = first_md; curr_md <= last_md; curr_md++) {
  454                 curr_md->mr_flags = mrcopyflags(curr_md->mr_flags &
  455                     ~MDF_FIRMWARE, mrd->mr_flags);
  456                 bcopy(mrd->mr_owner, curr_md->mr_owner, sizeof(mrd->mr_owner));
  457         }
  458 
  459         return (0);
  460 }
  461 
  462 /*
  463  * Modify/add a variable MTRR to satisfy the request.
  464  *
  465  * XXX needs to be updated to properly support "busy" ranges.
  466  */
  467 static int
  468 amd64_mrsetvariable(struct mem_range_softc *sc, struct mem_range_desc *mrd,
  469     int *arg)
  470 {
  471         struct mem_range_desc *curr_md, *free_md;
  472         int i;
  473 
  474         /*
  475          * Scan the currently active variable descriptors, look for
  476          * one we exactly match (straight takeover) and for possible
  477          * accidental overlaps.
  478          *
  479          * Keep track of the first empty variable descriptor in case
  480          * we can't perform a takeover.
  481          */
  482         i = (sc->mr_cap & MR686_FIXMTRR) ? MTRR_N64K + MTRR_N16K + MTRR_N4K : 0;
  483         curr_md = sc->mr_desc + i;
  484         free_md = NULL;
  485         for (; i < sc->mr_ndesc; i++, curr_md++) {
  486                 if (curr_md->mr_flags & MDF_ACTIVE) {
  487                         /* Exact match? */
  488                         if ((curr_md->mr_base == mrd->mr_base) &&
  489                             (curr_md->mr_len == mrd->mr_len)) {
  490 
  491                                 /* Whoops, owned by someone. */
  492                                 if (curr_md->mr_flags & MDF_BUSY)
  493                                         return (EBUSY);
  494 
  495                                 /* Check that we aren't doing something risky */
  496                                 if (!(mrd->mr_flags & MDF_FORCE) &&
  497                                     ((curr_md->mr_flags & MDF_ATTRMASK) ==
  498                                     MDF_UNKNOWN))
  499                                         return (EACCES);
  500 
  501                                 /* Ok, just hijack this entry. */
  502                                 free_md = curr_md;
  503                                 break;
  504                         }
  505 
  506                         /* Non-exact overlap? */
  507                         if (mroverlap(curr_md, mrd)) {
  508                                 /* Between conflicting region types? */
  509                                 if (amd64_mtrrconflict(curr_md->mr_flags,
  510                                     mrd->mr_flags))
  511                                         return (EINVAL);
  512                         }
  513                 } else if (free_md == NULL) {
  514                         free_md = curr_md;
  515                 }
  516         }
  517 
  518         /* Got somewhere to put it? */
  519         if (free_md == NULL)
  520                 return (ENOSPC);
  521 
  522         /* Set up new descriptor. */
  523         free_md->mr_base = mrd->mr_base;
  524         free_md->mr_len = mrd->mr_len;
  525         free_md->mr_flags = mrcopyflags(MDF_ACTIVE, mrd->mr_flags);
  526         bcopy(mrd->mr_owner, free_md->mr_owner, sizeof(mrd->mr_owner));
  527         return (0);
  528 }
  529 
  530 /*
  531  * Handle requests to set memory range attributes by manipulating MTRRs.
  532  */
  533 static int
  534 amd64_mrset(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg)
  535 {
  536         struct mem_range_desc *targ;
  537         int error, i;
  538 
  539         switch (*arg) {
  540         case MEMRANGE_SET_UPDATE:
  541                 /*
  542                  * Make sure that what's being asked for is even
  543                  * possible at all.
  544                  */
  545                 if (!mrvalid(mrd->mr_base, mrd->mr_len) ||
  546                     amd64_mtrrtype(mrd->mr_flags) == -1)
  547                         return (EINVAL);
  548 
  549 #define FIXTOP  ((MTRR_N64K * 0x10000) + (MTRR_N16K * 0x4000) + (MTRR_N4K * 0x1000))
  550 
  551                 /* Are the "low memory" conditions applicable? */
  552                 if ((sc->mr_cap & MR686_FIXMTRR) &&
  553                     ((mrd->mr_base + mrd->mr_len) <= FIXTOP)) {
  554                         if ((error = amd64_mrsetlow(sc, mrd, arg)) != 0)
  555                                 return (error);
  556                 } else {
  557                         /* It's time to play with variable MTRRs. */
  558                         if ((error = amd64_mrsetvariable(sc, mrd, arg)) != 0)
  559                                 return (error);
  560                 }
  561                 break;
  562 
  563         case MEMRANGE_SET_REMOVE:
  564                 if ((targ = mem_range_match(sc, mrd)) == NULL)
  565                         return (ENOENT);
  566                 if (targ->mr_flags & MDF_FIXACTIVE)
  567                         return (EPERM);
  568                 if (targ->mr_flags & MDF_BUSY)
  569                         return (EBUSY);
  570                 targ->mr_flags &= ~MDF_ACTIVE;
  571                 targ->mr_owner[0] = 0;
  572                 break;
  573 
  574         default:
  575                 return (EOPNOTSUPP);
  576         }
  577 
  578         /*
  579          * Ensure that the direct map region does not contain any mappings
  580          * that span MTRRs of different types.  However, the fixed MTRRs can
  581          * be ignored, because a large page mapping the first 1 MB of physical
  582          * memory is a special case that the processor handles.  The entire
  583          * TLB will be invalidated by amd64_mrstore(), so pmap_demote_DMAP()
  584          * needn't do it.
  585          */
  586         i = (sc->mr_cap & MR686_FIXMTRR) ? MTRR_N64K + MTRR_N16K + MTRR_N4K : 0;
  587         mrd = sc->mr_desc + i;
  588         for (; i < sc->mr_ndesc; i++, mrd++) {
  589                 if ((mrd->mr_flags & (MDF_ACTIVE | MDF_BOGUS)) == MDF_ACTIVE)
  590                         pmap_demote_DMAP(mrd->mr_base, mrd->mr_len, FALSE);
  591         }
  592 
  593         /* Update the hardware. */
  594         amd64_mrstore(sc);
  595 
  596         /* Refetch to see where we're at. */
  597         amd64_mrfetch(sc);
  598         return (0);
  599 }
  600 
  601 /*
  602  * Work out how many ranges we support, initialise storage for them,
  603  * and fetch the initial settings.
  604  */
  605 static void
  606 amd64_mrinit(struct mem_range_softc *sc)
  607 {
  608         struct mem_range_desc *mrd;
  609         u_int regs[4];
  610         int i, nmdesc = 0, pabits;
  611 
  612         mtrrcap = rdmsr(MSR_MTRRcap);
  613         mtrrdef = rdmsr(MSR_MTRRdefType);
  614 
  615         /* For now, bail out if MTRRs are not enabled. */
  616         if (!(mtrrdef & MTRR_DEF_ENABLE)) {
  617                 if (bootverbose)
  618                         printf("CPU supports MTRRs but not enabled\n");
  619                 return;
  620         }
  621         nmdesc = mtrrcap & MTRR_CAP_VCNT;
  622 
  623         /*
  624          * Determine the size of the PhysMask and PhysBase fields in
  625          * the variable range MTRRs.  If the extended CPUID 0x80000008
  626          * is present, use that to figure out how many physical
  627          * address bits the CPU supports.  Otherwise, default to 36
  628          * address bits.
  629          */
  630         if (cpu_exthigh >= 0x80000008) {
  631                 do_cpuid(0x80000008, regs);
  632                 pabits = regs[0] & 0xff;
  633         } else
  634                 pabits = 36;
  635         mtrr_physmask = ((1UL << pabits) - 1) & ~0xfffUL;
  636 
  637         /* If fixed MTRRs supported and enabled. */
  638         if ((mtrrcap & MTRR_CAP_FIXED) && (mtrrdef & MTRR_DEF_FIXED_ENABLE)) {
  639                 sc->mr_cap = MR686_FIXMTRR;
  640                 nmdesc += MTRR_N64K + MTRR_N16K + MTRR_N4K;
  641         }
  642 
  643         sc->mr_desc = malloc(nmdesc * sizeof(struct mem_range_desc), M_MEMDESC,
  644             M_WAITOK | M_ZERO);
  645         sc->mr_ndesc = nmdesc;
  646 
  647         mrd = sc->mr_desc;
  648 
  649         /* Populate the fixed MTRR entries' base/length. */
  650         if (sc->mr_cap & MR686_FIXMTRR) {
  651                 for (i = 0; i < MTRR_N64K; i++, mrd++) {
  652                         mrd->mr_base = i * 0x10000;
  653                         mrd->mr_len = 0x10000;
  654                         mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN |
  655                             MDF_FIXACTIVE;
  656                 }
  657                 for (i = 0; i < MTRR_N16K; i++, mrd++) {
  658                         mrd->mr_base = i * 0x4000 + 0x80000;
  659                         mrd->mr_len = 0x4000;
  660                         mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN |
  661                             MDF_FIXACTIVE;
  662                 }
  663                 for (i = 0; i < MTRR_N4K; i++, mrd++) {
  664                         mrd->mr_base = i * 0x1000 + 0xc0000;
  665                         mrd->mr_len = 0x1000;
  666                         mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN |
  667                             MDF_FIXACTIVE;
  668                 }
  669         }
  670 
  671         /*
  672          * Get current settings, anything set now is considered to
  673          * have been set by the firmware. (XXX has something already
  674          * played here?)
  675          */
  676         amd64_mrfetch(sc);
  677         mrd = sc->mr_desc;
  678         for (i = 0; i < sc->mr_ndesc; i++, mrd++) {
  679                 if (mrd->mr_flags & MDF_ACTIVE)
  680                         mrd->mr_flags |= MDF_FIRMWARE;
  681         }
  682 
  683         /*
  684          * Ensure that the direct map region does not contain any mappings
  685          * that span MTRRs of different types.  However, the fixed MTRRs can
  686          * be ignored, because a large page mapping the first 1 MB of physical
  687          * memory is a special case that the processor handles.  Invalidate
  688          * any old TLB entries that might hold inconsistent memory type
  689          * information. 
  690          */
  691         i = (sc->mr_cap & MR686_FIXMTRR) ? MTRR_N64K + MTRR_N16K + MTRR_N4K : 0;
  692         mrd = sc->mr_desc + i;
  693         for (; i < sc->mr_ndesc; i++, mrd++) {
  694                 if ((mrd->mr_flags & (MDF_ACTIVE | MDF_BOGUS)) == MDF_ACTIVE)
  695                         pmap_demote_DMAP(mrd->mr_base, mrd->mr_len, TRUE);
  696         }
  697 }
  698 
  699 /*
  700  * Initialise MTRRs on an AP after the BSP has run the init code.
  701  */
  702 static void
  703 amd64_mrAPinit(struct mem_range_softc *sc)
  704 {
  705 
  706         amd64_mrstoreone(sc);
  707         wrmsr(MSR_MTRRdefType, mtrrdef);
  708 }
  709 
  710 /*
  711  * Re-initialise running CPU(s) MTRRs to match the ranges in the descriptor
  712  * list.
  713  *
  714  * XXX Must be called with interrupts enabled.
  715  */
  716 static void
  717 amd64_mrreinit(struct mem_range_softc *sc)
  718 {
  719 #ifdef SMP
  720         /*
  721          * We should use ipi_all_but_self() to call other CPUs into a
  722          * locking gate, then call a target function to do this work.
  723          * The "proper" solution involves a generalised locking gate
  724          * implementation, not ready yet.
  725          */
  726         smp_rendezvous(NULL, (void *)amd64_mrAPinit, NULL, sc);
  727 #else
  728         disable_intr();                         /* disable interrupts */
  729         amd64_mrAPinit(sc);
  730         enable_intr();
  731 #endif
  732 }
  733 
  734 static void
  735 amd64_mem_drvinit(void *unused)
  736 {
  737 
  738         if (mtrrs_disabled)
  739                 return;
  740         if (!(cpu_feature & CPUID_MTRR))
  741                 return;
  742         if ((cpu_id & 0xf00) != 0x600 && (cpu_id & 0xf00) != 0xf00)
  743                 return;
  744         switch (cpu_vendor_id) {
  745         case CPU_VENDOR_INTEL:
  746         case CPU_VENDOR_AMD:
  747         case CPU_VENDOR_CENTAUR:
  748                 break;
  749         default:
  750                 return;
  751         }
  752         mem_range_softc.mr_op = &amd64_mrops;
  753 }
  754 SYSINIT(amd64memdev, SI_SUB_DRIVERS, SI_ORDER_FIRST, amd64_mem_drvinit, NULL);
Cache object: 560883699a7fb9e1bbf3cbe20c06cfd6
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FreeBSD/Linux Kernel Cross Reference sys/amd64/amd64/amd64_mem.c

FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/amd64_mem.c
