The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/amd64_mem.c

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    1 /*-
    2  * Copyright (c) 1999 Michael Smith <msmith@freebsd.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD: releng/5.2/sys/amd64/amd64/amd64_mem.c 123180 2003-12-06 23:19:47Z peter $");
   29 
   30 #include <sys/param.h>
   31 #include <sys/kernel.h>
   32 #include <sys/systm.h>
   33 #include <sys/malloc.h>
   34 #include <sys/memrange.h>
   35 #include <sys/smp.h>
   36 #include <sys/sysctl.h>
   37 
   38 #include <machine/md_var.h>
   39 #include <machine/specialreg.h>
   40 
   41 /*
   42  * amd64 memory range operations
   43  *
   44  * This code will probably be impenetrable without reference to the
   45  * Intel Pentium Pro documentation or x86-64 programmers manual vol 2.
   46  */
   47 
   48 static char *mem_owner_bios = "BIOS";
   49 
   50 #define MR686_FIXMTRR   (1<<0)
   51 
   52 #define mrwithin(mr, a) \
   53     (((a) >= (mr)->mr_base) && ((a) < ((mr)->mr_base + (mr)->mr_len)))
   54 #define mroverlap(mra, mrb) \
   55     (mrwithin(mra, mrb->mr_base) || mrwithin(mrb, mra->mr_base))
   56 
   57 #define mrvalid(base, len)                                              \
   58     ((!(base & ((1 << 12) - 1))) &&     /* base is multiple of 4k */    \
   59      ((len) >= (1 << 12)) &&            /* length is >= 4k */           \
   60      powerof2((len)) &&                 /* ... and power of two */      \
   61      !((base) & ((len) - 1)))           /* range is not discontiuous */
   62 
   63 #define mrcopyflags(curr, new) (((curr) & ~MDF_ATTRMASK) | ((new) & MDF_ATTRMASK))
   64 
   65 static int                      mtrrs_disabled;
   66 TUNABLE_INT("machdep.disable_mtrrs", &mtrrs_disabled);
   67 SYSCTL_INT(_machdep, OID_AUTO, disable_mtrrs, CTLFLAG_RDTUN,
   68         &mtrrs_disabled, 0, "Disable amd64 MTRRs.");
   69 
   70 static void                     amd64_mrinit(struct mem_range_softc *sc);
   71 static int                      amd64_mrset(struct mem_range_softc *sc,
   72                                            struct mem_range_desc *mrd,
   73                                            int *arg);
   74 static void                     amd64_mrAPinit(struct mem_range_softc *sc);
   75 
   76 static struct mem_range_ops amd64_mrops = {
   77         amd64_mrinit,
   78         amd64_mrset,
   79         amd64_mrAPinit
   80 };
   81 
   82 /* XXX for AP startup hook */
   83 static u_int64_t                mtrrcap, mtrrdef;
   84 
   85 static struct mem_range_desc    *mem_range_match(struct mem_range_softc *sc,
   86                                                  struct mem_range_desc *mrd);
   87 static void                     amd64_mrfetch(struct mem_range_softc *sc);
   88 static int                      amd64_mtrrtype(int flags);
   89 static int                      amd64_mrt2mtrr(int flags, int oldval);
   90 static int                      amd64_mtrrconflict(int flag1, int flag2);
   91 static void                     amd64_mrstore(struct mem_range_softc *sc);
   92 static void                     amd64_mrstoreone(void *arg);
   93 static struct mem_range_desc    *amd64_mtrrfixsearch(struct mem_range_softc *sc,
   94                                                     u_int64_t addr);
   95 static int                      amd64_mrsetlow(struct mem_range_softc *sc,
   96                                               struct mem_range_desc *mrd,
   97                                               int *arg);
   98 static int                      amd64_mrsetvariable(struct mem_range_softc *sc,
   99                                                    struct mem_range_desc *mrd,
  100                                                    int *arg);
  101 
  102 /* amd64 MTRR type to memory range type conversion */
  103 static int amd64_mtrrtomrt[] = {
  104     MDF_UNCACHEABLE,
  105     MDF_WRITECOMBINE,
  106     MDF_UNKNOWN,
  107     MDF_UNKNOWN,
  108     MDF_WRITETHROUGH,
  109     MDF_WRITEPROTECT,
  110     MDF_WRITEBACK
  111 };
  112 
  113 #define MTRRTOMRTLEN (sizeof(amd64_mtrrtomrt) / sizeof(amd64_mtrrtomrt[0]))
  114 
  115 static int
  116 amd64_mtrr2mrt(int val)
  117 {
  118         if (val < 0 || val >= MTRRTOMRTLEN)
  119                 return MDF_UNKNOWN;
  120         return amd64_mtrrtomrt[val];
  121 }
  122 
  123 /* 
  124  * amd64 MTRR conflicts. Writeback and uncachable may overlap.
  125  */
  126 static int
  127 amd64_mtrrconflict(int flag1, int flag2)
  128 {
  129         flag1 &= MDF_ATTRMASK;
  130         flag2 &= MDF_ATTRMASK;
  131         if ((flag1 & MDF_UNKNOWN) || (flag2 & MDF_UNKNOWN))
  132                 return 1;
  133         if (flag1 == flag2 ||
  134             (flag1 == MDF_WRITEBACK && flag2 == MDF_UNCACHEABLE) ||
  135             (flag2 == MDF_WRITEBACK && flag1 == MDF_UNCACHEABLE))
  136                 return 0;
  137         return 1;
  138 }
  139 
  140 /*
  141  * Look for an exactly-matching range.
  142  */
  143 static struct mem_range_desc *
  144 mem_range_match(struct mem_range_softc *sc, struct mem_range_desc *mrd) 
  145 {
  146     struct mem_range_desc       *cand;
  147     int                         i;
  148         
  149     for (i = 0, cand = sc->mr_desc; i < sc->mr_ndesc; i++, cand++)
  150         if ((cand->mr_base == mrd->mr_base) &&
  151             (cand->mr_len == mrd->mr_len))
  152             return(cand);
  153     return(NULL);
  154 }
  155 
  156 /*
  157  * Fetch the current mtrr settings from the current CPU (assumed to all
  158  * be in sync in the SMP case).  Note that if we are here, we assume
  159  * that MTRRs are enabled, and we may or may not have fixed MTRRs.
  160  */
  161 static void
  162 amd64_mrfetch(struct mem_range_softc *sc)
  163 {
  164     struct mem_range_desc       *mrd;
  165     u_int64_t                   msrv;
  166     int                         i, j, msr;
  167 
  168     mrd = sc->mr_desc;
  169 
  170     /* Get fixed-range MTRRs */
  171     if (sc->mr_cap & MR686_FIXMTRR) {
  172         msr = MSR_MTRR64kBase;
  173         for (i = 0; i < (MTRR_N64K / 8); i++, msr++) {
  174             msrv = rdmsr(msr);
  175             for (j = 0; j < 8; j++, mrd++) {
  176                 mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) |
  177                     amd64_mtrr2mrt(msrv & 0xff) |
  178                     MDF_ACTIVE;
  179                 if (mrd->mr_owner[0] == 0)
  180                     strcpy(mrd->mr_owner, mem_owner_bios);
  181                 msrv = msrv >> 8;
  182             }
  183         }
  184         msr = MSR_MTRR16kBase;
  185         for (i = 0; i < (MTRR_N16K / 8); i++, msr++) {
  186             msrv = rdmsr(msr);
  187             for (j = 0; j < 8; j++, mrd++) {
  188                 mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) |
  189                     amd64_mtrr2mrt(msrv & 0xff) |
  190                     MDF_ACTIVE;
  191                 if (mrd->mr_owner[0] == 0)
  192                     strcpy(mrd->mr_owner, mem_owner_bios);
  193                 msrv = msrv >> 8;
  194             }
  195         }
  196         msr = MSR_MTRR4kBase;
  197         for (i = 0; i < (MTRR_N4K / 8); i++, msr++) {
  198             msrv = rdmsr(msr);
  199             for (j = 0; j < 8; j++, mrd++) {
  200                 mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) |
  201                     amd64_mtrr2mrt(msrv & 0xff) |
  202                     MDF_ACTIVE;
  203                 if (mrd->mr_owner[0] == 0)
  204                     strcpy(mrd->mr_owner, mem_owner_bios);
  205                 msrv = msrv >> 8;
  206             }
  207         }
  208     }
  209 
  210     /* Get remainder which must be variable MTRRs */
  211     msr = MSR_MTRRVarBase;
  212     for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) {
  213         msrv = rdmsr(msr);
  214         mrd->mr_flags = (mrd->mr_flags & ~MDF_ATTRMASK) |
  215             amd64_mtrr2mrt(msrv & 0xff);
  216         mrd->mr_base = msrv & 0x000000fffffff000L;
  217         msrv = rdmsr(msr + 1);
  218         mrd->mr_flags = (msrv & 0x800) ? 
  219             (mrd->mr_flags | MDF_ACTIVE) :
  220             (mrd->mr_flags & ~MDF_ACTIVE);
  221         /* Compute the range from the mask. Ick. */
  222         mrd->mr_len = (~(msrv & 0x000000fffffff000L) & 0x000000ffffffffffL) + 1;
  223         if (!mrvalid(mrd->mr_base, mrd->mr_len))
  224             mrd->mr_flags |= MDF_BOGUS;
  225         /* If unclaimed and active, must be the BIOS */
  226         if ((mrd->mr_flags & MDF_ACTIVE) && (mrd->mr_owner[0] == 0))
  227             strcpy(mrd->mr_owner, mem_owner_bios);
  228     }
  229 }
  230 
  231 /*
  232  * Return the MTRR memory type matching a region's flags
  233  */
  234 static int
  235 amd64_mtrrtype(int flags)
  236 {
  237     int         i;
  238 
  239     flags &= MDF_ATTRMASK;
  240 
  241     for (i = 0; i < MTRRTOMRTLEN; i++) {
  242         if (amd64_mtrrtomrt[i] == MDF_UNKNOWN)
  243             continue;
  244         if (flags == amd64_mtrrtomrt[i])
  245             return(i);
  246     }
  247     return(-1);
  248 }
  249 
  250 static int
  251 amd64_mrt2mtrr(int flags, int oldval)
  252 {
  253         int val;
  254 
  255         if ((val = amd64_mtrrtype(flags)) == -1)
  256                 return oldval & 0xff;
  257         return val & 0xff;
  258 }
  259 
  260 /*
  261  * Update running CPU(s) MTRRs to match the ranges in the descriptor
  262  * list.
  263  *
  264  * XXX Must be called with interrupts enabled.
  265  */
  266 static void
  267 amd64_mrstore(struct mem_range_softc *sc)
  268 {
  269 #ifdef SMP
  270     /*
  271      * We should use ipi_all_but_self() to call other CPUs into a 
  272      * locking gate, then call a target function to do this work.
  273      * The "proper" solution involves a generalised locking gate
  274      * implementation, not ready yet.
  275      */
  276     smp_rendezvous(NULL, amd64_mrstoreone, NULL, (void *)sc);
  277 #else
  278     disable_intr();                             /* disable interrupts */
  279     amd64_mrstoreone((void *)sc);
  280     enable_intr();
  281 #endif
  282 }
  283 
  284 /*
  285  * Update the current CPU's MTRRs with those represented in the
  286  * descriptor list.  Note that we do this wholesale rather than
  287  * just stuffing one entry; this is simpler (but slower, of course).
  288  */
  289 static void
  290 amd64_mrstoreone(void *arg)
  291 {
  292     struct mem_range_softc      *sc = (struct mem_range_softc *)arg;
  293     struct mem_range_desc       *mrd;
  294     u_int64_t                   omsrv, msrv;
  295     int                         i, j, msr;
  296     u_int                       cr4save;
  297 
  298     mrd = sc->mr_desc;
  299 
  300     cr4save = rcr4();                           /* save cr4 */
  301     if (cr4save & CR4_PGE)
  302         load_cr4(cr4save & ~CR4_PGE);
  303     load_cr0((rcr0() & ~CR0_NW) | CR0_CD);      /* disable caches (CD = 1, NW = 0) */
  304     wbinvd();                                   /* flush caches, TLBs */
  305     wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~0x800);    /* disable MTRRs (E = 0) */
  306 
  307     /* Set fixed-range MTRRs */
  308     if (sc->mr_cap & MR686_FIXMTRR) {
  309         msr = MSR_MTRR64kBase;
  310         for (i = 0; i < (MTRR_N64K / 8); i++, msr++) {
  311             msrv = 0;
  312             omsrv = rdmsr(msr);
  313             for (j = 7; j >= 0; j--) {
  314                 msrv = msrv << 8;
  315                 msrv |= amd64_mrt2mtrr((mrd + j)->mr_flags, omsrv >> (j*8));
  316             }
  317             wrmsr(msr, msrv);
  318             mrd += 8;
  319         }
  320         msr = MSR_MTRR16kBase;
  321         for (i = 0; i < (MTRR_N16K / 8); i++, msr++) {
  322             msrv = 0;
  323             omsrv = rdmsr(msr);
  324             for (j = 7; j >= 0; j--) {
  325                 msrv = msrv << 8;
  326                 msrv |= amd64_mrt2mtrr((mrd + j)->mr_flags, omsrv >> (j*8));
  327             }
  328             wrmsr(msr, msrv);
  329             mrd += 8;
  330         }
  331         msr = MSR_MTRR4kBase;
  332         for (i = 0; i < (MTRR_N4K / 8); i++, msr++) {
  333             msrv = 0;
  334             omsrv = rdmsr(msr);
  335             for (j = 7; j >= 0; j--) {
  336                 msrv = msrv << 8;
  337                 msrv |= amd64_mrt2mtrr((mrd + j)->mr_flags, omsrv >> (j*8));
  338             }
  339             wrmsr(msr, msrv);
  340             mrd += 8;
  341         }
  342     }
  343 
  344     /* Set remainder which must be variable MTRRs */
  345     msr = MSR_MTRRVarBase;
  346     for (; (mrd - sc->mr_desc) < sc->mr_ndesc; msr += 2, mrd++) {
  347         /* base/type register */
  348         omsrv = rdmsr(msr);
  349         if (mrd->mr_flags & MDF_ACTIVE) {
  350             msrv = mrd->mr_base & 0x000000fffffff000L;
  351             msrv |= amd64_mrt2mtrr(mrd->mr_flags, omsrv);
  352         } else {
  353             msrv = 0;
  354         }
  355         wrmsr(msr, msrv);       
  356             
  357         /* mask/active register */
  358         if (mrd->mr_flags & MDF_ACTIVE) {
  359             msrv = 0x800 | (~(mrd->mr_len - 1) & 0x000000fffffff000L);
  360         } else {
  361             msrv = 0;
  362         }
  363         wrmsr(msr + 1, msrv);
  364     }
  365     wbinvd();                                                   /* flush caches, TLBs */
  366     wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) | 0x800);     /* restore MTRR state */
  367     load_cr0(rcr0() & ~(CR0_CD | CR0_NW));                      /* enable caches CD = 0 and NW = 0 */
  368     load_cr4(cr4save);                                          /* restore cr4 */
  369 }
  370 
  371 /*
  372  * Hunt for the fixed MTRR referencing (addr)
  373  */
  374 static struct mem_range_desc *
  375 amd64_mtrrfixsearch(struct mem_range_softc *sc, u_int64_t addr)
  376 {
  377     struct mem_range_desc *mrd;
  378     int                 i;
  379     
  380     for (i = 0, mrd = sc->mr_desc; i < (MTRR_N64K + MTRR_N16K + MTRR_N4K); i++, mrd++)
  381         if ((addr >= mrd->mr_base) && (addr < (mrd->mr_base + mrd->mr_len)))
  382             return(mrd);
  383     return(NULL);
  384 }
  385 
  386 /*
  387  * Try to satisfy the given range request by manipulating the fixed MTRRs that
  388  * cover low memory.
  389  *
  390  * Note that we try to be generous here; we'll bloat the range out to the 
  391  * next higher/lower boundary to avoid the consumer having to know too much
  392  * about the mechanisms here.
  393  *
  394  * XXX note that this will have to be updated when we start supporting "busy" ranges.
  395  */
  396 static int
  397 amd64_mrsetlow(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg)
  398 {
  399     struct mem_range_desc       *first_md, *last_md, *curr_md;
  400 
  401     /* range check */
  402     if (((first_md = amd64_mtrrfixsearch(sc, mrd->mr_base)) == NULL) ||
  403         ((last_md = amd64_mtrrfixsearch(sc, mrd->mr_base + mrd->mr_len - 1)) == NULL))
  404         return(EINVAL);
  405 
  406     /* check we aren't doing something risky */
  407     if (!(mrd->mr_flags & MDF_FORCE))
  408         for (curr_md = first_md; curr_md <= last_md; curr_md++) {
  409             if ((curr_md->mr_flags & MDF_ATTRMASK) == MDF_UNKNOWN)
  410                 return (EACCES);
  411         }
  412 
  413     /* set flags, clear set-by-firmware flag */
  414     for (curr_md = first_md; curr_md <= last_md; curr_md++) {
  415         curr_md->mr_flags = mrcopyflags(curr_md->mr_flags & ~MDF_FIRMWARE, mrd->mr_flags);
  416         bcopy(mrd->mr_owner, curr_md->mr_owner, sizeof(mrd->mr_owner));
  417     }
  418 
  419     return(0);
  420 }
  421 
  422 
  423 /*
  424  * Modify/add a variable MTRR to satisfy the request.
  425  *
  426  * XXX needs to be updated to properly support "busy" ranges.
  427  */
  428 static int
  429 amd64_mrsetvariable(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg)
  430 {
  431     struct mem_range_desc       *curr_md, *free_md;
  432     int                         i;
  433     
  434     /* 
  435      * Scan the currently active variable descriptors, look for 
  436      * one we exactly match (straight takeover) and for possible
  437      * accidental overlaps.
  438      * Keep track of the first empty variable descriptor in case we
  439      * can't perform a takeover.
  440      */
  441     i = (sc->mr_cap & MR686_FIXMTRR) ? MTRR_N64K + MTRR_N16K + MTRR_N4K : 0;
  442     curr_md = sc->mr_desc + i;
  443     free_md = NULL;
  444     for (; i < sc->mr_ndesc; i++, curr_md++) {
  445         if (curr_md->mr_flags & MDF_ACTIVE) {
  446             /* exact match? */
  447             if ((curr_md->mr_base == mrd->mr_base) &&
  448                 (curr_md->mr_len == mrd->mr_len)) {
  449                 /* whoops, owned by someone */
  450                 if (curr_md->mr_flags & MDF_BUSY)
  451                     return(EBUSY);
  452                 /* check we aren't doing something risky */
  453                 if (!(mrd->mr_flags & MDF_FORCE) &&
  454                   ((curr_md->mr_flags & MDF_ATTRMASK) == MDF_UNKNOWN))
  455                     return (EACCES);
  456                 /* Ok, just hijack this entry */
  457                 free_md = curr_md;
  458                 break;
  459             }
  460             /* non-exact overlap ? */
  461             if (mroverlap(curr_md, mrd)) {
  462                 /* between conflicting region types? */
  463                 if (amd64_mtrrconflict(curr_md->mr_flags, mrd->mr_flags))
  464                     return(EINVAL);
  465             }
  466         } else if (free_md == NULL) {
  467             free_md = curr_md;
  468         }
  469     }
  470     /* got somewhere to put it? */
  471     if (free_md == NULL)
  472         return(ENOSPC);
  473 
  474     /* Set up new descriptor */
  475     free_md->mr_base = mrd->mr_base;
  476     free_md->mr_len = mrd->mr_len;
  477     free_md->mr_flags = mrcopyflags(MDF_ACTIVE, mrd->mr_flags);
  478     bcopy(mrd->mr_owner, free_md->mr_owner, sizeof(mrd->mr_owner));
  479     return(0);
  480 }
  481 
  482 /*
  483  * Handle requests to set memory range attributes by manipulating MTRRs.
  484  *
  485  */
  486 static int
  487 amd64_mrset(struct mem_range_softc *sc, struct mem_range_desc *mrd, int *arg)
  488 {
  489     struct mem_range_desc       *targ;
  490     int                         error = 0;
  491 
  492     switch(*arg) {
  493     case MEMRANGE_SET_UPDATE:
  494         /* make sure that what's being asked for is even possible at all */
  495         if (!mrvalid(mrd->mr_base, mrd->mr_len) ||
  496             amd64_mtrrtype(mrd->mr_flags) == -1)
  497             return(EINVAL);
  498 
  499 #define FIXTOP  ((MTRR_N64K * 0x10000) + (MTRR_N16K * 0x4000) + (MTRR_N4K * 0x1000))
  500 
  501         /* are the "low memory" conditions applicable? */
  502         if ((sc->mr_cap & MR686_FIXMTRR) &&
  503             ((mrd->mr_base + mrd->mr_len) <= FIXTOP)) {
  504             if ((error = amd64_mrsetlow(sc, mrd, arg)) != 0)
  505                 return(error);
  506         } else {
  507             /* it's time to play with variable MTRRs */
  508             if ((error = amd64_mrsetvariable(sc, mrd, arg)) != 0)
  509                 return(error);
  510         }
  511         break;
  512 
  513     case MEMRANGE_SET_REMOVE:
  514         if ((targ = mem_range_match(sc, mrd)) == NULL)
  515             return(ENOENT);
  516         if (targ->mr_flags & MDF_FIXACTIVE)
  517             return(EPERM);
  518         if (targ->mr_flags & MDF_BUSY)
  519             return(EBUSY);
  520         targ->mr_flags &= ~MDF_ACTIVE;
  521         targ->mr_owner[0] = 0;
  522         break;
  523 
  524     default:
  525         return(EOPNOTSUPP);
  526     }
  527 
  528     /* update the hardware */
  529     amd64_mrstore(sc);
  530     amd64_mrfetch(sc);  /* refetch to see where we're at */
  531     return(0);
  532 }
  533 
  534 /*
  535  * Work out how many ranges we support, initialise storage for them, 
  536  * fetch the initial settings.
  537  */
  538 static void
  539 amd64_mrinit(struct mem_range_softc *sc)
  540 {
  541     struct mem_range_desc       *mrd;
  542     int                         nmdesc = 0;
  543     int                         i;
  544 
  545     mtrrcap = rdmsr(MSR_MTRRcap);
  546     mtrrdef = rdmsr(MSR_MTRRdefType);
  547 
  548     /* For now, bail out if MTRRs are not enabled */
  549     if (!(mtrrdef & 0x800)) {
  550         if (bootverbose)
  551             printf("CPU supports MTRRs but not enabled\n");
  552         return;
  553     }
  554     nmdesc = mtrrcap & 0xff;
  555 
  556     /* If fixed MTRRs supported and enabled */
  557     if ((mtrrcap & 0x100) && (mtrrdef & 0x400)) {
  558         sc->mr_cap = MR686_FIXMTRR;
  559         nmdesc += MTRR_N64K + MTRR_N16K + MTRR_N4K;
  560     }
  561 
  562     sc->mr_desc = 
  563         (struct mem_range_desc *)malloc(nmdesc * sizeof(struct mem_range_desc), 
  564                                         M_MEMDESC, M_WAITOK | M_ZERO);
  565     sc->mr_ndesc = nmdesc;
  566 
  567     mrd = sc->mr_desc;
  568 
  569     /* Populate the fixed MTRR entries' base/length */
  570     if (sc->mr_cap & MR686_FIXMTRR) {
  571         for (i = 0; i < MTRR_N64K; i++, mrd++) {
  572             mrd->mr_base = i * 0x10000;
  573             mrd->mr_len = 0x10000;
  574             mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN | MDF_FIXACTIVE;
  575         }
  576         for (i = 0; i < MTRR_N16K; i++, mrd++) {
  577             mrd->mr_base = i * 0x4000 + 0x80000;
  578             mrd->mr_len = 0x4000;
  579             mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN | MDF_FIXACTIVE;
  580         }
  581         for (i = 0; i < MTRR_N4K; i++, mrd++) {
  582             mrd->mr_base = i * 0x1000 + 0xc0000;
  583             mrd->mr_len = 0x1000;
  584             mrd->mr_flags = MDF_FIXBASE | MDF_FIXLEN | MDF_FIXACTIVE;
  585         }
  586     }
  587 
  588     /* 
  589      * Get current settings, anything set now is considered to have 
  590      * been set by the firmware. (XXX has something already played here?)
  591      */
  592     amd64_mrfetch(sc);
  593     mrd = sc->mr_desc;
  594     for (i = 0; i < sc->mr_ndesc; i++, mrd++) {
  595         if (mrd->mr_flags & MDF_ACTIVE)
  596             mrd->mr_flags |= MDF_FIRMWARE;
  597     }
  598 }
  599 
  600 /*
  601  * Initialise MTRRs on an AP after the BSP has run the init code.
  602  */
  603 static void
  604 amd64_mrAPinit(struct mem_range_softc *sc)
  605 {
  606     amd64_mrstoreone((void *)sc);       /* set MTRRs to match BSP */
  607     wrmsr(MSR_MTRRdefType, mtrrdef);    /* set MTRR behaviour to match BSP */
  608 }
  609 
  610 static void
  611 amd64_mem_drvinit(void *unused)
  612 {
  613         if (mtrrs_disabled)
  614                 return;
  615         if (!(cpu_feature & CPUID_MTRR))
  616                 return;
  617         if ((cpu_id & 0xf00) != 0x600 && (cpu_id & 0xf00) != 0xf00)
  618                 return;
  619         if ((strcmp(cpu_vendor, "GenuineIntel") != 0) &&
  620             (strcmp(cpu_vendor, "AuthenticAMD") != 0))
  621                 return;
  622         mem_range_softc.mr_op = &amd64_mrops;
  623 }
  624 
  625 SYSINIT(amd64memdev,SI_SUB_DRIVERS,SI_ORDER_FIRST,amd64_mem_drvinit,NULL)

Cache object: 33277e7e44d8c841ca7ef2f9d24db5d4


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