Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/apic_vector.S
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * Copyright (c) 1989, 1990 William F. Jolitz. 3 * Copyright (c) 1990 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: vector.s, 386BSD 0.1 unknown origin 31 * $FreeBSD: releng/8.1/sys/amd64/amd64/apic_vector.S 208294 2010-05-19 09:32:59Z kib $ 32 */ 33 34 /* 35 * Interrupt entry points for external interrupts triggered by I/O APICs 36 * as well as IPI handlers. 37 */ 38 39 #include <machine/asmacros.h> 40 #include <machine/apicreg.h> 41 42 #include "assym.s" 43 44 /* 45 * I/O Interrupt Entry Point. Rather than having one entry point for 46 * each interrupt source, we use one entry point for each 32-bit word 47 * in the ISR. The handler determines the highest bit set in the ISR, 48 * translates that into a vector, and passes the vector to the 49 * lapic_handle_intr() function. 50 */ 51 #define ISR_VEC(index, vec_name) \ 52 .text ; \ 53 SUPERALIGN_TEXT ; \ 54 IDTVEC(vec_name) ; \ 55 PUSH_FRAME ; \ 56 FAKE_MCOUNT(TF_RIP(%rsp)) ; \ 57 movq lapic, %rdx ; /* pointer to local APIC */ \ 58 movl LA_ISR + 16 * (index)(%rdx), %eax ; /* load ISR */ \ 59 bsrl %eax, %eax ; /* index of highset set bit in ISR */ \ 60 jz 2f ; \ 61 addl $(32 * index),%eax ; \ 62 1: ; \ 63 movq %rsp, %rsi ; \ 64 movl %eax, %edi ; /* pass the IRQ */ \ 65 call lapic_handle_intr ; \ 66 MEXITCOUNT ; \ 67 jmp doreti ; \ 68 2: movl $-1, %eax ; /* send a vector of -1 */ \ 69 jmp 1b 70 71 /* 72 * Handle "spurious INTerrupts". 73 * Notes: 74 * This is different than the "spurious INTerrupt" generated by an 75 * 8259 PIC for missing INTs. See the APIC documentation for details. 76 * This routine should NOT do an 'EOI' cycle. 77 */ 78 .text 79 SUPERALIGN_TEXT 80 IDTVEC(spuriousint) 81 82 /* No EOI cycle used here */ 83 84 jmp doreti_iret 85 86 ISR_VEC(1, apic_isr1) 87 ISR_VEC(2, apic_isr2) 88 ISR_VEC(3, apic_isr3) 89 ISR_VEC(4, apic_isr4) 90 ISR_VEC(5, apic_isr5) 91 ISR_VEC(6, apic_isr6) 92 ISR_VEC(7, apic_isr7) 93 94 /* 95 * Local APIC periodic timer handler. 96 */ 97 .text 98 SUPERALIGN_TEXT 99 IDTVEC(timerint) 100 PUSH_FRAME 101 FAKE_MCOUNT(TF_RIP(%rsp)) 102 movq %rsp, %rdi 103 call lapic_handle_timer 104 MEXITCOUNT 105 jmp doreti 106 107 /* 108 * Local APIC error interrupt handler. 109 */ 110 .text 111 SUPERALIGN_TEXT 112 IDTVEC(errorint) 113 PUSH_FRAME 114 FAKE_MCOUNT(TF_RIP(%rsp)) 115 call lapic_handle_error 116 MEXITCOUNT 117 jmp doreti 118 119 #ifdef SMP 120 /* 121 * Global address space TLB shootdown. 122 */ 123 .text 124 SUPERALIGN_TEXT 125 IDTVEC(invltlb) 126 pushq %rax 127 128 movq %cr3, %rax /* invalidate the TLB */ 129 movq %rax, %cr3 130 131 movq lapic, %rax 132 movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */ 133 134 lock 135 incl smp_tlb_wait 136 137 popq %rax 138 jmp doreti_iret 139 140 /* 141 * Single page TLB shootdown 142 */ 143 .text 144 SUPERALIGN_TEXT 145 IDTVEC(invlpg) 146 pushq %rax 147 148 movq smp_tlb_addr1, %rax 149 invlpg (%rax) /* invalidate single page */ 150 151 movq lapic, %rax 152 movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */ 153 154 lock 155 incl smp_tlb_wait 156 157 popq %rax 158 jmp doreti_iret 159 160 /* 161 * Page range TLB shootdown. 162 */ 163 .text 164 SUPERALIGN_TEXT 165 IDTVEC(invlrng) 166 pushq %rax 167 pushq %rdx 168 169 movq smp_tlb_addr1, %rdx 170 movq smp_tlb_addr2, %rax 171 1: invlpg (%rdx) /* invalidate single page */ 172 addq $PAGE_SIZE, %rdx 173 cmpq %rax, %rdx 174 jb 1b 175 176 movq lapic, %rax 177 movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */ 178 179 lock 180 incl smp_tlb_wait 181 182 popq %rdx 183 popq %rax 184 jmp doreti_iret 185 186 /* 187 * Invalidate cache. 188 */ 189 .text 190 SUPERALIGN_TEXT 191 IDTVEC(invlcache) 192 pushq %rax 193 194 wbinvd 195 196 movq lapic, %rax 197 movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */ 198 199 lock 200 incl smp_tlb_wait 201 202 popq %rax 203 jmp doreti_iret 204 205 /* 206 * Handler for IPIs sent via the per-cpu IPI bitmap. 207 */ 208 .text 209 SUPERALIGN_TEXT 210 IDTVEC(ipi_intr_bitmap_handler) 211 PUSH_FRAME 212 213 movq lapic, %rdx 214 movl $0, LA_EOI(%rdx) /* End Of Interrupt to APIC */ 215 216 FAKE_MCOUNT(TF_RIP(%rsp)) 217 218 call ipi_bitmap_handler 219 MEXITCOUNT 220 jmp doreti 221 222 /* 223 * Executed by a CPU when it receives an IPI_STOP from another CPU. 224 */ 225 .text 226 SUPERALIGN_TEXT 227 IDTVEC(cpustop) 228 PUSH_FRAME 229 230 movq lapic, %rax 231 movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */ 232 233 call cpustop_handler 234 jmp doreti 235 236 /* 237 * Executed by a CPU when it receives an IPI_SUSPEND from another CPU. 238 */ 239 .text 240 SUPERALIGN_TEXT 241 IDTVEC(cpususpend) 242 PUSH_FRAME 243 244 movq lapic, %rax 245 movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */ 246 247 call cpususpend_handler 248 249 POP_FRAME 250 jmp doreti_iret 251 252 /* 253 * Executed by a CPU when it receives a RENDEZVOUS IPI from another CPU. 254 * 255 * - Calls the generic rendezvous action function. 256 */ 257 .text 258 SUPERALIGN_TEXT 259 IDTVEC(rendezvous) 260 PUSH_FRAME 261 call smp_rendezvous_action 262 movq lapic, %rax 263 movl $0, LA_EOI(%rax) /* End Of Interrupt to APIC */ 264 jmp doreti 265 #endif /* SMP */
Cache object: 1d41f3d1f1b25dfe35fa57616584fb93
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]