The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/bpf_jit_machdep.h

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    1 /*-
    2  * Copyright (C) 2002-2003 NetGroup, Politecnico di Torino (Italy)
    3  * Copyright (C) 2005-2008 Jung-uk Kim <jkim@FreeBSD.org>
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  *
   10  * 1. Redistributions of source code must retain the above copyright
   11  * notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  * notice, this list of conditions and the following disclaimer in the
   14  * documentation and/or other materials provided with the distribution.
   15  * 3. Neither the name of the Politecnico di Torino nor the names of its
   16  * contributors may be used to endorse or promote products derived from
   17  * this software without specific prior written permission.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
   20  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
   21  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
   22  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
   23  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
   24  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
   25  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
   29  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   30  *
   31  * $FreeBSD: releng/8.2/sys/amd64/amd64/bpf_jit_machdep.h 182173 2008-08-25 20:43:13Z jkim $
   32  */
   33 
   34 #ifndef _BPF_JIT_MACHDEP_H_
   35 #define _BPF_JIT_MACHDEP_H_
   36 
   37 /*
   38  * Registers
   39  */
   40 #define RAX     0
   41 #define RCX     1
   42 #define RDX     2
   43 #define RBX     3
   44 #define RSP     4
   45 #define RBP     5
   46 #define RSI     6
   47 #define RDI     7
   48 #define R8      0
   49 #define R9      1
   50 #define R10     2
   51 #define R11     3
   52 #define R12     4
   53 #define R13     5
   54 #define R14     6
   55 #define R15     7
   56 
   57 #define EAX     0
   58 #define ECX     1
   59 #define EDX     2
   60 #define EBX     3
   61 #define ESP     4
   62 #define EBP     5
   63 #define ESI     6
   64 #define EDI     7
   65 #define R8D     0
   66 #define R9D     1
   67 #define R10D    2
   68 #define R11D    3
   69 #define R12D    4
   70 #define R13D    5
   71 #define R14D    6
   72 #define R15D    7
   73 
   74 #define AX      0
   75 #define CX      1
   76 #define DX      2
   77 #define BX      3
   78 #define SP      4
   79 #define BP      5
   80 #define SI      6
   81 #define DI      7
   82 
   83 #define AL      0
   84 #define CL      1
   85 #define DL      2
   86 #define BL      3
   87 
   88 /* A stream of native binary code.*/
   89 typedef struct bpf_bin_stream {
   90         /* Current native instruction pointer. */
   91         int             cur_ip;
   92 
   93         /*
   94          * Current BPF instruction pointer, i.e. position in
   95          * the BPF program reached by the jitter.
   96          */
   97         int             bpf_pc;
   98 
   99         /* Instruction buffer, contains the generated native code. */
  100         char            *ibuf;
  101 
  102         /* Jumps reference table. */
  103         u_int           *refs;
  104 } bpf_bin_stream;
  105 
  106 /*
  107  * Prototype of the emit functions.
  108  *
  109  * Different emit functions are used to create the reference table and
  110  * to generate the actual filtering code. This allows to have simpler
  111  * instruction macros.
  112  * The first parameter is the stream that will receive the data.
  113  * The second one is a variable containing the data.
  114  * The third one is the length, that can be 1, 2, or 4 since it is possible
  115  * to emit a byte, a short, or a word at a time.
  116  */
  117 typedef void (*emit_func)(bpf_bin_stream *stream, u_int value, u_int n);
  118 
  119 /*
  120  * native Instruction Macros
  121  */
  122 
  123 /* movl i32,r32 */
  124 #define MOVid(i32, r32) do {                                            \
  125         emitm(&stream, (11 << 4) | (1 << 3) | (r32 & 0x7), 1);          \
  126         emitm(&stream, i32, 4);                                         \
  127 } while (0)
  128 
  129 /* movq i64,r64 */
  130 #define MOViq(i64, r64) do {                                            \
  131         emitm(&stream, 0x48, 1);                                        \
  132         emitm(&stream, (11 << 4) | (1 << 3) | (r64 & 0x7), 1);          \
  133         emitm(&stream, i64, 4);                                         \
  134         emitm(&stream, (i64 >> 32), 4);                                 \
  135 } while (0)
  136 
  137 /* movl sr32,dr32 */
  138 #define MOVrd(sr32, dr32) do {                                          \
  139         emitm(&stream, 0x89, 1);                                        \
  140         emitm(&stream,                                                  \
  141             (3 << 6) | ((sr32 & 0x7) << 3) | (dr32 & 0x7), 1);          \
  142 } while (0)
  143 
  144 /* movl sr32,dr32 (dr32 = %r8-15d) */
  145 #define MOVrd2(sr32, dr32) do {                                         \
  146         emitm(&stream, 0x8941, 2);                                      \
  147         emitm(&stream,                                                  \
  148             (3 << 6) | ((sr32 & 0x7) << 3) | (dr32 & 0x7), 1);          \
  149 } while (0)
  150 
  151 /* movl sr32,dr32 (sr32 = %r8-15d) */
  152 #define MOVrd3(sr32, dr32) do {                                         \
  153         emitm(&stream, 0x8944, 2);                                      \
  154         emitm(&stream,                                                  \
  155             (3 << 6) | ((sr32 & 0x7) << 3) | (dr32 & 0x7), 1);          \
  156 } while (0)
  157 
  158 /* movq sr64,dr64 */
  159 #define MOVrq(sr64, dr64) do {                                          \
  160         emitm(&stream, 0x8948, 2);                                      \
  161         emitm(&stream,                                                  \
  162             (3 << 6) | ((sr64 & 0x7) << 3) | (dr64 & 0x7), 1);          \
  163 } while (0)
  164 
  165 /* movq sr64,dr64 (dr64 = %r8-15) */
  166 #define MOVrq2(sr64, dr64) do {                                         \
  167         emitm(&stream, 0x8949, 2);                                      \
  168         emitm(&stream,                                                  \
  169             (3 << 6) | ((sr64 & 0x7) << 3) | (dr64 & 0x7), 1);          \
  170 } while (0)
  171 
  172 /* movq sr64,dr64 (sr64 = %r8-15) */
  173 #define MOVrq3(sr64, dr64) do {                                         \
  174         emitm(&stream, 0x894c, 2);                                      \
  175         emitm(&stream,                                                  \
  176             (3 << 6) | ((sr64 & 0x7) << 3) | (dr64 & 0x7), 1);          \
  177 } while (0)
  178 
  179 /* movl (sr64,or64,1),dr32 */
  180 #define MOVobd(sr64, or64, dr32) do {                                   \
  181         emitm(&stream, 0x8b, 1);                                        \
  182         emitm(&stream, ((dr32 & 0x7) << 3) | 4, 1);                     \
  183         emitm(&stream, ((or64 & 0x7) << 3) | (sr64 & 0x7), 1);          \
  184 } while (0)
  185 
  186 /* movw (sr64,or64,1),dr16 */
  187 #define MOVobw(sr64, or64, dr16) do {                                   \
  188         emitm(&stream, 0x8b66, 2);                                      \
  189         emitm(&stream, ((dr16 & 0x7) << 3) | 4, 1);                     \
  190         emitm(&stream, ((or64 & 0x7) << 3) | (sr64 & 0x7), 1);          \
  191 } while (0)
  192 
  193 /* movb (sr64,or64,1),dr8 */
  194 #define MOVobb(sr64, or64, dr8) do {                                    \
  195         emitm(&stream, 0x8a, 1);                                        \
  196         emitm(&stream, ((dr8 & 0x7) << 3) | 4, 1);                      \
  197         emitm(&stream, ((or64 & 0x7) << 3) | (sr64 & 0x7), 1);          \
  198 } while (0)
  199 
  200 /* movl sr32,(dr64,or64,1) */
  201 #define MOVomd(sr32, dr64, or64) do {                                   \
  202         emitm(&stream, 0x89, 1);                                        \
  203         emitm(&stream, ((sr32 & 0x7) << 3) | 4, 1);                     \
  204         emitm(&stream, ((or64 & 0x7) << 3) | (dr64 & 0x7), 1);          \
  205 } while (0)
  206 
  207 /* bswapl dr32 */
  208 #define BSWAP(dr32) do {                                                \
  209         emitm(&stream, 0xf, 1);                                         \
  210         emitm(&stream, (0x19 << 3) | dr32, 1);                          \
  211 } while (0)
  212 
  213 /* xchgb %al,%ah */
  214 #define SWAP_AX() do {                                                  \
  215         emitm(&stream, 0xc486, 2);                                      \
  216 } while (0)
  217 
  218 /* ret */
  219 #define RET() do {                                              \
  220         emitm(&stream, 0xc3, 1);                                        \
  221 } while (0)
  222 
  223 /* addl sr32,dr32 */
  224 #define ADDrd(sr32, dr32) do {                                          \
  225         emitm(&stream, 0x01, 1);                                        \
  226         emitm(&stream,                                                  \
  227             (3 << 6) | ((sr32 & 0x7) << 3) | (dr32 & 0x7), 1);          \
  228 } while (0)
  229 
  230 /* addl i32,%eax */
  231 #define ADD_EAXi(i32) do {                                              \
  232         emitm(&stream, 0x05, 1);                                        \
  233         emitm(&stream, i32, 4);                                         \
  234 } while (0)
  235 
  236 /* addl i8,r32 */
  237 #define ADDib(i8, r32) do {                                             \
  238         emitm(&stream, 0x83, 1);                                        \
  239         emitm(&stream, (24 << 3) | r32, 1);                             \
  240         emitm(&stream, i8, 1);                                          \
  241 } while (0)
  242 
  243 /* subl sr32,dr32 */
  244 #define SUBrd(sr32, dr32) do {                                          \
  245         emitm(&stream, 0x29, 1);                                        \
  246         emitm(&stream,                                                  \
  247             (3 << 6) | ((sr32 & 0x7) << 3) | (dr32 & 0x7), 1);          \
  248 } while (0)
  249 
  250 /* subl i32,%eax */
  251 #define SUB_EAXi(i32) do {                                              \
  252         emitm(&stream, 0x2d, 1);                                        \
  253         emitm(&stream, i32, 4);                                         \
  254 } while (0)
  255 
  256 /* mull r32 */
  257 #define MULrd(r32) do {                                                 \
  258         emitm(&stream, 0xf7, 1);                                        \
  259         emitm(&stream, (7 << 5) | (r32 & 0x7), 1);                      \
  260 } while (0)
  261 
  262 /* divl r32 */
  263 #define DIVrd(r32) do {                                                 \
  264         emitm(&stream, 0xf7, 1);                                        \
  265         emitm(&stream, (15 << 4) | (r32 & 0x7), 1);                     \
  266 } while (0)
  267 
  268 /* andb i8,r8 */
  269 #define ANDib(i8, r8) do {                                              \
  270         if (r8 == AL) {                                                 \
  271                 emitm(&stream, 0x24, 1);                                \
  272         } else {                                                        \
  273                 emitm(&stream, 0x80, 1);                                \
  274                 emitm(&stream, (7 << 5) | r8, 1);                       \
  275         }                                                               \
  276         emitm(&stream, i8, 1);                                          \
  277 } while (0)
  278 
  279 /* andl i32,r32 */
  280 #define ANDid(i32, r32) do {                                            \
  281         if (r32 == EAX) {                                               \
  282                 emitm(&stream, 0x25, 1);                                \
  283         } else {                                                        \
  284                 emitm(&stream, 0x81, 1);                                \
  285                 emitm(&stream, (7 << 5) | r32, 1);                      \
  286         }                                                               \
  287         emitm(&stream, i32, 4);                                         \
  288 } while (0)
  289 
  290 /* andl sr32,dr32 */
  291 #define ANDrd(sr32, dr32) do {                                          \
  292         emitm(&stream, 0x21, 1);                                        \
  293         emitm(&stream,                                                  \
  294             (3 << 6) | ((sr32 & 0x7) << 3) | (dr32 & 0x7), 1);          \
  295 } while (0)
  296 
  297 /* testl i32,r32 */
  298 #define TESTid(i32, r32) do {                                           \
  299         if (r32 == EAX) {                                               \
  300                 emitm(&stream, 0xa9, 1);                                \
  301         } else {                                                        \
  302                 emitm(&stream, 0xf7, 1);                                \
  303                 emitm(&stream, (3 << 6) | r32, 1);                      \
  304         }                                                               \
  305         emitm(&stream, i32, 4);                                         \
  306 } while (0)
  307 
  308 /* testl sr32,dr32 */
  309 #define TESTrd(sr32, dr32) do {                                         \
  310         emitm(&stream, 0x85, 1);                                        \
  311         emitm(&stream,                                                  \
  312             (3 << 6) | ((sr32 & 0x7) << 3) | (dr32 & 0x7), 1);          \
  313 } while (0)
  314 
  315 /* orl sr32,dr32 */
  316 #define ORrd(sr32, dr32) do {                                           \
  317         emitm(&stream, 0x09, 1);                                        \
  318         emitm(&stream,                                                  \
  319             (3 << 6) | ((sr32 & 0x7) << 3) | (dr32 & 0x7), 1);          \
  320 } while (0)
  321 
  322 /* orl i32,r32 */
  323 #define ORid(i32, r32) do {                                             \
  324         if (r32 == EAX) {                                               \
  325                 emitm(&stream, 0x0d, 1);                                \
  326         } else {                                                        \
  327                 emitm(&stream, 0x81, 1);                                \
  328                 emitm(&stream, (25 << 3) | r32, 1);                     \
  329         }                                                               \
  330         emitm(&stream, i32, 4);                                         \
  331 } while (0)
  332 
  333 /* shll i8,r32 */
  334 #define SHLib(i8, r32) do {                                             \
  335         emitm(&stream, 0xc1, 1);                                        \
  336         emitm(&stream, (7 << 5) | (r32 & 0x7), 1);                      \
  337         emitm(&stream, i8, 1);                                          \
  338 } while (0)
  339 
  340 /* shll %cl,dr32 */
  341 #define SHL_CLrb(dr32) do {                                             \
  342         emitm(&stream, 0xd3, 1);                                        \
  343         emitm(&stream, (7 << 5) | (dr32 & 0x7), 1);                     \
  344 } while (0)
  345 
  346 /* shrl i8,r32 */
  347 #define SHRib(i8, r32) do {                                             \
  348         emitm(&stream, 0xc1, 1);                                        \
  349         emitm(&stream, (29 << 3) | (r32 & 0x7), 1);                     \
  350         emitm(&stream, i8, 1);                                          \
  351 } while (0)
  352 
  353 /* shrl %cl,dr32 */
  354 #define SHR_CLrb(dr32) do {                                             \
  355         emitm(&stream, 0xd3, 1);                                        \
  356         emitm(&stream, (29 << 3) | (dr32 & 0x7), 1);                    \
  357 } while (0)
  358 
  359 /* negl r32 */
  360 #define NEGd(r32) do {                                                  \
  361         emitm(&stream, 0xf7, 1);                                        \
  362         emitm(&stream, (27 << 3) | (r32 & 0x7), 1);                     \
  363 } while (0)
  364 
  365 /* cmpl sr32,dr32 */
  366 #define CMPrd(sr32, dr32) do {                                          \
  367         emitm(&stream, 0x39, 1);                                        \
  368         emitm(&stream,                                                  \
  369             (3 << 6) | ((sr32 & 0x7) << 3) | (dr32 & 0x7), 1);          \
  370 } while (0)
  371 
  372 /* cmpl i32,dr32 */
  373 #define CMPid(i32, dr32) do {                                           \
  374         if (dr32 == EAX){                                               \
  375                 emitm(&stream, 0x3d, 1);                                \
  376                 emitm(&stream, i32, 4);                                 \
  377         } else {                                                        \
  378                 emitm(&stream, 0x81, 1);                                \
  379                 emitm(&stream, (0x1f << 3) | (dr32 & 0x7), 1);          \
  380                 emitm(&stream, i32, 4);                                 \
  381         }                                                               \
  382 } while (0)
  383 
  384 /* jb off8 */
  385 #define JBb(off8) do {                                                  \
  386         emitm(&stream, 0x72, 1);                                        \
  387         emitm(&stream, off8, 1);                                        \
  388 } while (0)
  389 
  390 /* jae off8 */
  391 #define JAEb(off8) do {                                                 \
  392         emitm(&stream, 0x73, 1);                                        \
  393         emitm(&stream, off8, 1);                                        \
  394 } while (0)
  395 
  396 /* jne off8 */
  397 #define JNEb(off8) do {                                                 \
  398         emitm(&stream, 0x75, 1);                                        \
  399         emitm(&stream, off8, 1);                                        \
  400 } while (0)
  401 
  402 /* ja off8 */
  403 #define JAb(off8) do {                                                  \
  404         emitm(&stream, 0x77, 1);                                        \
  405         emitm(&stream, off8, 1);                                        \
  406 } while (0)
  407 
  408 /* jmp off32 */
  409 #define JMP(off32) do {                                                 \
  410         emitm(&stream, 0xe9, 1);                                        \
  411         emitm(&stream, off32, 4);                                       \
  412 } while (0)
  413 
  414 /* xorl r32,r32 */
  415 #define ZEROrd(r32) do {                                                \
  416         emitm(&stream, 0x31, 1);                                        \
  417         emitm(&stream, (3 << 6) | ((r32 & 0x7) << 3) | (r32 & 0x7), 1); \
  418 } while (0)
  419 
  420 /*
  421  * Conditional long jumps
  422  */
  423 #define JB      0x82
  424 #define JAE     0x83
  425 #define JE      0x84
  426 #define JNE     0x85
  427 #define JBE     0x86
  428 #define JA      0x87
  429 
  430 #define JCC(t, f) do {                                                  \
  431         if (ins->jt != 0 && ins->jf != 0) {                             \
  432                 /* 5 is the size of the following jmp */                \
  433                 emitm(&stream, ((t) << 8) | 0x0f, 2);                   \
  434                 emitm(&stream, stream.refs[stream.bpf_pc + ins->jt] -   \
  435                     stream.refs[stream.bpf_pc] + 5, 4);                 \
  436                 JMP(stream.refs[stream.bpf_pc + ins->jf] -              \
  437                     stream.refs[stream.bpf_pc]);                        \
  438         } else if (ins->jt != 0) {                                      \
  439                 emitm(&stream, ((t) << 8) | 0x0f, 2);                   \
  440                 emitm(&stream, stream.refs[stream.bpf_pc + ins->jt] -   \
  441                     stream.refs[stream.bpf_pc], 4);                     \
  442         } else {                                                        \
  443                 emitm(&stream, ((f) << 8) | 0x0f, 2);                   \
  444                 emitm(&stream, stream.refs[stream.bpf_pc + ins->jf] -   \
  445                     stream.refs[stream.bpf_pc], 4);                     \
  446         }                                                               \
  447 } while (0)
  448 
  449 #endif  /* _BPF_JIT_MACHDEP_H_ */

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