Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/amd64/amd64/cpu_switch.S
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1 /*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1990 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * William Jolitz. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 36 #include <machine/asmacros.h> 37 #include <machine/specialreg.h> 38 39 #include "assym.s" 40 #include "opt_sched.h" 41 42 /*****************************************************************************/ 43 /* Scheduling */ 44 /*****************************************************************************/ 45 46 .text 47 48 #ifdef SMP 49 #define LK lock ; 50 #else 51 #define LK 52 #endif 53 54 #if defined(SCHED_ULE) && defined(SMP) 55 #define SETLK xchgq 56 #else 57 #define SETLK movq 58 #endif 59 60 /* 61 * cpu_throw() 62 * 63 * This is the second half of cpu_switch(). It is used when the current 64 * thread is either a dummy or slated to die, and we no longer care 65 * about its state. This is only a slight optimization and is probably 66 * not worth it anymore. Note that we need to clear the pm_active bits so 67 * we do need the old proc if it still exists. 68 * %rdi = oldtd 69 * %rsi = newtd 70 */ 71 ENTRY(cpu_throw) 72 movl PCPU(CPUID),%eax 73 testq %rdi,%rdi 74 jz 1f 75 /* release bit from old pm_active */ 76 movq PCPU(CURPMAP),%rdx 77 LK btrl %eax,PM_ACTIVE(%rdx) /* clear old */ 78 1: 79 movq TD_PCB(%rsi),%r8 /* newtd->td_proc */ 80 movq PCB_CR3(%r8),%rdx 81 movq %rdx,%cr3 /* new address space */ 82 jmp swact 83 END(cpu_throw) 84 85 /* 86 * cpu_switch(old, new, mtx) 87 * 88 * Save the current thread state, then select the next thread to run 89 * and load its state. 90 * %rdi = oldtd 91 * %rsi = newtd 92 * %rdx = mtx 93 */ 94 ENTRY(cpu_switch) 95 /* Switch to new thread. First, save context. */ 96 movq TD_PCB(%rdi),%r8 97 orl $PCB_FULL_IRET,PCB_FLAGS(%r8) 98 99 movq (%rsp),%rax /* Hardware registers */ 100 movq %r15,PCB_R15(%r8) 101 movq %r14,PCB_R14(%r8) 102 movq %r13,PCB_R13(%r8) 103 movq %r12,PCB_R12(%r8) 104 movq %rbp,PCB_RBP(%r8) 105 movq %rsp,PCB_RSP(%r8) 106 movq %rbx,PCB_RBX(%r8) 107 movq %rax,PCB_RIP(%r8) 108 109 testl $PCB_DBREGS,PCB_FLAGS(%r8) 110 jnz store_dr /* static predict not taken */ 111 done_store_dr: 112 113 /* have we used fp, and need a save? */ 114 cmpq %rdi,PCPU(FPCURTHREAD) 115 jne 3f 116 movq PCB_SAVEFPU(%r8),%r8 117 clts 118 cmpl $0,use_xsave 119 jne 1f 120 fxsave (%r8) 121 jmp 2f 122 1: movq %rdx,%rcx 123 movl xsave_mask,%eax 124 movl xsave_mask+4,%edx 125 .globl ctx_switch_xsave 126 ctx_switch_xsave: 127 /* This is patched to xsaveopt if supported, see fpuinit_bsp1() */ 128 xsave (%r8) 129 movq %rcx,%rdx 130 2: smsw %ax 131 orb $CR0_TS,%al 132 lmsw %ax 133 xorl %eax,%eax 134 movq %rax,PCPU(FPCURTHREAD) 135 3: 136 137 /* Save is done. Now fire up new thread. Leave old vmspace. */ 138 movq TD_PCB(%rsi),%r8 139 140 /* switch address space */ 141 movq PCB_CR3(%r8),%rcx 142 movq %cr3,%rax 143 cmpq %rcx,%rax /* Same address space? */ 144 jne swinact 145 SETLK %rdx, TD_LOCK(%rdi) /* Release the old thread */ 146 jmp sw1 147 swinact: 148 movq %rcx,%cr3 /* new address space */ 149 movl PCPU(CPUID), %eax 150 /* Release bit from old pmap->pm_active */ 151 movq PCPU(CURPMAP),%rcx 152 LK btrl %eax,PM_ACTIVE(%rcx) /* clear old */ 153 SETLK %rdx, TD_LOCK(%rdi) /* Release the old thread */ 154 swact: 155 /* Set bit in new pmap->pm_active */ 156 movq TD_PROC(%rsi),%rdx /* newproc */ 157 movq P_VMSPACE(%rdx), %rdx 158 addq $VM_PMAP,%rdx 159 LK btsl %eax,PM_ACTIVE(%rdx) /* set new */ 160 movq %rdx,PCPU(CURPMAP) 161 162 sw1: 163 #if defined(SCHED_ULE) && defined(SMP) 164 /* Wait for the new thread to become unblocked */ 165 movq $blocked_lock, %rdx 166 1: 167 movq TD_LOCK(%rsi),%rcx 168 cmpq %rcx, %rdx 169 pause 170 je 1b 171 #endif 172 /* 173 * At this point, we've switched address spaces and are ready 174 * to load up the rest of the next context. 175 */ 176 177 /* Skip loading user fsbase/gsbase for kthreads */ 178 testl $TDP_KTHREAD,TD_PFLAGS(%rsi) 179 jnz do_kthread 180 181 /* 182 * Load ldt register 183 */ 184 movq TD_PROC(%rsi),%rcx 185 cmpq $0, P_MD+MD_LDT(%rcx) 186 jne do_ldt 187 xorl %eax,%eax 188 ld_ldt: lldt %ax 189 190 /* Restore fs base in GDT */ 191 movl PCB_FSBASE(%r8),%eax 192 movq PCPU(FS32P),%rdx 193 movw %ax,2(%rdx) 194 shrl $16,%eax 195 movb %al,4(%rdx) 196 shrl $8,%eax 197 movb %al,7(%rdx) 198 199 /* Restore gs base in GDT */ 200 movl PCB_GSBASE(%r8),%eax 201 movq PCPU(GS32P),%rdx 202 movw %ax,2(%rdx) 203 shrl $16,%eax 204 movb %al,4(%rdx) 205 shrl $8,%eax 206 movb %al,7(%rdx) 207 208 do_kthread: 209 /* Do we need to reload tss ? */ 210 movq PCPU(TSSP),%rax 211 movq PCB_TSSP(%r8),%rdx 212 testq %rdx,%rdx 213 cmovzq PCPU(COMMONTSSP),%rdx 214 cmpq %rax,%rdx 215 jne do_tss 216 done_tss: 217 movq %r8,PCPU(RSP0) 218 movq %r8,PCPU(CURPCB) 219 /* Update the TSS_RSP0 pointer for the next interrupt */ 220 movq %r8,COMMON_TSS_RSP0(%rdx) 221 movq %rsi,PCPU(CURTHREAD) /* into next thread */ 222 223 /* Test if debug registers should be restored. */ 224 testl $PCB_DBREGS,PCB_FLAGS(%r8) 225 jnz load_dr /* static predict not taken */ 226 done_load_dr: 227 228 /* Restore context. */ 229 movq PCB_R15(%r8),%r15 230 movq PCB_R14(%r8),%r14 231 movq PCB_R13(%r8),%r13 232 movq PCB_R12(%r8),%r12 233 movq PCB_RBP(%r8),%rbp 234 movq PCB_RSP(%r8),%rsp 235 movq PCB_RBX(%r8),%rbx 236 movq PCB_RIP(%r8),%rax 237 movq %rax,(%rsp) 238 ret 239 240 /* 241 * We order these strangely for several reasons. 242 * 1: I wanted to use static branch prediction hints 243 * 2: Most athlon64/opteron cpus don't have them. They define 244 * a forward branch as 'predict not taken'. Intel cores have 245 * the 'rep' prefix to invert this. 246 * So, to make it work on both forms of cpu we do the detour. 247 * We use jumps rather than call in order to avoid the stack. 248 */ 249 250 store_dr: 251 movq %dr7,%rax /* yes, do the save */ 252 movq %dr0,%r15 253 movq %dr1,%r14 254 movq %dr2,%r13 255 movq %dr3,%r12 256 movq %dr6,%r11 257 movq %r15,PCB_DR0(%r8) 258 movq %r14,PCB_DR1(%r8) 259 movq %r13,PCB_DR2(%r8) 260 movq %r12,PCB_DR3(%r8) 261 movq %r11,PCB_DR6(%r8) 262 movq %rax,PCB_DR7(%r8) 263 andq $0x0000fc00, %rax /* disable all watchpoints */ 264 movq %rax,%dr7 265 jmp done_store_dr 266 267 load_dr: 268 movq %dr7,%rax 269 movq PCB_DR0(%r8),%r15 270 movq PCB_DR1(%r8),%r14 271 movq PCB_DR2(%r8),%r13 272 movq PCB_DR3(%r8),%r12 273 movq PCB_DR6(%r8),%r11 274 movq PCB_DR7(%r8),%rcx 275 movq %r15,%dr0 276 movq %r14,%dr1 277 /* Preserve reserved bits in %dr7 */ 278 andq $0x0000fc00,%rax 279 andq $~0x0000fc00,%rcx 280 movq %r13,%dr2 281 movq %r12,%dr3 282 orq %rcx,%rax 283 movq %r11,%dr6 284 movq %rax,%dr7 285 jmp done_load_dr 286 287 do_tss: movq %rdx,PCPU(TSSP) 288 movq %rdx,%rcx 289 movq PCPU(TSS),%rax 290 movw %cx,2(%rax) 291 shrq $16,%rcx 292 movb %cl,4(%rax) 293 shrq $8,%rcx 294 movb %cl,7(%rax) 295 shrq $8,%rcx 296 movl %ecx,8(%rax) 297 movb $0x89,5(%rax) /* unset busy */ 298 movl $TSSSEL,%eax 299 ltr %ax 300 jmp done_tss 301 302 do_ldt: movq PCPU(LDT),%rax 303 movq P_MD+MD_LDT_SD(%rcx),%rdx 304 movq %rdx,(%rax) 305 movq P_MD+MD_LDT_SD+8(%rcx),%rdx 306 movq %rdx,8(%rax) 307 movl $LDTSEL,%eax 308 jmp ld_ldt 309 END(cpu_switch) 310 311 /* 312 * savectx(pcb) 313 * Update pcb, saving current processor state. 314 */ 315 ENTRY(savectx) 316 /* Save caller's return address. */ 317 movq (%rsp),%rax 318 movq %rax,PCB_RIP(%rdi) 319 320 movq %rbx,PCB_RBX(%rdi) 321 movq %rsp,PCB_RSP(%rdi) 322 movq %rbp,PCB_RBP(%rdi) 323 movq %r12,PCB_R12(%rdi) 324 movq %r13,PCB_R13(%rdi) 325 movq %r14,PCB_R14(%rdi) 326 movq %r15,PCB_R15(%rdi) 327 328 movq %cr0,%rax 329 movq %rax,PCB_CR0(%rdi) 330 movq %cr2,%rax 331 movq %rax,PCB_CR2(%rdi) 332 movq %cr3,%rax 333 movq %rax,PCB_CR3(%rdi) 334 movq %cr4,%rax 335 movq %rax,PCB_CR4(%rdi) 336 337 movq %dr0,%rax 338 movq %rax,PCB_DR0(%rdi) 339 movq %dr1,%rax 340 movq %rax,PCB_DR1(%rdi) 341 movq %dr2,%rax 342 movq %rax,PCB_DR2(%rdi) 343 movq %dr3,%rax 344 movq %rax,PCB_DR3(%rdi) 345 movq %dr6,%rax 346 movq %rax,PCB_DR6(%rdi) 347 movq %dr7,%rax 348 movq %rax,PCB_DR7(%rdi) 349 350 movl $MSR_FSBASE,%ecx 351 rdmsr 352 movl %eax,PCB_FSBASE(%rdi) 353 movl %edx,PCB_FSBASE+4(%rdi) 354 movl $MSR_GSBASE,%ecx 355 rdmsr 356 movl %eax,PCB_GSBASE(%rdi) 357 movl %edx,PCB_GSBASE+4(%rdi) 358 movl $MSR_KGSBASE,%ecx 359 rdmsr 360 movl %eax,PCB_KGSBASE(%rdi) 361 movl %edx,PCB_KGSBASE+4(%rdi) 362 363 sgdt PCB_GDT(%rdi) 364 sidt PCB_IDT(%rdi) 365 sldt PCB_LDT(%rdi) 366 str PCB_TR(%rdi) 367 368 movl $1,%eax 369 ret 370 END(savectx)
Cache object: 14936f63679bb059e842486ab0dd3b3b
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