Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/exception.S
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1 /*- 2 * Copyright (c) 1989, 1990 William F. Jolitz. 3 * Copyright (c) 1990 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 4. Neither the name of the University nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: releng/6.1/sys/amd64/amd64/exception.S 158179 2006-04-30 16:44:43Z cvs2svn $ 31 */ 32 33 #include "opt_atpic.h" 34 #include "opt_compat.h" 35 36 #include <machine/asmacros.h> 37 #include <machine/psl.h> 38 #include <machine/trap.h> 39 40 #include "assym.s" 41 42 .text 43 44 /*****************************************************************************/ 45 /* Trap handling */ 46 /*****************************************************************************/ 47 /* 48 * Trap and fault vector routines. 49 * 50 * All traps are 'interrupt gates', SDT_SYSIGT. An interrupt gate pushes 51 * state on the stack but also disables interrupts. This is important for 52 * us for the use of the swapgs instruction. We cannot be interrupted 53 * until the GS.base value is correct. For most traps, we automatically 54 * then enable interrupts if the interrupted context had them enabled. 55 * This is equivalent to the i386 port's use of SDT_SYS386TGT. 56 * 57 * The cpu will push a certain amount of state onto the kernel stack for 58 * the current process. See amd64/include/frame.h. 59 * This includes the current RFLAGS (status register, which includes 60 * the interrupt disable state prior to the trap), the code segment register, 61 * and the return instruction pointer are pushed by the cpu. The cpu 62 * will also push an 'error' code for certain traps. We push a dummy 63 * error code for those traps where the cpu doesn't in order to maintain 64 * a consistent frame. We also push a contrived 'trap number'. 65 * 66 * The cpu does not push the general registers, we must do that, and we 67 * must restore them prior to calling 'iret'. The cpu adjusts the %cs and 68 * %ss segment registers, but does not mess with %ds, %es, or %fs. Thus we 69 * must load them with appropriate values for supervisor mode operation. 70 */ 71 72 MCOUNT_LABEL(user) 73 MCOUNT_LABEL(btrap) 74 75 /* Traps that we leave interrupts disabled for.. */ 76 #define TRAP_NOEN(a) \ 77 subq $TF_RIP,%rsp; \ 78 movq $(a),TF_TRAPNO(%rsp) ; \ 79 movq $0,TF_ADDR(%rsp) ; \ 80 movq $0,TF_ERR(%rsp) ; \ 81 jmp alltraps_noen 82 IDTVEC(dbg) 83 TRAP_NOEN(T_TRCTRAP) 84 IDTVEC(bpt) 85 TRAP_NOEN(T_BPTFLT) 86 87 /* Regular traps; The cpu does not supply tf_err for these. */ 88 #define TRAP(a) \ 89 subq $TF_RIP,%rsp; \ 90 movq $(a),TF_TRAPNO(%rsp) ; \ 91 movq $0,TF_ADDR(%rsp) ; \ 92 movq $0,TF_ERR(%rsp) ; \ 93 jmp alltraps 94 IDTVEC(div) 95 TRAP(T_DIVIDE) 96 IDTVEC(ofl) 97 TRAP(T_OFLOW) 98 IDTVEC(bnd) 99 TRAP(T_BOUND) 100 IDTVEC(ill) 101 TRAP(T_PRIVINFLT) 102 IDTVEC(dna) 103 TRAP(T_DNA) 104 IDTVEC(fpusegm) 105 TRAP(T_FPOPFLT) 106 IDTVEC(mchk) 107 TRAP(T_MCHK) 108 IDTVEC(rsvd) 109 TRAP(T_RESERVED) 110 IDTVEC(fpu) 111 TRAP(T_ARITHTRAP) 112 IDTVEC(xmm) 113 TRAP(T_XMMFLT) 114 115 /* This group of traps have tf_err already pushed by the cpu */ 116 #define TRAP_ERR(a) \ 117 subq $TF_ERR,%rsp; \ 118 movq $(a),TF_TRAPNO(%rsp) ; \ 119 movq $0,TF_ADDR(%rsp) ; \ 120 jmp alltraps 121 IDTVEC(tss) 122 TRAP_ERR(T_TSSFLT) 123 IDTVEC(missing) 124 TRAP_ERR(T_SEGNPFLT) 125 IDTVEC(stk) 126 TRAP_ERR(T_STKFLT) 127 IDTVEC(align) 128 TRAP_ERR(T_ALIGNFLT) 129 130 /* 131 * alltraps entry point. Use swapgs if this is the first time in the 132 * kernel from userland. Reenable interrupts if they were enabled 133 * before the trap. This approximates SDT_SYS386TGT on the i386 port. 134 */ 135 136 SUPERALIGN_TEXT 137 .globl alltraps 138 .type alltraps,@function 139 alltraps: 140 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */ 141 jz alltraps_testi /* already running with kernel GS.base */ 142 swapgs 143 alltraps_testi: 144 testl $PSL_I,TF_RFLAGS(%rsp) 145 jz alltraps_pushregs 146 sti 147 alltraps_pushregs: 148 movq %rdi,TF_RDI(%rsp) 149 alltraps_pushregs_no_rdi: 150 movq %rsi,TF_RSI(%rsp) 151 movq %rdx,TF_RDX(%rsp) 152 movq %rcx,TF_RCX(%rsp) 153 movq %r8,TF_R8(%rsp) 154 movq %r9,TF_R9(%rsp) 155 movq %rax,TF_RAX(%rsp) 156 movq %rbx,TF_RBX(%rsp) 157 movq %rbp,TF_RBP(%rsp) 158 movq %r10,TF_R10(%rsp) 159 movq %r11,TF_R11(%rsp) 160 movq %r12,TF_R12(%rsp) 161 movq %r13,TF_R13(%rsp) 162 movq %r14,TF_R14(%rsp) 163 movq %r15,TF_R15(%rsp) 164 FAKE_MCOUNT(TF_RIP(%rsp)) 165 .globl calltrap 166 .type calltrap,@function 167 calltrap: 168 call trap 169 MEXITCOUNT 170 jmp doreti /* Handle any pending ASTs */ 171 172 /* 173 * alltraps_noen entry point. Unlike alltraps above, we want to 174 * leave the interrupts disabled. This corresponds to 175 * SDT_SYS386IGT on the i386 port. 176 */ 177 SUPERALIGN_TEXT 178 .globl alltraps_noen 179 .type alltraps_noen,@function 180 alltraps_noen: 181 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */ 182 jz alltraps_pushregs /* already running with kernel GS.base */ 183 swapgs 184 jmp alltraps_pushregs 185 186 IDTVEC(dblfault) 187 subq $TF_ERR,%rsp 188 movq $T_DOUBLEFLT,TF_TRAPNO(%rsp) 189 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */ 190 jz 1f /* already running with kernel GS.base */ 191 swapgs 192 1: call dblfault_handler 193 2: hlt 194 jmp 2b 195 196 IDTVEC(page) 197 subq $TF_ERR,%rsp 198 movq $T_PAGEFLT,TF_TRAPNO(%rsp) 199 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */ 200 jz 1f /* already running with kernel GS.base */ 201 swapgs 202 1: 203 movq %rdi,TF_RDI(%rsp) /* free up a GP register */ 204 movq %cr2,%rdi /* preserve %cr2 before .. */ 205 movq %rdi,TF_ADDR(%rsp) /* enabling interrupts. */ 206 testl $PSL_I,TF_RFLAGS(%rsp) 207 jz alltraps_pushregs_no_rdi 208 sti 209 jmp alltraps_pushregs_no_rdi 210 211 /* 212 * We have to special-case this one. If we get a trap in doreti() at 213 * the iretq stage, we'll reenter with the wrong gs state. We'll have 214 * to do a special the swapgs in this case even coming from the kernel. 215 * XXX linux has a trap handler for their equivalent of load_gs(). 216 */ 217 IDTVEC(prot) 218 subq $TF_ERR,%rsp 219 movq $T_PROTFLT,TF_TRAPNO(%rsp) 220 movq $0,TF_ADDR(%rsp) 221 movq %rdi,TF_RDI(%rsp) /* free up a GP register */ 222 leaq doreti_iret(%rip),%rdi 223 cmpq %rdi,TF_RIP(%rsp) 224 je 2f /* kernel but with user gsbase!! */ 225 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */ 226 jz 1f /* already running with kernel GS.base */ 227 2: 228 swapgs 229 1: 230 testl $PSL_I,TF_RFLAGS(%rsp) 231 jz alltraps_pushregs_no_rdi 232 sti 233 jmp alltraps_pushregs_no_rdi 234 235 /* 236 * Fast syscall entry point. We enter here with just our new %cs/%ss set, 237 * and the new privilige level. We are still running on the old user stack 238 * pointer. We have to juggle a few things around to find our stack etc. 239 * swapgs gives us access to our PCPU space only. 240 */ 241 IDTVEC(fast_syscall) 242 swapgs 243 movq %rsp,PCPU(SCRATCH_RSP) 244 movq PCPU(RSP0),%rsp 245 /* Now emulate a trapframe. Make the 8 byte alignment odd for call. */ 246 subq $TF_SIZE,%rsp 247 /* defer TF_RSP till we have a spare register */ 248 movq %r11,TF_RFLAGS(%rsp) 249 movq %rcx,TF_RIP(%rsp) /* %rcx original value is in %r10 */ 250 movq PCPU(SCRATCH_RSP),%r11 /* %r11 already saved */ 251 movq %r11,TF_RSP(%rsp) /* user stack pointer */ 252 sti 253 movq $KUDSEL,TF_SS(%rsp) 254 movq $KUCSEL,TF_CS(%rsp) 255 movq $2,TF_ERR(%rsp) 256 movq %rdi,TF_RDI(%rsp) /* arg 1 */ 257 movq %rsi,TF_RSI(%rsp) /* arg 2 */ 258 movq %rdx,TF_RDX(%rsp) /* arg 3 */ 259 movq %r10,TF_RCX(%rsp) /* arg 4 */ 260 movq %r8,TF_R8(%rsp) /* arg 5 */ 261 movq %r9,TF_R9(%rsp) /* arg 6 */ 262 movq %rax,TF_RAX(%rsp) /* syscall number */ 263 movq %rbx,TF_RBX(%rsp) /* C preserved */ 264 movq %rbp,TF_RBP(%rsp) /* C preserved */ 265 movq %r12,TF_R12(%rsp) /* C preserved */ 266 movq %r13,TF_R13(%rsp) /* C preserved */ 267 movq %r14,TF_R14(%rsp) /* C preserved */ 268 movq %r15,TF_R15(%rsp) /* C preserved */ 269 FAKE_MCOUNT(TF_RIP(%rsp)) 270 call syscall 271 movq PCPU(CURPCB),%rax 272 testq $PCB_FULLCTX,PCB_FLAGS(%rax) 273 jne 3f 274 1: /* Check for and handle AST's on return to userland */ 275 cli 276 movq PCPU(CURTHREAD),%rax 277 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax) 278 je 2f 279 sti 280 movq %rsp, %rdi 281 call ast 282 jmp 1b 283 2: /* restore preserved registers */ 284 MEXITCOUNT 285 movq TF_RDI(%rsp),%rdi /* bonus; preserve arg 1 */ 286 movq TF_RSI(%rsp),%rsi /* bonus: preserve arg 2 */ 287 movq TF_RDX(%rsp),%rdx /* return value 2 */ 288 movq TF_RAX(%rsp),%rax /* return value 1 */ 289 movq TF_RBX(%rsp),%rbx /* C preserved */ 290 movq TF_RBP(%rsp),%rbp /* C preserved */ 291 movq TF_R12(%rsp),%r12 /* C preserved */ 292 movq TF_R13(%rsp),%r13 /* C preserved */ 293 movq TF_R14(%rsp),%r14 /* C preserved */ 294 movq TF_R15(%rsp),%r15 /* C preserved */ 295 movq TF_RFLAGS(%rsp),%r11 /* original %rflags */ 296 movq TF_RIP(%rsp),%rcx /* original %rip */ 297 movq TF_RSP(%rsp),%r9 /* user stack pointer */ 298 movq %r9,%rsp /* original %rsp */ 299 swapgs 300 sysretq 301 3: /* Requested full context restore, use doreti for that */ 302 andq $~PCB_FULLCTX,PCB_FLAGS(%rax) 303 MEXITCOUNT 304 jmp doreti 305 306 /* 307 * Here for CYA insurance, in case a "syscall" instruction gets 308 * issued from 32 bit compatability mode. MSR_CSTAR has to point 309 * to *something* if EFER_SCE is enabled. 310 */ 311 IDTVEC(fast_syscall32) 312 sysret 313 314 /* 315 * NMI handling is special. 316 * 317 * First, NMIs do not respect the state of the processor's RFLAGS.IF 318 * bit and the NMI handler may be invoked at any time, including when 319 * the processor is in a critical section with RFLAGS.IF == 0. In 320 * particular, this means that the processor's GS.base values could be 321 * inconsistent on entry to the handler, and so we need to read 322 * MSR_GSBASE to determine if a 'swapgs' is needed. We use '%ebx', a 323 * C-preserved register, to remember whether to swap GS back on the 324 * exit path. 325 * 326 * Second, the processor treats NMIs specially, blocking further NMIs 327 * until an 'iretq' instruction is executed. We therefore need to 328 * execute the NMI handler with interrupts disabled to prevent a 329 * nested interrupt from executing an 'iretq' instruction and 330 * inadvertently taking the processor out of NMI mode. 331 */ 332 333 IDTVEC(nmi) 334 subq $TF_RIP,%rsp 335 movq $(T_NMI),TF_TRAPNO(%rsp) 336 movq $0,TF_ADDR(%rsp) 337 movq $0,TF_ERR(%rsp) 338 movq %rdi,TF_RDI(%rsp) 339 movq %rsi,TF_RSI(%rsp) 340 movq %rdx,TF_RDX(%rsp) 341 movq %rcx,TF_RCX(%rsp) 342 movq %r8,TF_R8(%rsp) 343 movq %r9,TF_R9(%rsp) 344 movq %rax,TF_RAX(%rsp) 345 movq %rbx,TF_RBX(%rsp) 346 movq %rbp,TF_RBP(%rsp) 347 movq %r10,TF_R10(%rsp) 348 movq %r11,TF_R11(%rsp) 349 movq %r12,TF_R12(%rsp) 350 movq %r13,TF_R13(%rsp) 351 movq %r14,TF_R14(%rsp) 352 movq %r15,TF_R15(%rsp) 353 xorl %ebx,%ebx 354 testb $SEL_RPL_MASK,TF_CS(%rsp) 355 jnz nmi_needswapgs /* we came from userland */ 356 movl $MSR_GSBASE,%ecx 357 rdmsr 358 cmpl $VM_MAXUSER_ADDRESS >> 32,%edx 359 jae nmi_calltrap /* GS.base holds a kernel VA */ 360 nmi_needswapgs: 361 incl %ebx 362 swapgs 363 /* Note: this label is also used by ddb and gdb: */ 364 nmi_calltrap: 365 FAKE_MCOUNT(TF_RIP(%rsp)) 366 call trap 367 MEXITCOUNT 368 testl %ebx,%ebx 369 jz nmi_restoreregs 370 swapgs 371 nmi_restoreregs: 372 movq TF_RDI(%rsp),%rdi 373 movq TF_RSI(%rsp),%rsi 374 movq TF_RDX(%rsp),%rdx 375 movq TF_RCX(%rsp),%rcx 376 movq TF_R8(%rsp),%r8 377 movq TF_R9(%rsp),%r9 378 movq TF_RAX(%rsp),%rax 379 movq TF_RBX(%rsp),%rbx 380 movq TF_RBP(%rsp),%rbp 381 movq TF_R10(%rsp),%r10 382 movq TF_R11(%rsp),%r11 383 movq TF_R12(%rsp),%r12 384 movq TF_R13(%rsp),%r13 385 movq TF_R14(%rsp),%r14 386 movq TF_R15(%rsp),%r15 387 addq $TF_RIP,%rsp 388 iretq 389 390 ENTRY(fork_trampoline) 391 movq %r12, %rdi /* function */ 392 movq %rbx, %rsi /* arg1 */ 393 movq %rsp, %rdx /* trapframe pointer */ 394 call fork_exit 395 MEXITCOUNT 396 jmp doreti /* Handle any ASTs */ 397 398 /* 399 * To efficiently implement classification of trap and interrupt handlers 400 * for profiling, there must be only trap handlers between the labels btrap 401 * and bintr, and only interrupt handlers between the labels bintr and 402 * eintr. This is implemented (partly) by including files that contain 403 * some of the handlers. Before including the files, set up a normal asm 404 * environment so that the included files doen't need to know that they are 405 * included. 406 */ 407 408 #ifdef COMPAT_IA32 409 .data 410 .p2align 4 411 .text 412 SUPERALIGN_TEXT 413 414 #include <amd64/ia32/ia32_exception.S> 415 #endif 416 417 .data 418 .p2align 4 419 .text 420 SUPERALIGN_TEXT 421 MCOUNT_LABEL(bintr) 422 423 #include <amd64/amd64/apic_vector.S> 424 425 #ifdef DEV_ATPIC 426 .data 427 .p2align 4 428 .text 429 SUPERALIGN_TEXT 430 431 #include <amd64/isa/atpic_vector.S> 432 #endif 433 434 .text 435 MCOUNT_LABEL(eintr) 436 437 /* 438 * void doreti(struct trapframe) 439 * 440 * Handle return from interrupts, traps and syscalls. 441 */ 442 .text 443 SUPERALIGN_TEXT 444 .type doreti,@function 445 doreti: 446 FAKE_MCOUNT($bintr) /* init "from" bintr -> doreti */ 447 /* 448 * Check if ASTs can be handled now. 449 */ 450 testb $SEL_RPL_MASK,TF_CS(%rsp) /* are we returning to user mode? */ 451 jz doreti_exit /* can't handle ASTs now if not */ 452 453 doreti_ast: 454 /* 455 * Check for ASTs atomically with returning. Disabling CPU 456 * interrupts provides sufficient locking eve in the SMP case, 457 * since we will be informed of any new ASTs by an IPI. 458 */ 459 cli 460 movq PCPU(CURTHREAD),%rax 461 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax) 462 je doreti_exit 463 sti 464 movq %rsp, %rdi /* pass a pointer to the trapframe */ 465 call ast 466 jmp doreti_ast 467 468 /* 469 * doreti_exit: pop registers, iret. 470 * 471 * The segment register pop is a special case, since it may 472 * fault if (for example) a sigreturn specifies bad segment 473 * registers. The fault is handled in trap.c. 474 */ 475 doreti_exit: 476 MEXITCOUNT 477 movq TF_RDI(%rsp),%rdi 478 movq TF_RSI(%rsp),%rsi 479 movq TF_RDX(%rsp),%rdx 480 movq TF_RCX(%rsp),%rcx 481 movq TF_R8(%rsp),%r8 482 movq TF_R9(%rsp),%r9 483 movq TF_RAX(%rsp),%rax 484 movq TF_RBX(%rsp),%rbx 485 movq TF_RBP(%rsp),%rbp 486 movq TF_R10(%rsp),%r10 487 movq TF_R11(%rsp),%r11 488 movq TF_R12(%rsp),%r12 489 movq TF_R13(%rsp),%r13 490 movq TF_R14(%rsp),%r14 491 movq TF_R15(%rsp),%r15 492 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */ 493 jz 1f /* keep running with kernel GS.base */ 494 cli 495 swapgs 496 1: addq $TF_RIP,%rsp /* skip over tf_err, tf_trapno */ 497 .globl doreti_iret 498 doreti_iret: 499 iretq 500 501 /* 502 * doreti_iret_fault. Alternative return code for 503 * the case where we get a fault in the doreti_exit code 504 * above. trap() (amd64/amd64/trap.c) catches this specific 505 * case, sends the process a signal and continues in the 506 * corresponding place in the code below. 507 */ 508 ALIGN_TEXT 509 .globl doreti_iret_fault 510 doreti_iret_fault: 511 subq $TF_RIP,%rsp /* space including tf_err, tf_trapno */ 512 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */ 513 jz 1f /* already running with kernel GS.base */ 514 swapgs 515 1: testl $PSL_I,TF_RFLAGS(%rsp) 516 jz 2f 517 sti 518 2: movq %rdi,TF_RDI(%rsp) 519 movq %rsi,TF_RSI(%rsp) 520 movq %rdx,TF_RDX(%rsp) 521 movq %rcx,TF_RCX(%rsp) 522 movq %r8,TF_R8(%rsp) 523 movq %r9,TF_R9(%rsp) 524 movq %rax,TF_RAX(%rsp) 525 movq %rbx,TF_RBX(%rsp) 526 movq %rbp,TF_RBP(%rsp) 527 movq %r10,TF_R10(%rsp) 528 movq %r11,TF_R11(%rsp) 529 movq %r12,TF_R12(%rsp) 530 movq %r13,TF_R13(%rsp) 531 movq %r14,TF_R14(%rsp) 532 movq %r15,TF_R15(%rsp) 533 movq $T_PROTFLT,TF_TRAPNO(%rsp) 534 movq $0,TF_ERR(%rsp) /* XXX should be the error code */ 535 movq $0,TF_ADDR(%rsp) 536 FAKE_MCOUNT(TF_RIP(%rsp)) 537 jmp calltrap
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