Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/exception.S
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * Copyright (c) 1989, 1990 William F. Jolitz. 3 * Copyright (c) 1990 The Regents of the University of California. 4 * Copyright (c) 2007 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * Portions of this software were developed by A. Joseph Koshy under 8 * sponsorship from the FreeBSD Foundation and Google, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $FreeBSD: releng/8.0/sys/amd64/amd64/exception.S 195535 2009-07-10 10:29:16Z kib $ 35 */ 36 37 #include "opt_atpic.h" 38 #include "opt_compat.h" 39 #include "opt_hwpmc_hooks.h" 40 #include "opt_kdtrace.h" 41 42 #include <machine/asmacros.h> 43 #include <machine/psl.h> 44 #include <machine/trap.h> 45 #include <machine/specialreg.h> 46 47 #include "assym.s" 48 49 #ifdef KDTRACE_HOOKS 50 .bss 51 .globl dtrace_invop_jump_addr 52 .align 8 53 .type dtrace_invop_jump_addr, @object 54 .size dtrace_invop_jump_addr, 8 55 dtrace_invop_jump_addr: 56 .zero 8 57 .globl dtrace_invop_calltrap_addr 58 .align 8 59 .type dtrace_invop_calltrap_addr, @object 60 .size dtrace_invop_calltrap_addr, 8 61 dtrace_invop_calltrap_addr: 62 .zero 8 63 #endif 64 .text 65 #ifdef HWPMC_HOOKS 66 ENTRY(start_exceptions) 67 #endif 68 69 /*****************************************************************************/ 70 /* Trap handling */ 71 /*****************************************************************************/ 72 /* 73 * Trap and fault vector routines. 74 * 75 * All traps are 'interrupt gates', SDT_SYSIGT. An interrupt gate pushes 76 * state on the stack but also disables interrupts. This is important for 77 * us for the use of the swapgs instruction. We cannot be interrupted 78 * until the GS.base value is correct. For most traps, we automatically 79 * then enable interrupts if the interrupted context had them enabled. 80 * This is equivalent to the i386 port's use of SDT_SYS386TGT. 81 * 82 * The cpu will push a certain amount of state onto the kernel stack for 83 * the current process. See amd64/include/frame.h. 84 * This includes the current RFLAGS (status register, which includes 85 * the interrupt disable state prior to the trap), the code segment register, 86 * and the return instruction pointer are pushed by the cpu. The cpu 87 * will also push an 'error' code for certain traps. We push a dummy 88 * error code for those traps where the cpu doesn't in order to maintain 89 * a consistent frame. We also push a contrived 'trap number'. 90 * 91 * The cpu does not push the general registers, we must do that, and we 92 * must restore them prior to calling 'iret'. The cpu adjusts the %cs and 93 * %ss segment registers, but does not mess with %ds, %es, or %fs. Thus we 94 * must load them with appropriate values for supervisor mode operation. 95 */ 96 97 MCOUNT_LABEL(user) 98 MCOUNT_LABEL(btrap) 99 100 /* Traps that we leave interrupts disabled for.. */ 101 #define TRAP_NOEN(a) \ 102 subq $TF_RIP,%rsp; \ 103 movl $(a),TF_TRAPNO(%rsp) ; \ 104 movq $0,TF_ADDR(%rsp) ; \ 105 movq $0,TF_ERR(%rsp) ; \ 106 jmp alltraps_noen 107 IDTVEC(dbg) 108 TRAP_NOEN(T_TRCTRAP) 109 IDTVEC(bpt) 110 TRAP_NOEN(T_BPTFLT) 111 112 /* Regular traps; The cpu does not supply tf_err for these. */ 113 #define TRAP(a) \ 114 subq $TF_RIP,%rsp; \ 115 movl $(a),TF_TRAPNO(%rsp) ; \ 116 movq $0,TF_ADDR(%rsp) ; \ 117 movq $0,TF_ERR(%rsp) ; \ 118 jmp alltraps 119 IDTVEC(div) 120 TRAP(T_DIVIDE) 121 IDTVEC(ofl) 122 TRAP(T_OFLOW) 123 IDTVEC(bnd) 124 TRAP(T_BOUND) 125 IDTVEC(ill) 126 TRAP(T_PRIVINFLT) 127 IDTVEC(dna) 128 TRAP(T_DNA) 129 IDTVEC(fpusegm) 130 TRAP(T_FPOPFLT) 131 IDTVEC(mchk) 132 TRAP(T_MCHK) 133 IDTVEC(rsvd) 134 TRAP(T_RESERVED) 135 IDTVEC(fpu) 136 TRAP(T_ARITHTRAP) 137 IDTVEC(xmm) 138 TRAP(T_XMMFLT) 139 140 /* This group of traps have tf_err already pushed by the cpu */ 141 #define TRAP_ERR(a) \ 142 subq $TF_ERR,%rsp; \ 143 movl $(a),TF_TRAPNO(%rsp) ; \ 144 movq $0,TF_ADDR(%rsp) ; \ 145 jmp alltraps 146 IDTVEC(tss) 147 TRAP_ERR(T_TSSFLT) 148 IDTVEC(missing) 149 TRAP_ERR(T_SEGNPFLT) 150 IDTVEC(stk) 151 TRAP_ERR(T_STKFLT) 152 IDTVEC(align) 153 TRAP_ERR(T_ALIGNFLT) 154 155 /* 156 * alltraps entry point. Use swapgs if this is the first time in the 157 * kernel from userland. Reenable interrupts if they were enabled 158 * before the trap. This approximates SDT_SYS386TGT on the i386 port. 159 */ 160 161 SUPERALIGN_TEXT 162 .globl alltraps 163 .type alltraps,@function 164 alltraps: 165 movq %rdi,TF_RDI(%rsp) 166 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */ 167 jz alltraps_testi /* already running with kernel GS.base */ 168 swapgs 169 movq PCPU(CURPCB),%rdi 170 movb $0,PCB_FULL_IRET(%rdi) 171 movw %fs,TF_FS(%rsp) 172 movw %gs,TF_GS(%rsp) 173 movw %es,TF_ES(%rsp) 174 movw %ds,TF_DS(%rsp) 175 alltraps_testi: 176 testl $PSL_I,TF_RFLAGS(%rsp) 177 jz alltraps_pushregs_no_rdi 178 sti 179 alltraps_pushregs_no_rdi: 180 movq %rsi,TF_RSI(%rsp) 181 movq %rdx,TF_RDX(%rsp) 182 movq %rcx,TF_RCX(%rsp) 183 movq %r8,TF_R8(%rsp) 184 movq %r9,TF_R9(%rsp) 185 movq %rax,TF_RAX(%rsp) 186 movq %rbx,TF_RBX(%rsp) 187 movq %rbp,TF_RBP(%rsp) 188 movq %r10,TF_R10(%rsp) 189 movq %r11,TF_R11(%rsp) 190 movq %r12,TF_R12(%rsp) 191 movq %r13,TF_R13(%rsp) 192 movq %r14,TF_R14(%rsp) 193 movq %r15,TF_R15(%rsp) 194 movl $TF_HASSEGS,TF_FLAGS(%rsp) 195 FAKE_MCOUNT(TF_RIP(%rsp)) 196 #ifdef KDTRACE_HOOKS 197 /* 198 * DTrace Function Boundary Trace (fbt) probes are triggered 199 * by int3 (0xcc) which causes the #BP (T_BPTFLT) breakpoint 200 * interrupt. For all other trap types, just handle them in 201 * the usual way. 202 */ 203 cmpl $T_BPTFLT,TF_TRAPNO(%rsp) 204 jne calltrap 205 206 /* Check if there is no DTrace hook registered. */ 207 cmpq $0,dtrace_invop_jump_addr 208 je calltrap 209 210 /* 211 * Set our jump address for the jump back in the event that 212 * the breakpoint wasn't caused by DTrace at all. 213 */ 214 movq $calltrap, dtrace_invop_calltrap_addr(%rip) 215 216 /* Jump to the code hooked in by DTrace. */ 217 movq dtrace_invop_jump_addr, %rax 218 jmpq *dtrace_invop_jump_addr 219 #endif 220 .globl calltrap 221 .type calltrap,@function 222 calltrap: 223 movq %rsp, %rdi 224 call trap 225 MEXITCOUNT 226 jmp doreti /* Handle any pending ASTs */ 227 228 /* 229 * alltraps_noen entry point. Unlike alltraps above, we want to 230 * leave the interrupts disabled. This corresponds to 231 * SDT_SYS386IGT on the i386 port. 232 */ 233 SUPERALIGN_TEXT 234 .globl alltraps_noen 235 .type alltraps_noen,@function 236 alltraps_noen: 237 movq %rdi,TF_RDI(%rsp) 238 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */ 239 jz 1f /* already running with kernel GS.base */ 240 swapgs 241 movq PCPU(CURPCB),%rdi 242 movb $0,PCB_FULL_IRET(%rdi) 243 1: movw %fs,TF_FS(%rsp) 244 movw %gs,TF_GS(%rsp) 245 movw %es,TF_ES(%rsp) 246 movw %ds,TF_DS(%rsp) 247 jmp alltraps_pushregs_no_rdi 248 249 IDTVEC(dblfault) 250 subq $TF_ERR,%rsp 251 movl $T_DOUBLEFLT,TF_TRAPNO(%rsp) 252 movq $0,TF_ADDR(%rsp) 253 movq $0,TF_ERR(%rsp) 254 movq %rdi,TF_RDI(%rsp) 255 movq %rsi,TF_RSI(%rsp) 256 movq %rdx,TF_RDX(%rsp) 257 movq %rcx,TF_RCX(%rsp) 258 movq %r8,TF_R8(%rsp) 259 movq %r9,TF_R9(%rsp) 260 movq %rax,TF_RAX(%rsp) 261 movq %rbx,TF_RBX(%rsp) 262 movq %rbp,TF_RBP(%rsp) 263 movq %r10,TF_R10(%rsp) 264 movq %r11,TF_R11(%rsp) 265 movq %r12,TF_R12(%rsp) 266 movq %r13,TF_R13(%rsp) 267 movq %r14,TF_R14(%rsp) 268 movq %r15,TF_R15(%rsp) 269 movw %fs,TF_FS(%rsp) 270 movw %gs,TF_GS(%rsp) 271 movw %es,TF_ES(%rsp) 272 movw %ds,TF_DS(%rsp) 273 movl $TF_HASSEGS,TF_FLAGS(%rsp) 274 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */ 275 jz 1f /* already running with kernel GS.base */ 276 swapgs 277 1: movq %rsp, %rdi 278 call dblfault_handler 279 2: hlt 280 jmp 2b 281 282 IDTVEC(page) 283 subq $TF_ERR,%rsp 284 movl $T_PAGEFLT,TF_TRAPNO(%rsp) 285 movq %rdi,TF_RDI(%rsp) /* free up a GP register */ 286 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */ 287 jz 1f /* already running with kernel GS.base */ 288 swapgs 289 movq PCPU(CURPCB),%rdi 290 movb $0,PCB_FULL_IRET(%rdi) 291 1: movq %cr2,%rdi /* preserve %cr2 before .. */ 292 movq %rdi,TF_ADDR(%rsp) /* enabling interrupts. */ 293 movw %fs,TF_FS(%rsp) 294 movw %gs,TF_GS(%rsp) 295 movw %es,TF_ES(%rsp) 296 movw %ds,TF_DS(%rsp) 297 testl $PSL_I,TF_RFLAGS(%rsp) 298 jz alltraps_pushregs_no_rdi 299 sti 300 jmp alltraps_pushregs_no_rdi 301 302 /* 303 * We have to special-case this one. If we get a trap in doreti() at 304 * the iretq stage, we'll reenter with the wrong gs state. We'll have 305 * to do a special the swapgs in this case even coming from the kernel. 306 * XXX linux has a trap handler for their equivalent of load_gs(). 307 */ 308 IDTVEC(prot) 309 subq $TF_ERR,%rsp 310 movl $T_PROTFLT,TF_TRAPNO(%rsp) 311 movq $0,TF_ADDR(%rsp) 312 movq %rdi,TF_RDI(%rsp) /* free up a GP register */ 313 leaq doreti_iret(%rip),%rdi 314 cmpq %rdi,TF_RIP(%rsp) 315 je 1f /* kernel but with user gsbase!! */ 316 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */ 317 jz 2f /* already running with kernel GS.base */ 318 1: swapgs 319 2: movq PCPU(CURPCB),%rdi 320 movb $1,PCB_FULL_IRET(%rdi) /* always full iret from GPF */ 321 movw %fs,TF_FS(%rsp) 322 movw %gs,TF_GS(%rsp) 323 movw %es,TF_ES(%rsp) 324 movw %ds,TF_DS(%rsp) 325 testl $PSL_I,TF_RFLAGS(%rsp) 326 jz alltraps_pushregs_no_rdi 327 sti 328 jmp alltraps_pushregs_no_rdi 329 330 /* 331 * Fast syscall entry point. We enter here with just our new %cs/%ss set, 332 * and the new privilige level. We are still running on the old user stack 333 * pointer. We have to juggle a few things around to find our stack etc. 334 * swapgs gives us access to our PCPU space only. 335 */ 336 IDTVEC(fast_syscall) 337 swapgs 338 movq %rsp,PCPU(SCRATCH_RSP) 339 movq PCPU(RSP0),%rsp 340 /* Now emulate a trapframe. Make the 8 byte alignment odd for call. */ 341 subq $TF_SIZE,%rsp 342 /* defer TF_RSP till we have a spare register */ 343 movq %r11,TF_RFLAGS(%rsp) 344 movq %rcx,TF_RIP(%rsp) /* %rcx original value is in %r10 */ 345 movq PCPU(SCRATCH_RSP),%r11 /* %r11 already saved */ 346 movq %r11,TF_RSP(%rsp) /* user stack pointer */ 347 movw %fs,TF_FS(%rsp) 348 movw %gs,TF_GS(%rsp) 349 movw %es,TF_ES(%rsp) 350 movw %ds,TF_DS(%rsp) 351 movq PCPU(CURPCB),%r11 352 movb $0,PCB_FULL_IRET(%r11) 353 sti 354 movq $KUDSEL,TF_SS(%rsp) 355 movq $KUCSEL,TF_CS(%rsp) 356 movq $2,TF_ERR(%rsp) 357 movq %rdi,TF_RDI(%rsp) /* arg 1 */ 358 movq %rsi,TF_RSI(%rsp) /* arg 2 */ 359 movq %rdx,TF_RDX(%rsp) /* arg 3 */ 360 movq %r10,TF_RCX(%rsp) /* arg 4 */ 361 movq %r8,TF_R8(%rsp) /* arg 5 */ 362 movq %r9,TF_R9(%rsp) /* arg 6 */ 363 movq %rax,TF_RAX(%rsp) /* syscall number */ 364 movq %rbx,TF_RBX(%rsp) /* C preserved */ 365 movq %rbp,TF_RBP(%rsp) /* C preserved */ 366 movq %r12,TF_R12(%rsp) /* C preserved */ 367 movq %r13,TF_R13(%rsp) /* C preserved */ 368 movq %r14,TF_R14(%rsp) /* C preserved */ 369 movq %r15,TF_R15(%rsp) /* C preserved */ 370 movl $TF_HASSEGS,TF_FLAGS(%rsp) 371 FAKE_MCOUNT(TF_RIP(%rsp)) 372 movq %rsp, %rdi 373 call syscall 374 movq PCPU(CURPCB),%rax 375 andq $~PCB_FULLCTX,PCB_FLAGS(%rax) 376 MEXITCOUNT 377 jmp doreti 378 379 /* 380 * Here for CYA insurance, in case a "syscall" instruction gets 381 * issued from 32 bit compatability mode. MSR_CSTAR has to point 382 * to *something* if EFER_SCE is enabled. 383 */ 384 IDTVEC(fast_syscall32) 385 sysret 386 387 /* 388 * NMI handling is special. 389 * 390 * First, NMIs do not respect the state of the processor's RFLAGS.IF 391 * bit. The NMI handler may be entered at any time, including when 392 * the processor is in a critical section with RFLAGS.IF == 0. 393 * The processor's GS.base value could be invalid on entry to the 394 * handler. 395 * 396 * Second, the processor treats NMIs specially, blocking further NMIs 397 * until an 'iretq' instruction is executed. We thus need to execute 398 * the NMI handler with interrupts disabled, to prevent a nested interrupt 399 * from executing an 'iretq' instruction and inadvertently taking the 400 * processor out of NMI mode. 401 * 402 * Third, the NMI handler runs on its own stack (tss_ist2). The canonical 403 * GS.base value for the processor is stored just above the bottom of its 404 * NMI stack. For NMIs taken from kernel mode, the current value in 405 * the processor's GS.base is saved at entry to C-preserved register %r12, 406 * the canonical value for GS.base is then loaded into the processor, and 407 * the saved value is restored at exit time. For NMIs taken from user mode, 408 * the cheaper 'SWAPGS' instructions are used for swapping GS.base. 409 */ 410 411 IDTVEC(nmi) 412 subq $TF_RIP,%rsp 413 movl $(T_NMI),TF_TRAPNO(%rsp) 414 movq $0,TF_ADDR(%rsp) 415 movq $0,TF_ERR(%rsp) 416 movq %rdi,TF_RDI(%rsp) 417 movq %rsi,TF_RSI(%rsp) 418 movq %rdx,TF_RDX(%rsp) 419 movq %rcx,TF_RCX(%rsp) 420 movq %r8,TF_R8(%rsp) 421 movq %r9,TF_R9(%rsp) 422 movq %rax,TF_RAX(%rsp) 423 movq %rbx,TF_RBX(%rsp) 424 movq %rbp,TF_RBP(%rsp) 425 movq %r10,TF_R10(%rsp) 426 movq %r11,TF_R11(%rsp) 427 movq %r12,TF_R12(%rsp) 428 movq %r13,TF_R13(%rsp) 429 movq %r14,TF_R14(%rsp) 430 movq %r15,TF_R15(%rsp) 431 movw %fs,TF_FS(%rsp) 432 movw %gs,TF_GS(%rsp) 433 movw %es,TF_ES(%rsp) 434 movw %ds,TF_DS(%rsp) 435 movl $TF_HASSEGS,TF_FLAGS(%rsp) 436 xorl %ebx,%ebx 437 testb $SEL_RPL_MASK,TF_CS(%rsp) 438 jnz nmi_fromuserspace 439 /* 440 * We've interrupted the kernel. Preserve GS.base in %r12. 441 */ 442 movl $MSR_GSBASE,%ecx 443 rdmsr 444 movq %rax,%r12 445 shlq $32,%rdx 446 orq %rdx,%r12 447 /* Retrieve and load the canonical value for GS.base. */ 448 movq TF_SIZE(%rsp),%rdx 449 movl %edx,%eax 450 shrq $32,%rdx 451 wrmsr 452 jmp nmi_calltrap 453 nmi_fromuserspace: 454 incl %ebx 455 swapgs 456 /* Note: this label is also used by ddb and gdb: */ 457 nmi_calltrap: 458 FAKE_MCOUNT(TF_RIP(%rsp)) 459 movq %rsp, %rdi 460 call trap 461 MEXITCOUNT 462 #ifdef HWPMC_HOOKS 463 /* 464 * Capture a userspace callchain if needed. 465 * 466 * - Check if the current trap was from user mode. 467 * - Check if the current thread is valid. 468 * - Check if the thread requires a user call chain to be 469 * captured. 470 * 471 * We are still in NMI mode at this point. 472 */ 473 testl %ebx,%ebx 474 jz nocallchain /* not from userspace */ 475 movq PCPU(CURTHREAD),%rax 476 orq %rax,%rax /* curthread present? */ 477 jz nocallchain 478 testl $TDP_CALLCHAIN,TD_PFLAGS(%rax) /* flagged for capture? */ 479 jz nocallchain 480 /* 481 * A user callchain is to be captured, so: 482 * - Move execution to the regular kernel stack, to allow for 483 * nested NMI interrupts. 484 * - Take the processor out of "NMI" mode by faking an "iret". 485 * - Enable interrupts, so that copyin() can work. 486 */ 487 movq %rsp,%rsi /* source stack pointer */ 488 movq $TF_SIZE,%rcx 489 movq PCPU(RSP0),%rdx 490 subq %rcx,%rdx 491 movq %rdx,%rdi /* destination stack pointer */ 492 493 shrq $3,%rcx /* trap frame size in long words */ 494 cld 495 rep 496 movsq /* copy trapframe */ 497 498 movl %ss,%eax 499 pushq %rax /* tf_ss */ 500 pushq %rdx /* tf_rsp (on kernel stack) */ 501 pushfq /* tf_rflags */ 502 movl %cs,%eax 503 pushq %rax /* tf_cs */ 504 pushq $outofnmi /* tf_rip */ 505 iretq 506 outofnmi: 507 /* 508 * At this point the processor has exited NMI mode and is running 509 * with interrupts turned off on the normal kernel stack. 510 * 511 * If a pending NMI gets recognized at or after this point, it 512 * will cause a kernel callchain to be traced. 513 * 514 * We turn interrupts back on, and call the user callchain capture hook. 515 */ 516 movq pmc_hook,%rax 517 orq %rax,%rax 518 jz nocallchain 519 movq PCPU(CURTHREAD),%rdi /* thread */ 520 movq $PMC_FN_USER_CALLCHAIN,%rsi /* command */ 521 movq %rsp,%rdx /* frame */ 522 sti 523 call *%rax 524 cli 525 nocallchain: 526 #endif 527 testl %ebx,%ebx 528 jnz doreti_exit 529 nmi_kernelexit: 530 /* 531 * Put back the preserved MSR_GSBASE value. 532 */ 533 movl $MSR_GSBASE,%ecx 534 movq %r12,%rdx 535 movl %edx,%eax 536 shrq $32,%rdx 537 wrmsr 538 nmi_restoreregs: 539 movq TF_RDI(%rsp),%rdi 540 movq TF_RSI(%rsp),%rsi 541 movq TF_RDX(%rsp),%rdx 542 movq TF_RCX(%rsp),%rcx 543 movq TF_R8(%rsp),%r8 544 movq TF_R9(%rsp),%r9 545 movq TF_RAX(%rsp),%rax 546 movq TF_RBX(%rsp),%rbx 547 movq TF_RBP(%rsp),%rbp 548 movq TF_R10(%rsp),%r10 549 movq TF_R11(%rsp),%r11 550 movq TF_R12(%rsp),%r12 551 movq TF_R13(%rsp),%r13 552 movq TF_R14(%rsp),%r14 553 movq TF_R15(%rsp),%r15 554 addq $TF_RIP,%rsp 555 iretq 556 557 ENTRY(fork_trampoline) 558 movq %r12, %rdi /* function */ 559 movq %rbx, %rsi /* arg1 */ 560 movq %rsp, %rdx /* trapframe pointer */ 561 call fork_exit 562 MEXITCOUNT 563 jmp doreti /* Handle any ASTs */ 564 565 /* 566 * To efficiently implement classification of trap and interrupt handlers 567 * for profiling, there must be only trap handlers between the labels btrap 568 * and bintr, and only interrupt handlers between the labels bintr and 569 * eintr. This is implemented (partly) by including files that contain 570 * some of the handlers. Before including the files, set up a normal asm 571 * environment so that the included files doen't need to know that they are 572 * included. 573 */ 574 575 #ifdef COMPAT_IA32 576 .data 577 .p2align 4 578 .text 579 SUPERALIGN_TEXT 580 581 #include <amd64/ia32/ia32_exception.S> 582 #endif 583 584 .data 585 .p2align 4 586 .text 587 SUPERALIGN_TEXT 588 MCOUNT_LABEL(bintr) 589 590 #include <amd64/amd64/apic_vector.S> 591 592 #ifdef DEV_ATPIC 593 .data 594 .p2align 4 595 .text 596 SUPERALIGN_TEXT 597 598 #include <amd64/isa/atpic_vector.S> 599 #endif 600 601 .text 602 MCOUNT_LABEL(eintr) 603 604 /* 605 * void doreti(struct trapframe) 606 * 607 * Handle return from interrupts, traps and syscalls. 608 */ 609 .text 610 SUPERALIGN_TEXT 611 .type doreti,@function 612 doreti: 613 FAKE_MCOUNT($bintr) /* init "from" bintr -> doreti */ 614 /* 615 * Check if ASTs can be handled now. 616 */ 617 testb $SEL_RPL_MASK,TF_CS(%rsp) /* are we returning to user mode? */ 618 jz doreti_exit /* can't handle ASTs now if not */ 619 620 doreti_ast: 621 /* 622 * Check for ASTs atomically with returning. Disabling CPU 623 * interrupts provides sufficient locking eve in the SMP case, 624 * since we will be informed of any new ASTs by an IPI. 625 */ 626 cli 627 movq PCPU(CURTHREAD),%rax 628 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax) 629 je doreti_exit 630 sti 631 movq %rsp, %rdi /* pass a pointer to the trapframe */ 632 call ast 633 jmp doreti_ast 634 635 /* 636 * doreti_exit: pop registers, iret. 637 * 638 * The segment register pop is a special case, since it may 639 * fault if (for example) a sigreturn specifies bad segment 640 * registers. The fault is handled in trap.c. 641 */ 642 doreti_exit: 643 MEXITCOUNT 644 movq PCPU(CURTHREAD),%r8 645 movq TD_PCB(%r8),%r8 646 647 /* 648 * Do not reload segment registers for kernel. 649 * Since we do not reload segments registers with sane 650 * values on kernel entry, descriptors referenced by 651 * segments registers may be not valid. This is fatal 652 * for the usermode, but is innocent for the kernel. 653 */ 654 testb $SEL_RPL_MASK,TF_CS(%rsp) 655 jz ld_regs 656 cmpb $0,PCB_FULL_IRET(%r8) 657 je ld_regs 658 testl $TF_HASSEGS,TF_FLAGS(%rsp) 659 je set_segs 660 661 do_segs: 662 /* Restore %fs and fsbase */ 663 movw TF_FS(%rsp),%ax 664 .globl ld_fs 665 ld_fs: movw %ax,%fs 666 cmpw $KUF32SEL,%ax 667 jne 1f 668 movl $MSR_FSBASE,%ecx 669 movl PCB_FSBASE(%r8),%eax 670 movl PCB_FSBASE+4(%r8),%edx 671 wrmsr 672 1: 673 /* Restore %gs and gsbase */ 674 movw TF_GS(%rsp),%si 675 pushfq 676 cli 677 movl $MSR_GSBASE,%ecx 678 rdmsr 679 .globl ld_gs 680 ld_gs: movw %si,%gs 681 wrmsr 682 popfq 683 cmpw $KUG32SEL,%si 684 jne 1f 685 movl $MSR_KGSBASE,%ecx 686 movl PCB_GSBASE(%r8),%eax 687 movl PCB_GSBASE+4(%r8),%edx 688 wrmsr 689 1: .globl ld_es 690 ld_es: movw TF_ES(%rsp),%es 691 .globl ld_ds 692 ld_ds: movw TF_DS(%rsp),%ds 693 ld_regs:movq TF_RDI(%rsp),%rdi 694 movq TF_RSI(%rsp),%rsi 695 movq TF_RDX(%rsp),%rdx 696 movq TF_RCX(%rsp),%rcx 697 movq TF_R8(%rsp),%r8 698 movq TF_R9(%rsp),%r9 699 movq TF_RAX(%rsp),%rax 700 movq TF_RBX(%rsp),%rbx 701 movq TF_RBP(%rsp),%rbp 702 movq TF_R10(%rsp),%r10 703 movq TF_R11(%rsp),%r11 704 movq TF_R12(%rsp),%r12 705 movq TF_R13(%rsp),%r13 706 movq TF_R14(%rsp),%r14 707 movq TF_R15(%rsp),%r15 708 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */ 709 jz 1f /* keep running with kernel GS.base */ 710 cli 711 swapgs 712 1: addq $TF_RIP,%rsp /* skip over tf_err, tf_trapno */ 713 .globl doreti_iret 714 doreti_iret: 715 iretq 716 717 set_segs: 718 movw $KUDSEL,%ax 719 movw %ax,TF_DS(%rsp) 720 movw %ax,TF_ES(%rsp) 721 movw $KUF32SEL,TF_FS(%rsp) 722 movw $KUG32SEL,TF_GS(%rsp) 723 jmp do_segs 724 725 /* 726 * doreti_iret_fault. Alternative return code for 727 * the case where we get a fault in the doreti_exit code 728 * above. trap() (amd64/amd64/trap.c) catches this specific 729 * case, sends the process a signal and continues in the 730 * corresponding place in the code below. 731 */ 732 ALIGN_TEXT 733 .globl doreti_iret_fault 734 doreti_iret_fault: 735 subq $TF_RIP,%rsp /* space including tf_err, tf_trapno */ 736 testl $PSL_I,TF_RFLAGS(%rsp) 737 jz 1f 738 sti 739 1: movw %fs,TF_FS(%rsp) 740 movw %gs,TF_GS(%rsp) 741 movw %es,TF_ES(%rsp) 742 movw %ds,TF_DS(%rsp) 743 movl $TF_HASSEGS,TF_FLAGS(%rsp) 744 movq %rdi,TF_RDI(%rsp) 745 movq %rsi,TF_RSI(%rsp) 746 movq %rdx,TF_RDX(%rsp) 747 movq %rcx,TF_RCX(%rsp) 748 movq %r8,TF_R8(%rsp) 749 movq %r9,TF_R9(%rsp) 750 movq %rax,TF_RAX(%rsp) 751 movq %rbx,TF_RBX(%rsp) 752 movq %rbp,TF_RBP(%rsp) 753 movq %r10,TF_R10(%rsp) 754 movq %r11,TF_R11(%rsp) 755 movq %r12,TF_R12(%rsp) 756 movq %r13,TF_R13(%rsp) 757 movq %r14,TF_R14(%rsp) 758 movq %r15,TF_R15(%rsp) 759 movl $T_PROTFLT,TF_TRAPNO(%rsp) 760 movq $0,TF_ERR(%rsp) /* XXX should be the error code */ 761 movq $0,TF_ADDR(%rsp) 762 FAKE_MCOUNT(TF_RIP(%rsp)) 763 jmp calltrap 764 765 ALIGN_TEXT 766 .globl ds_load_fault 767 ds_load_fault: 768 movl $T_PROTFLT,TF_TRAPNO(%rsp) 769 movq %rsp, %rdi 770 call trap 771 movw $KUDSEL,TF_DS(%rsp) 772 jmp doreti 773 774 ALIGN_TEXT 775 .globl es_load_fault 776 es_load_fault: 777 movl $T_PROTFLT,TF_TRAPNO(%rsp) 778 movq %rsp, %rdi 779 call trap 780 movw $KUDSEL,TF_ES(%rsp) 781 jmp doreti 782 783 ALIGN_TEXT 784 .globl fs_load_fault 785 fs_load_fault: 786 movl $T_PROTFLT,TF_TRAPNO(%rsp) 787 movq %rsp, %rdi 788 call trap 789 movw $KUF32SEL,TF_FS(%rsp) 790 jmp doreti 791 792 ALIGN_TEXT 793 .globl gs_load_fault 794 gs_load_fault: 795 popfq 796 movl $T_PROTFLT,TF_TRAPNO(%rsp) 797 movq %rsp, %rdi 798 call trap 799 movw $KUG32SEL,TF_GS(%rsp) 800 jmp doreti 801 #ifdef HWPMC_HOOKS 802 ENTRY(end_exceptions) 803 #endif
Cache object: 441e2fb0dbc6d3ac0f3f88094a6884e5
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]