1 /*-
2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
4 * Copyright (c) 2007 The FreeBSD Foundation
5 * All rights reserved.
6 *
7 * Portions of this software were developed by A. Joseph Koshy under
8 * sponsorship from the FreeBSD Foundation and Google, Inc.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $FreeBSD: releng/8.1/sys/amd64/amd64/exception.S 208294 2010-05-19 09:32:59Z kib $
35 */
36
37 #include "opt_atpic.h"
38 #include "opt_compat.h"
39 #include "opt_hwpmc_hooks.h"
40 #include "opt_kdtrace.h"
41
42 #include <machine/asmacros.h>
43 #include <machine/psl.h>
44 #include <machine/trap.h>
45 #include <machine/specialreg.h>
46
47 #include "assym.s"
48
49 #ifdef KDTRACE_HOOKS
50 .bss
51 .globl dtrace_invop_jump_addr
52 .align 8
53 .type dtrace_invop_jump_addr,@object
54 .size dtrace_invop_jump_addr,8
55 dtrace_invop_jump_addr:
56 .zero 8
57 .globl dtrace_invop_calltrap_addr
58 .align 8
59 .type dtrace_invop_calltrap_addr,@object
60 .size dtrace_invop_calltrap_addr,8
61 dtrace_invop_calltrap_addr:
62 .zero 8
63 #endif
64 .text
65 #ifdef HWPMC_HOOKS
66 ENTRY(start_exceptions)
67 #endif
68
69 /*****************************************************************************/
70 /* Trap handling */
71 /*****************************************************************************/
72 /*
73 * Trap and fault vector routines.
74 *
75 * All traps are 'interrupt gates', SDT_SYSIGT. An interrupt gate pushes
76 * state on the stack but also disables interrupts. This is important for
77 * us for the use of the swapgs instruction. We cannot be interrupted
78 * until the GS.base value is correct. For most traps, we automatically
79 * then enable interrupts if the interrupted context had them enabled.
80 * This is equivalent to the i386 port's use of SDT_SYS386TGT.
81 *
82 * The cpu will push a certain amount of state onto the kernel stack for
83 * the current process. See amd64/include/frame.h.
84 * This includes the current RFLAGS (status register, which includes
85 * the interrupt disable state prior to the trap), the code segment register,
86 * and the return instruction pointer are pushed by the cpu. The cpu
87 * will also push an 'error' code for certain traps. We push a dummy
88 * error code for those traps where the cpu doesn't in order to maintain
89 * a consistent frame. We also push a contrived 'trap number'.
90 *
91 * The cpu does not push the general registers, we must do that, and we
92 * must restore them prior to calling 'iret'. The cpu adjusts the %cs and
93 * %ss segment registers, but does not mess with %ds, %es, or %fs. Thus we
94 * must load them with appropriate values for supervisor mode operation.
95 */
96
97 MCOUNT_LABEL(user)
98 MCOUNT_LABEL(btrap)
99
100 /* Traps that we leave interrupts disabled for.. */
101 #define TRAP_NOEN(a) \
102 subq $TF_RIP,%rsp; \
103 movl $(a),TF_TRAPNO(%rsp) ; \
104 movq $0,TF_ADDR(%rsp) ; \
105 movq $0,TF_ERR(%rsp) ; \
106 jmp alltraps_noen
107 IDTVEC(dbg)
108 TRAP_NOEN(T_TRCTRAP)
109 IDTVEC(bpt)
110 TRAP_NOEN(T_BPTFLT)
111
112 /* Regular traps; The cpu does not supply tf_err for these. */
113 #define TRAP(a) \
114 subq $TF_RIP,%rsp; \
115 movl $(a),TF_TRAPNO(%rsp) ; \
116 movq $0,TF_ADDR(%rsp) ; \
117 movq $0,TF_ERR(%rsp) ; \
118 jmp alltraps
119 IDTVEC(div)
120 TRAP(T_DIVIDE)
121 IDTVEC(ofl)
122 TRAP(T_OFLOW)
123 IDTVEC(bnd)
124 TRAP(T_BOUND)
125 IDTVEC(ill)
126 TRAP(T_PRIVINFLT)
127 IDTVEC(dna)
128 TRAP(T_DNA)
129 IDTVEC(fpusegm)
130 TRAP(T_FPOPFLT)
131 IDTVEC(mchk)
132 TRAP(T_MCHK)
133 IDTVEC(rsvd)
134 TRAP(T_RESERVED)
135 IDTVEC(fpu)
136 TRAP(T_ARITHTRAP)
137 IDTVEC(xmm)
138 TRAP(T_XMMFLT)
139
140 /* This group of traps have tf_err already pushed by the cpu */
141 #define TRAP_ERR(a) \
142 subq $TF_ERR,%rsp; \
143 movl $(a),TF_TRAPNO(%rsp) ; \
144 movq $0,TF_ADDR(%rsp) ; \
145 jmp alltraps
146 IDTVEC(tss)
147 TRAP_ERR(T_TSSFLT)
148 IDTVEC(missing)
149 TRAP_ERR(T_SEGNPFLT)
150 IDTVEC(stk)
151 TRAP_ERR(T_STKFLT)
152 IDTVEC(align)
153 TRAP_ERR(T_ALIGNFLT)
154
155 /*
156 * alltraps entry point. Use swapgs if this is the first time in the
157 * kernel from userland. Reenable interrupts if they were enabled
158 * before the trap. This approximates SDT_SYS386TGT on the i386 port.
159 */
160 SUPERALIGN_TEXT
161 .globl alltraps
162 .type alltraps,@function
163 alltraps:
164 movq %rdi,TF_RDI(%rsp)
165 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
166 jz alltraps_testi /* already running with kernel GS.base */
167 swapgs
168 movq PCPU(CURPCB),%rdi
169 movb $0,PCB_FULL_IRET(%rdi)
170 movw %fs,TF_FS(%rsp)
171 movw %gs,TF_GS(%rsp)
172 movw %es,TF_ES(%rsp)
173 movw %ds,TF_DS(%rsp)
174 alltraps_testi:
175 testl $PSL_I,TF_RFLAGS(%rsp)
176 jz alltraps_pushregs_no_rdi
177 sti
178 alltraps_pushregs_no_rdi:
179 movq %rsi,TF_RSI(%rsp)
180 movq %rdx,TF_RDX(%rsp)
181 movq %rcx,TF_RCX(%rsp)
182 movq %r8,TF_R8(%rsp)
183 movq %r9,TF_R9(%rsp)
184 movq %rax,TF_RAX(%rsp)
185 movq %rbx,TF_RBX(%rsp)
186 movq %rbp,TF_RBP(%rsp)
187 movq %r10,TF_R10(%rsp)
188 movq %r11,TF_R11(%rsp)
189 movq %r12,TF_R12(%rsp)
190 movq %r13,TF_R13(%rsp)
191 movq %r14,TF_R14(%rsp)
192 movq %r15,TF_R15(%rsp)
193 movl $TF_HASSEGS,TF_FLAGS(%rsp)
194 FAKE_MCOUNT(TF_RIP(%rsp))
195 #ifdef KDTRACE_HOOKS
196 /*
197 * DTrace Function Boundary Trace (fbt) probes are triggered
198 * by int3 (0xcc) which causes the #BP (T_BPTFLT) breakpoint
199 * interrupt. For all other trap types, just handle them in
200 * the usual way.
201 */
202 cmpl $T_BPTFLT,TF_TRAPNO(%rsp)
203 jne calltrap
204
205 /* Check if there is no DTrace hook registered. */
206 cmpq $0,dtrace_invop_jump_addr
207 je calltrap
208
209 /*
210 * Set our jump address for the jump back in the event that
211 * the breakpoint wasn't caused by DTrace at all.
212 */
213 movq $calltrap,dtrace_invop_calltrap_addr(%rip)
214
215 /* Jump to the code hooked in by DTrace. */
216 movq dtrace_invop_jump_addr,%rax
217 jmpq *dtrace_invop_jump_addr
218 #endif
219 .globl calltrap
220 .type calltrap,@function
221 calltrap:
222 movq %rsp,%rdi
223 call trap
224 MEXITCOUNT
225 jmp doreti /* Handle any pending ASTs */
226
227 /*
228 * alltraps_noen entry point. Unlike alltraps above, we want to
229 * leave the interrupts disabled. This corresponds to
230 * SDT_SYS386IGT on the i386 port.
231 */
232 SUPERALIGN_TEXT
233 .globl alltraps_noen
234 .type alltraps_noen,@function
235 alltraps_noen:
236 movq %rdi,TF_RDI(%rsp)
237 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
238 jz 1f /* already running with kernel GS.base */
239 swapgs
240 movq PCPU(CURPCB),%rdi
241 movb $0,PCB_FULL_IRET(%rdi)
242 1: movw %fs,TF_FS(%rsp)
243 movw %gs,TF_GS(%rsp)
244 movw %es,TF_ES(%rsp)
245 movw %ds,TF_DS(%rsp)
246 jmp alltraps_pushregs_no_rdi
247
248 IDTVEC(dblfault)
249 subq $TF_ERR,%rsp
250 movl $T_DOUBLEFLT,TF_TRAPNO(%rsp)
251 movq $0,TF_ADDR(%rsp)
252 movq $0,TF_ERR(%rsp)
253 movq %rdi,TF_RDI(%rsp)
254 movq %rsi,TF_RSI(%rsp)
255 movq %rdx,TF_RDX(%rsp)
256 movq %rcx,TF_RCX(%rsp)
257 movq %r8,TF_R8(%rsp)
258 movq %r9,TF_R9(%rsp)
259 movq %rax,TF_RAX(%rsp)
260 movq %rbx,TF_RBX(%rsp)
261 movq %rbp,TF_RBP(%rsp)
262 movq %r10,TF_R10(%rsp)
263 movq %r11,TF_R11(%rsp)
264 movq %r12,TF_R12(%rsp)
265 movq %r13,TF_R13(%rsp)
266 movq %r14,TF_R14(%rsp)
267 movq %r15,TF_R15(%rsp)
268 movw %fs,TF_FS(%rsp)
269 movw %gs,TF_GS(%rsp)
270 movw %es,TF_ES(%rsp)
271 movw %ds,TF_DS(%rsp)
272 movl $TF_HASSEGS,TF_FLAGS(%rsp)
273 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
274 jz 1f /* already running with kernel GS.base */
275 swapgs
276 1:
277 movq %rsp,%rdi
278 call dblfault_handler
279 2:
280 hlt
281 jmp 2b
282
283 IDTVEC(page)
284 subq $TF_ERR,%rsp
285 movl $T_PAGEFLT,TF_TRAPNO(%rsp)
286 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
287 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
288 jz 1f /* already running with kernel GS.base */
289 swapgs
290 movq PCPU(CURPCB),%rdi
291 movb $0,PCB_FULL_IRET(%rdi)
292 1: movq %cr2,%rdi /* preserve %cr2 before .. */
293 movq %rdi,TF_ADDR(%rsp) /* enabling interrupts. */
294 movw %fs,TF_FS(%rsp)
295 movw %gs,TF_GS(%rsp)
296 movw %es,TF_ES(%rsp)
297 movw %ds,TF_DS(%rsp)
298 testl $PSL_I,TF_RFLAGS(%rsp)
299 jz alltraps_pushregs_no_rdi
300 sti
301 jmp alltraps_pushregs_no_rdi
302
303 /*
304 * We have to special-case this one. If we get a trap in doreti() at
305 * the iretq stage, we'll reenter with the wrong gs state. We'll have
306 * to do a special the swapgs in this case even coming from the kernel.
307 * XXX linux has a trap handler for their equivalent of load_gs().
308 */
309 IDTVEC(prot)
310 subq $TF_ERR,%rsp
311 movl $T_PROTFLT,TF_TRAPNO(%rsp)
312 movq $0,TF_ADDR(%rsp)
313 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
314 leaq doreti_iret(%rip),%rdi
315 cmpq %rdi,TF_RIP(%rsp)
316 je 1f /* kernel but with user gsbase!! */
317 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
318 jz 2f /* already running with kernel GS.base */
319 1: swapgs
320 2: movq PCPU(CURPCB),%rdi
321 movb $1,PCB_FULL_IRET(%rdi) /* always full iret from GPF */
322 movw %fs,TF_FS(%rsp)
323 movw %gs,TF_GS(%rsp)
324 movw %es,TF_ES(%rsp)
325 movw %ds,TF_DS(%rsp)
326 testl $PSL_I,TF_RFLAGS(%rsp)
327 jz alltraps_pushregs_no_rdi
328 sti
329 jmp alltraps_pushregs_no_rdi
330
331 /*
332 * Fast syscall entry point. We enter here with just our new %cs/%ss set,
333 * and the new privilige level. We are still running on the old user stack
334 * pointer. We have to juggle a few things around to find our stack etc.
335 * swapgs gives us access to our PCPU space only.
336 */
337 IDTVEC(fast_syscall)
338 swapgs
339 movq %rsp,PCPU(SCRATCH_RSP)
340 movq PCPU(RSP0),%rsp
341 /* Now emulate a trapframe. Make the 8 byte alignment odd for call. */
342 subq $TF_SIZE,%rsp
343 /* defer TF_RSP till we have a spare register */
344 movq %r11,TF_RFLAGS(%rsp)
345 movq %rcx,TF_RIP(%rsp) /* %rcx original value is in %r10 */
346 movq PCPU(SCRATCH_RSP),%r11 /* %r11 already saved */
347 movq %r11,TF_RSP(%rsp) /* user stack pointer */
348 movw %fs,TF_FS(%rsp)
349 movw %gs,TF_GS(%rsp)
350 movw %es,TF_ES(%rsp)
351 movw %ds,TF_DS(%rsp)
352 movq PCPU(CURPCB),%r11
353 movb $0,PCB_FULL_IRET(%r11)
354 sti
355 movq $KUDSEL,TF_SS(%rsp)
356 movq $KUCSEL,TF_CS(%rsp)
357 movq $2,TF_ERR(%rsp)
358 movq %rdi,TF_RDI(%rsp) /* arg 1 */
359 movq %rsi,TF_RSI(%rsp) /* arg 2 */
360 movq %rdx,TF_RDX(%rsp) /* arg 3 */
361 movq %r10,TF_RCX(%rsp) /* arg 4 */
362 movq %r8,TF_R8(%rsp) /* arg 5 */
363 movq %r9,TF_R9(%rsp) /* arg 6 */
364 movq %rax,TF_RAX(%rsp) /* syscall number */
365 movq %rbx,TF_RBX(%rsp) /* C preserved */
366 movq %rbp,TF_RBP(%rsp) /* C preserved */
367 movq %r12,TF_R12(%rsp) /* C preserved */
368 movq %r13,TF_R13(%rsp) /* C preserved */
369 movq %r14,TF_R14(%rsp) /* C preserved */
370 movq %r15,TF_R15(%rsp) /* C preserved */
371 movl $TF_HASSEGS,TF_FLAGS(%rsp)
372 FAKE_MCOUNT(TF_RIP(%rsp))
373 movq %rsp,%rdi
374 call syscall
375 movq PCPU(CURPCB),%rax
376 andq $~PCB_FULLCTX,PCB_FLAGS(%rax)
377 MEXITCOUNT
378 jmp doreti
379
380 /*
381 * Here for CYA insurance, in case a "syscall" instruction gets
382 * issued from 32 bit compatability mode. MSR_CSTAR has to point
383 * to *something* if EFER_SCE is enabled.
384 */
385 IDTVEC(fast_syscall32)
386 sysret
387
388 /*
389 * NMI handling is special.
390 *
391 * First, NMIs do not respect the state of the processor's RFLAGS.IF
392 * bit. The NMI handler may be entered at any time, including when
393 * the processor is in a critical section with RFLAGS.IF == 0.
394 * The processor's GS.base value could be invalid on entry to the
395 * handler.
396 *
397 * Second, the processor treats NMIs specially, blocking further NMIs
398 * until an 'iretq' instruction is executed. We thus need to execute
399 * the NMI handler with interrupts disabled, to prevent a nested interrupt
400 * from executing an 'iretq' instruction and inadvertently taking the
401 * processor out of NMI mode.
402 *
403 * Third, the NMI handler runs on its own stack (tss_ist2). The canonical
404 * GS.base value for the processor is stored just above the bottom of its
405 * NMI stack. For NMIs taken from kernel mode, the current value in
406 * the processor's GS.base is saved at entry to C-preserved register %r12,
407 * the canonical value for GS.base is then loaded into the processor, and
408 * the saved value is restored at exit time. For NMIs taken from user mode,
409 * the cheaper 'SWAPGS' instructions are used for swapping GS.base.
410 */
411
412 IDTVEC(nmi)
413 subq $TF_RIP,%rsp
414 movl $(T_NMI),TF_TRAPNO(%rsp)
415 movq $0,TF_ADDR(%rsp)
416 movq $0,TF_ERR(%rsp)
417 movq %rdi,TF_RDI(%rsp)
418 movq %rsi,TF_RSI(%rsp)
419 movq %rdx,TF_RDX(%rsp)
420 movq %rcx,TF_RCX(%rsp)
421 movq %r8,TF_R8(%rsp)
422 movq %r9,TF_R9(%rsp)
423 movq %rax,TF_RAX(%rsp)
424 movq %rbx,TF_RBX(%rsp)
425 movq %rbp,TF_RBP(%rsp)
426 movq %r10,TF_R10(%rsp)
427 movq %r11,TF_R11(%rsp)
428 movq %r12,TF_R12(%rsp)
429 movq %r13,TF_R13(%rsp)
430 movq %r14,TF_R14(%rsp)
431 movq %r15,TF_R15(%rsp)
432 movw %fs,TF_FS(%rsp)
433 movw %gs,TF_GS(%rsp)
434 movw %es,TF_ES(%rsp)
435 movw %ds,TF_DS(%rsp)
436 movl $TF_HASSEGS,TF_FLAGS(%rsp)
437 xorl %ebx,%ebx
438 testb $SEL_RPL_MASK,TF_CS(%rsp)
439 jnz nmi_fromuserspace
440 /*
441 * We've interrupted the kernel. Preserve GS.base in %r12.
442 */
443 movl $MSR_GSBASE,%ecx
444 rdmsr
445 movq %rax,%r12
446 shlq $32,%rdx
447 orq %rdx,%r12
448 /* Retrieve and load the canonical value for GS.base. */
449 movq TF_SIZE(%rsp),%rdx
450 movl %edx,%eax
451 shrq $32,%rdx
452 wrmsr
453 jmp nmi_calltrap
454 nmi_fromuserspace:
455 incl %ebx
456 swapgs
457 /* Note: this label is also used by ddb and gdb: */
458 nmi_calltrap:
459 FAKE_MCOUNT(TF_RIP(%rsp))
460 movq %rsp,%rdi
461 call trap
462 MEXITCOUNT
463 #ifdef HWPMC_HOOKS
464 /*
465 * Capture a userspace callchain if needed.
466 *
467 * - Check if the current trap was from user mode.
468 * - Check if the current thread is valid.
469 * - Check if the thread requires a user call chain to be
470 * captured.
471 *
472 * We are still in NMI mode at this point.
473 */
474 testl %ebx,%ebx
475 jz nocallchain /* not from userspace */
476 movq PCPU(CURTHREAD),%rax
477 orq %rax,%rax /* curthread present? */
478 jz nocallchain
479 testl $TDP_CALLCHAIN,TD_PFLAGS(%rax) /* flagged for capture? */
480 jz nocallchain
481 /*
482 * A user callchain is to be captured, so:
483 * - Move execution to the regular kernel stack, to allow for
484 * nested NMI interrupts.
485 * - Take the processor out of "NMI" mode by faking an "iret".
486 * - Enable interrupts, so that copyin() can work.
487 */
488 movq %rsp,%rsi /* source stack pointer */
489 movq $TF_SIZE,%rcx
490 movq PCPU(RSP0),%rdx
491 subq %rcx,%rdx
492 movq %rdx,%rdi /* destination stack pointer */
493
494 shrq $3,%rcx /* trap frame size in long words */
495 cld
496 rep
497 movsq /* copy trapframe */
498
499 movl %ss,%eax
500 pushq %rax /* tf_ss */
501 pushq %rdx /* tf_rsp (on kernel stack) */
502 pushfq /* tf_rflags */
503 movl %cs,%eax
504 pushq %rax /* tf_cs */
505 pushq $outofnmi /* tf_rip */
506 iretq
507 outofnmi:
508 /*
509 * At this point the processor has exited NMI mode and is running
510 * with interrupts turned off on the normal kernel stack.
511 *
512 * If a pending NMI gets recognized at or after this point, it
513 * will cause a kernel callchain to be traced.
514 *
515 * We turn interrupts back on, and call the user callchain capture hook.
516 */
517 movq pmc_hook,%rax
518 orq %rax,%rax
519 jz nocallchain
520 movq PCPU(CURTHREAD),%rdi /* thread */
521 movq $PMC_FN_USER_CALLCHAIN,%rsi /* command */
522 movq %rsp,%rdx /* frame */
523 sti
524 call *%rax
525 cli
526 nocallchain:
527 #endif
528 testl %ebx,%ebx
529 jnz doreti_exit
530 nmi_kernelexit:
531 /*
532 * Put back the preserved MSR_GSBASE value.
533 */
534 movl $MSR_GSBASE,%ecx
535 movq %r12,%rdx
536 movl %edx,%eax
537 shrq $32,%rdx
538 wrmsr
539 nmi_restoreregs:
540 movq TF_RDI(%rsp),%rdi
541 movq TF_RSI(%rsp),%rsi
542 movq TF_RDX(%rsp),%rdx
543 movq TF_RCX(%rsp),%rcx
544 movq TF_R8(%rsp),%r8
545 movq TF_R9(%rsp),%r9
546 movq TF_RAX(%rsp),%rax
547 movq TF_RBX(%rsp),%rbx
548 movq TF_RBP(%rsp),%rbp
549 movq TF_R10(%rsp),%r10
550 movq TF_R11(%rsp),%r11
551 movq TF_R12(%rsp),%r12
552 movq TF_R13(%rsp),%r13
553 movq TF_R14(%rsp),%r14
554 movq TF_R15(%rsp),%r15
555 addq $TF_RIP,%rsp
556 jmp doreti_iret
557
558 ENTRY(fork_trampoline)
559 movq %r12,%rdi /* function */
560 movq %rbx,%rsi /* arg1 */
561 movq %rsp,%rdx /* trapframe pointer */
562 call fork_exit
563 MEXITCOUNT
564 jmp doreti /* Handle any ASTs */
565
566 /*
567 * To efficiently implement classification of trap and interrupt handlers
568 * for profiling, there must be only trap handlers between the labels btrap
569 * and bintr, and only interrupt handlers between the labels bintr and
570 * eintr. This is implemented (partly) by including files that contain
571 * some of the handlers. Before including the files, set up a normal asm
572 * environment so that the included files doen't need to know that they are
573 * included.
574 */
575
576 #ifdef COMPAT_FREEBSD32
577 .data
578 .p2align 4
579 .text
580 SUPERALIGN_TEXT
581
582 #include <amd64/ia32/ia32_exception.S>
583 #endif
584
585 .data
586 .p2align 4
587 .text
588 SUPERALIGN_TEXT
589 MCOUNT_LABEL(bintr)
590
591 #include <amd64/amd64/apic_vector.S>
592
593 #ifdef DEV_ATPIC
594 .data
595 .p2align 4
596 .text
597 SUPERALIGN_TEXT
598
599 #include <amd64/isa/atpic_vector.S>
600 #endif
601
602 .text
603 MCOUNT_LABEL(eintr)
604
605 /*
606 * void doreti(struct trapframe)
607 *
608 * Handle return from interrupts, traps and syscalls.
609 */
610 .text
611 SUPERALIGN_TEXT
612 .type doreti,@function
613 doreti:
614 FAKE_MCOUNT($bintr) /* init "from" bintr -> doreti */
615 /*
616 * Check if ASTs can be handled now.
617 */
618 testb $SEL_RPL_MASK,TF_CS(%rsp) /* are we returning to user mode? */
619 jz doreti_exit /* can't handle ASTs now if not */
620
621 doreti_ast:
622 /*
623 * Check for ASTs atomically with returning. Disabling CPU
624 * interrupts provides sufficient locking eve in the SMP case,
625 * since we will be informed of any new ASTs by an IPI.
626 */
627 cli
628 movq PCPU(CURTHREAD),%rax
629 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
630 je doreti_exit
631 sti
632 movq %rsp,%rdi /* pass a pointer to the trapframe */
633 call ast
634 jmp doreti_ast
635
636 /*
637 * doreti_exit: pop registers, iret.
638 *
639 * The segment register pop is a special case, since it may
640 * fault if (for example) a sigreturn specifies bad segment
641 * registers. The fault is handled in trap.c.
642 */
643 doreti_exit:
644 MEXITCOUNT
645 movq PCPU(CURTHREAD),%r8
646 movq TD_PCB(%r8),%r8
647
648 /*
649 * Do not reload segment registers for kernel.
650 * Since we do not reload segments registers with sane
651 * values on kernel entry, descriptors referenced by
652 * segments registers might be not valid. This is fatal
653 * for user mode, but is not a problem for the kernel.
654 */
655 testb $SEL_RPL_MASK,TF_CS(%rsp)
656 jz ld_regs
657 cmpb $0,PCB_FULL_IRET(%r8)
658 je ld_regs
659 testl $TF_HASSEGS,TF_FLAGS(%rsp)
660 je set_segs
661
662 do_segs:
663 /* Restore %fs and fsbase */
664 movw TF_FS(%rsp),%ax
665 .globl ld_fs
666 ld_fs:
667 movw %ax,%fs
668 cmpw $KUF32SEL,%ax
669 jne 1f
670 movl $MSR_FSBASE,%ecx
671 movl PCB_FSBASE(%r8),%eax
672 movl PCB_FSBASE+4(%r8),%edx
673 .globl ld_fsbase
674 ld_fsbase:
675 wrmsr
676 1:
677 /* Restore %gs and gsbase */
678 movw TF_GS(%rsp),%si
679 pushfq
680 cli
681 movl $MSR_GSBASE,%ecx
682 rdmsr
683 .globl ld_gs
684 ld_gs:
685 movw %si,%gs
686 wrmsr
687 popfq
688 cmpw $KUG32SEL,%si
689 jne 1f
690 movl $MSR_KGSBASE,%ecx
691 movl PCB_GSBASE(%r8),%eax
692 movl PCB_GSBASE+4(%r8),%edx
693 .globl ld_gsbase
694 ld_gsbase:
695 wrmsr
696 1:
697 .globl ld_es
698 ld_es:
699 movw TF_ES(%rsp),%es
700 .globl ld_ds
701 ld_ds:
702 movw TF_DS(%rsp),%ds
703 ld_regs:
704 movq TF_RDI(%rsp),%rdi
705 movq TF_RSI(%rsp),%rsi
706 movq TF_RDX(%rsp),%rdx
707 movq TF_RCX(%rsp),%rcx
708 movq TF_R8(%rsp),%r8
709 movq TF_R9(%rsp),%r9
710 movq TF_RAX(%rsp),%rax
711 movq TF_RBX(%rsp),%rbx
712 movq TF_RBP(%rsp),%rbp
713 movq TF_R10(%rsp),%r10
714 movq TF_R11(%rsp),%r11
715 movq TF_R12(%rsp),%r12
716 movq TF_R13(%rsp),%r13
717 movq TF_R14(%rsp),%r14
718 movq TF_R15(%rsp),%r15
719 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
720 jz 1f /* keep running with kernel GS.base */
721 cli
722 swapgs
723 1:
724 addq $TF_RIP,%rsp /* skip over tf_err, tf_trapno */
725 .globl doreti_iret
726 doreti_iret:
727 iretq
728
729 set_segs:
730 movw $KUDSEL,%ax
731 movw %ax,TF_DS(%rsp)
732 movw %ax,TF_ES(%rsp)
733 movw $KUF32SEL,TF_FS(%rsp)
734 movw $KUG32SEL,TF_GS(%rsp)
735 jmp do_segs
736
737 /*
738 * doreti_iret_fault. Alternative return code for
739 * the case where we get a fault in the doreti_exit code
740 * above. trap() (amd64/amd64/trap.c) catches this specific
741 * case, sends the process a signal and continues in the
742 * corresponding place in the code below.
743 */
744 ALIGN_TEXT
745 .globl doreti_iret_fault
746 doreti_iret_fault:
747 subq $TF_RIP,%rsp /* space including tf_err, tf_trapno */
748 testl $PSL_I,TF_RFLAGS(%rsp)
749 jz 1f
750 sti
751 1:
752 movw %fs,TF_FS(%rsp)
753 movw %gs,TF_GS(%rsp)
754 movw %es,TF_ES(%rsp)
755 movw %ds,TF_DS(%rsp)
756 movl $TF_HASSEGS,TF_FLAGS(%rsp)
757 movq %rdi,TF_RDI(%rsp)
758 movq %rsi,TF_RSI(%rsp)
759 movq %rdx,TF_RDX(%rsp)
760 movq %rcx,TF_RCX(%rsp)
761 movq %r8,TF_R8(%rsp)
762 movq %r9,TF_R9(%rsp)
763 movq %rax,TF_RAX(%rsp)
764 movq %rbx,TF_RBX(%rsp)
765 movq %rbp,TF_RBP(%rsp)
766 movq %r10,TF_R10(%rsp)
767 movq %r11,TF_R11(%rsp)
768 movq %r12,TF_R12(%rsp)
769 movq %r13,TF_R13(%rsp)
770 movq %r14,TF_R14(%rsp)
771 movq %r15,TF_R15(%rsp)
772 movl $T_PROTFLT,TF_TRAPNO(%rsp)
773 movq $0,TF_ERR(%rsp) /* XXX should be the error code */
774 movq $0,TF_ADDR(%rsp)
775 FAKE_MCOUNT(TF_RIP(%rsp))
776 jmp calltrap
777
778 ALIGN_TEXT
779 .globl ds_load_fault
780 ds_load_fault:
781 movl $T_PROTFLT,TF_TRAPNO(%rsp)
782 movq %rsp,%rdi
783 call trap
784 movw $KUDSEL,TF_DS(%rsp)
785 jmp doreti
786
787 ALIGN_TEXT
788 .globl es_load_fault
789 es_load_fault:
790 movl $T_PROTFLT,TF_TRAPNO(%rsp)
791 movq %rsp,%rdi
792 call trap
793 movw $KUDSEL,TF_ES(%rsp)
794 jmp doreti
795
796 ALIGN_TEXT
797 .globl fs_load_fault
798 fs_load_fault:
799 movl $T_PROTFLT,TF_TRAPNO(%rsp)
800 movq %rsp,%rdi
801 call trap
802 movw $KUF32SEL,TF_FS(%rsp)
803 jmp doreti
804
805 ALIGN_TEXT
806 .globl gs_load_fault
807 gs_load_fault:
808 popfq
809 movl $T_PROTFLT,TF_TRAPNO(%rsp)
810 movq %rsp,%rdi
811 call trap
812 movw $KUG32SEL,TF_GS(%rsp)
813 jmp doreti
814
815 ALIGN_TEXT
816 .globl fsbase_load_fault
817 fsbase_load_fault:
818 movl $T_PROTFLT,TF_TRAPNO(%rsp)
819 movq %rsp,%rdi
820 call trap
821 movq PCPU(CURTHREAD),%r8
822 movq TD_PCB(%r8),%r8
823 movq $0,PCB_FSBASE(%r8)
824 jmp doreti
825
826 ALIGN_TEXT
827 .globl gsbase_load_fault
828 gsbase_load_fault:
829 movl $T_PROTFLT,TF_TRAPNO(%rsp)
830 movq %rsp,%rdi
831 call trap
832 movq PCPU(CURTHREAD),%r8
833 movq TD_PCB(%r8),%r8
834 movq $0,PCB_GSBASE(%r8)
835 jmp doreti
836
837 #ifdef HWPMC_HOOKS
838 ENTRY(end_exceptions)
839 #endif
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