1 /*-
2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
4 * Copyright (c) 2007 The FreeBSD Foundation
5 * All rights reserved.
6 *
7 * Portions of this software were developed by A. Joseph Koshy under
8 * sponsorship from the FreeBSD Foundation and Google, Inc.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $FreeBSD: releng/8.2/sys/amd64/amd64/exception.S 216457 2010-12-15 15:23:25Z kib $
35 */
36
37 #include "opt_atpic.h"
38 #include "opt_compat.h"
39 #include "opt_hwpmc_hooks.h"
40 #include "opt_kdtrace.h"
41
42 #include <machine/asmacros.h>
43 #include <machine/psl.h>
44 #include <machine/trap.h>
45 #include <machine/specialreg.h>
46
47 #include "assym.s"
48
49 #ifdef KDTRACE_HOOKS
50 .bss
51 .globl dtrace_invop_jump_addr
52 .align 8
53 .type dtrace_invop_jump_addr,@object
54 .size dtrace_invop_jump_addr,8
55 dtrace_invop_jump_addr:
56 .zero 8
57 .globl dtrace_invop_calltrap_addr
58 .align 8
59 .type dtrace_invop_calltrap_addr,@object
60 .size dtrace_invop_calltrap_addr,8
61 dtrace_invop_calltrap_addr:
62 .zero 8
63 #endif
64 .text
65 #ifdef HWPMC_HOOKS
66 ENTRY(start_exceptions)
67 #endif
68
69 /*****************************************************************************/
70 /* Trap handling */
71 /*****************************************************************************/
72 /*
73 * Trap and fault vector routines.
74 *
75 * All traps are 'interrupt gates', SDT_SYSIGT. An interrupt gate pushes
76 * state on the stack but also disables interrupts. This is important for
77 * us for the use of the swapgs instruction. We cannot be interrupted
78 * until the GS.base value is correct. For most traps, we automatically
79 * then enable interrupts if the interrupted context had them enabled.
80 * This is equivalent to the i386 port's use of SDT_SYS386TGT.
81 *
82 * The cpu will push a certain amount of state onto the kernel stack for
83 * the current process. See amd64/include/frame.h.
84 * This includes the current RFLAGS (status register, which includes
85 * the interrupt disable state prior to the trap), the code segment register,
86 * and the return instruction pointer are pushed by the cpu. The cpu
87 * will also push an 'error' code for certain traps. We push a dummy
88 * error code for those traps where the cpu doesn't in order to maintain
89 * a consistent frame. We also push a contrived 'trap number'.
90 *
91 * The cpu does not push the general registers, we must do that, and we
92 * must restore them prior to calling 'iret'. The cpu adjusts the %cs and
93 * %ss segment registers, but does not mess with %ds, %es, or %fs. Thus we
94 * must load them with appropriate values for supervisor mode operation.
95 */
96
97 MCOUNT_LABEL(user)
98 MCOUNT_LABEL(btrap)
99
100 /* Traps that we leave interrupts disabled for.. */
101 #define TRAP_NOEN(a) \
102 subq $TF_RIP,%rsp; \
103 movl $(a),TF_TRAPNO(%rsp) ; \
104 movq $0,TF_ADDR(%rsp) ; \
105 movq $0,TF_ERR(%rsp) ; \
106 jmp alltraps_noen
107 IDTVEC(dbg)
108 TRAP_NOEN(T_TRCTRAP)
109 IDTVEC(bpt)
110 TRAP_NOEN(T_BPTFLT)
111
112 /* Regular traps; The cpu does not supply tf_err for these. */
113 #define TRAP(a) \
114 subq $TF_RIP,%rsp; \
115 movl $(a),TF_TRAPNO(%rsp) ; \
116 movq $0,TF_ADDR(%rsp) ; \
117 movq $0,TF_ERR(%rsp) ; \
118 jmp alltraps
119 IDTVEC(div)
120 TRAP(T_DIVIDE)
121 IDTVEC(ofl)
122 TRAP(T_OFLOW)
123 IDTVEC(bnd)
124 TRAP(T_BOUND)
125 IDTVEC(ill)
126 TRAP(T_PRIVINFLT)
127 IDTVEC(dna)
128 TRAP(T_DNA)
129 IDTVEC(fpusegm)
130 TRAP(T_FPOPFLT)
131 IDTVEC(mchk)
132 TRAP(T_MCHK)
133 IDTVEC(rsvd)
134 TRAP(T_RESERVED)
135 IDTVEC(fpu)
136 TRAP(T_ARITHTRAP)
137 IDTVEC(xmm)
138 TRAP(T_XMMFLT)
139
140 /* This group of traps have tf_err already pushed by the cpu */
141 #define TRAP_ERR(a) \
142 subq $TF_ERR,%rsp; \
143 movl $(a),TF_TRAPNO(%rsp) ; \
144 movq $0,TF_ADDR(%rsp) ; \
145 jmp alltraps
146 IDTVEC(tss)
147 TRAP_ERR(T_TSSFLT)
148 IDTVEC(missing)
149 TRAP_ERR(T_SEGNPFLT)
150 IDTVEC(stk)
151 TRAP_ERR(T_STKFLT)
152 IDTVEC(align)
153 TRAP_ERR(T_ALIGNFLT)
154
155 /*
156 * alltraps entry point. Use swapgs if this is the first time in the
157 * kernel from userland. Reenable interrupts if they were enabled
158 * before the trap. This approximates SDT_SYS386TGT on the i386 port.
159 */
160 SUPERALIGN_TEXT
161 .globl alltraps
162 .type alltraps,@function
163 alltraps:
164 movq %rdi,TF_RDI(%rsp)
165 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
166 jz alltraps_testi /* already running with kernel GS.base */
167 swapgs
168 movq PCPU(CURPCB),%rdi
169 movb $0,PCB_FULL_IRET(%rdi)
170 movw %fs,TF_FS(%rsp)
171 movw %gs,TF_GS(%rsp)
172 movw %es,TF_ES(%rsp)
173 movw %ds,TF_DS(%rsp)
174 alltraps_testi:
175 testl $PSL_I,TF_RFLAGS(%rsp)
176 jz alltraps_pushregs_no_rdi
177 sti
178 alltraps_pushregs_no_rdi:
179 movq %rsi,TF_RSI(%rsp)
180 movq %rdx,TF_RDX(%rsp)
181 movq %rcx,TF_RCX(%rsp)
182 movq %r8,TF_R8(%rsp)
183 movq %r9,TF_R9(%rsp)
184 movq %rax,TF_RAX(%rsp)
185 movq %rbx,TF_RBX(%rsp)
186 movq %rbp,TF_RBP(%rsp)
187 movq %r10,TF_R10(%rsp)
188 movq %r11,TF_R11(%rsp)
189 movq %r12,TF_R12(%rsp)
190 movq %r13,TF_R13(%rsp)
191 movq %r14,TF_R14(%rsp)
192 movq %r15,TF_R15(%rsp)
193 movl $TF_HASSEGS,TF_FLAGS(%rsp)
194 cld
195 FAKE_MCOUNT(TF_RIP(%rsp))
196 #ifdef KDTRACE_HOOKS
197 /*
198 * DTrace Function Boundary Trace (fbt) probes are triggered
199 * by int3 (0xcc) which causes the #BP (T_BPTFLT) breakpoint
200 * interrupt. For all other trap types, just handle them in
201 * the usual way.
202 */
203 cmpl $T_BPTFLT,TF_TRAPNO(%rsp)
204 jne calltrap
205
206 /* Check if there is no DTrace hook registered. */
207 cmpq $0,dtrace_invop_jump_addr
208 je calltrap
209
210 /*
211 * Set our jump address for the jump back in the event that
212 * the breakpoint wasn't caused by DTrace at all.
213 */
214 movq $calltrap,dtrace_invop_calltrap_addr(%rip)
215
216 /* Jump to the code hooked in by DTrace. */
217 movq dtrace_invop_jump_addr,%rax
218 jmpq *dtrace_invop_jump_addr
219 #endif
220 .globl calltrap
221 .type calltrap,@function
222 calltrap:
223 movq %rsp,%rdi
224 call trap
225 MEXITCOUNT
226 jmp doreti /* Handle any pending ASTs */
227
228 /*
229 * alltraps_noen entry point. Unlike alltraps above, we want to
230 * leave the interrupts disabled. This corresponds to
231 * SDT_SYS386IGT on the i386 port.
232 */
233 SUPERALIGN_TEXT
234 .globl alltraps_noen
235 .type alltraps_noen,@function
236 alltraps_noen:
237 movq %rdi,TF_RDI(%rsp)
238 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
239 jz 1f /* already running with kernel GS.base */
240 swapgs
241 movq PCPU(CURPCB),%rdi
242 movb $0,PCB_FULL_IRET(%rdi)
243 1: movw %fs,TF_FS(%rsp)
244 movw %gs,TF_GS(%rsp)
245 movw %es,TF_ES(%rsp)
246 movw %ds,TF_DS(%rsp)
247 jmp alltraps_pushregs_no_rdi
248
249 IDTVEC(dblfault)
250 subq $TF_ERR,%rsp
251 movl $T_DOUBLEFLT,TF_TRAPNO(%rsp)
252 movq $0,TF_ADDR(%rsp)
253 movq $0,TF_ERR(%rsp)
254 movq %rdi,TF_RDI(%rsp)
255 movq %rsi,TF_RSI(%rsp)
256 movq %rdx,TF_RDX(%rsp)
257 movq %rcx,TF_RCX(%rsp)
258 movq %r8,TF_R8(%rsp)
259 movq %r9,TF_R9(%rsp)
260 movq %rax,TF_RAX(%rsp)
261 movq %rbx,TF_RBX(%rsp)
262 movq %rbp,TF_RBP(%rsp)
263 movq %r10,TF_R10(%rsp)
264 movq %r11,TF_R11(%rsp)
265 movq %r12,TF_R12(%rsp)
266 movq %r13,TF_R13(%rsp)
267 movq %r14,TF_R14(%rsp)
268 movq %r15,TF_R15(%rsp)
269 movw %fs,TF_FS(%rsp)
270 movw %gs,TF_GS(%rsp)
271 movw %es,TF_ES(%rsp)
272 movw %ds,TF_DS(%rsp)
273 movl $TF_HASSEGS,TF_FLAGS(%rsp)
274 cld
275 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
276 jz 1f /* already running with kernel GS.base */
277 swapgs
278 1:
279 movq %rsp,%rdi
280 call dblfault_handler
281 2:
282 hlt
283 jmp 2b
284
285 IDTVEC(page)
286 subq $TF_ERR,%rsp
287 movl $T_PAGEFLT,TF_TRAPNO(%rsp)
288 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
289 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
290 jz 1f /* already running with kernel GS.base */
291 swapgs
292 movq PCPU(CURPCB),%rdi
293 movb $0,PCB_FULL_IRET(%rdi)
294 1: movq %cr2,%rdi /* preserve %cr2 before .. */
295 movq %rdi,TF_ADDR(%rsp) /* enabling interrupts. */
296 movw %fs,TF_FS(%rsp)
297 movw %gs,TF_GS(%rsp)
298 movw %es,TF_ES(%rsp)
299 movw %ds,TF_DS(%rsp)
300 testl $PSL_I,TF_RFLAGS(%rsp)
301 jz alltraps_pushregs_no_rdi
302 sti
303 jmp alltraps_pushregs_no_rdi
304
305 /*
306 * We have to special-case this one. If we get a trap in doreti() at
307 * the iretq stage, we'll reenter with the wrong gs state. We'll have
308 * to do a special the swapgs in this case even coming from the kernel.
309 * XXX linux has a trap handler for their equivalent of load_gs().
310 */
311 IDTVEC(prot)
312 subq $TF_ERR,%rsp
313 movl $T_PROTFLT,TF_TRAPNO(%rsp)
314 movq $0,TF_ADDR(%rsp)
315 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
316 leaq doreti_iret(%rip),%rdi
317 cmpq %rdi,TF_RIP(%rsp)
318 je 1f /* kernel but with user gsbase!! */
319 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
320 jz 2f /* already running with kernel GS.base */
321 1: swapgs
322 2: movq PCPU(CURPCB),%rdi
323 movb $1,PCB_FULL_IRET(%rdi) /* always full iret from GPF */
324 movw %fs,TF_FS(%rsp)
325 movw %gs,TF_GS(%rsp)
326 movw %es,TF_ES(%rsp)
327 movw %ds,TF_DS(%rsp)
328 testl $PSL_I,TF_RFLAGS(%rsp)
329 jz alltraps_pushregs_no_rdi
330 sti
331 jmp alltraps_pushregs_no_rdi
332
333 /*
334 * Fast syscall entry point. We enter here with just our new %cs/%ss set,
335 * and the new privilige level. We are still running on the old user stack
336 * pointer. We have to juggle a few things around to find our stack etc.
337 * swapgs gives us access to our PCPU space only.
338 */
339 IDTVEC(fast_syscall)
340 swapgs
341 movq %rsp,PCPU(SCRATCH_RSP)
342 movq PCPU(RSP0),%rsp
343 /* Now emulate a trapframe. Make the 8 byte alignment odd for call. */
344 subq $TF_SIZE,%rsp
345 /* defer TF_RSP till we have a spare register */
346 movq %r11,TF_RFLAGS(%rsp)
347 movq %rcx,TF_RIP(%rsp) /* %rcx original value is in %r10 */
348 movq PCPU(SCRATCH_RSP),%r11 /* %r11 already saved */
349 movq %r11,TF_RSP(%rsp) /* user stack pointer */
350 movw %fs,TF_FS(%rsp)
351 movw %gs,TF_GS(%rsp)
352 movw %es,TF_ES(%rsp)
353 movw %ds,TF_DS(%rsp)
354 movq PCPU(CURPCB),%r11
355 movb $0,PCB_FULL_IRET(%r11)
356 sti
357 movq $KUDSEL,TF_SS(%rsp)
358 movq $KUCSEL,TF_CS(%rsp)
359 movq $2,TF_ERR(%rsp)
360 movq %rdi,TF_RDI(%rsp) /* arg 1 */
361 movq %rsi,TF_RSI(%rsp) /* arg 2 */
362 movq %rdx,TF_RDX(%rsp) /* arg 3 */
363 movq %r10,TF_RCX(%rsp) /* arg 4 */
364 movq %r8,TF_R8(%rsp) /* arg 5 */
365 movq %r9,TF_R9(%rsp) /* arg 6 */
366 movq %rax,TF_RAX(%rsp) /* syscall number */
367 movq %rbx,TF_RBX(%rsp) /* C preserved */
368 movq %rbp,TF_RBP(%rsp) /* C preserved */
369 movq %r12,TF_R12(%rsp) /* C preserved */
370 movq %r13,TF_R13(%rsp) /* C preserved */
371 movq %r14,TF_R14(%rsp) /* C preserved */
372 movq %r15,TF_R15(%rsp) /* C preserved */
373 movl $TF_HASSEGS,TF_FLAGS(%rsp)
374 cld
375 FAKE_MCOUNT(TF_RIP(%rsp))
376 movq %rsp,%rdi
377 call syscall
378 movq PCPU(CURPCB),%rax
379 MEXITCOUNT
380 jmp doreti
381
382 /*
383 * Here for CYA insurance, in case a "syscall" instruction gets
384 * issued from 32 bit compatability mode. MSR_CSTAR has to point
385 * to *something* if EFER_SCE is enabled.
386 */
387 IDTVEC(fast_syscall32)
388 sysret
389
390 /*
391 * NMI handling is special.
392 *
393 * First, NMIs do not respect the state of the processor's RFLAGS.IF
394 * bit. The NMI handler may be entered at any time, including when
395 * the processor is in a critical section with RFLAGS.IF == 0.
396 * The processor's GS.base value could be invalid on entry to the
397 * handler.
398 *
399 * Second, the processor treats NMIs specially, blocking further NMIs
400 * until an 'iretq' instruction is executed. We thus need to execute
401 * the NMI handler with interrupts disabled, to prevent a nested interrupt
402 * from executing an 'iretq' instruction and inadvertently taking the
403 * processor out of NMI mode.
404 *
405 * Third, the NMI handler runs on its own stack (tss_ist2). The canonical
406 * GS.base value for the processor is stored just above the bottom of its
407 * NMI stack. For NMIs taken from kernel mode, the current value in
408 * the processor's GS.base is saved at entry to C-preserved register %r12,
409 * the canonical value for GS.base is then loaded into the processor, and
410 * the saved value is restored at exit time. For NMIs taken from user mode,
411 * the cheaper 'SWAPGS' instructions are used for swapping GS.base.
412 */
413
414 IDTVEC(nmi)
415 subq $TF_RIP,%rsp
416 movl $(T_NMI),TF_TRAPNO(%rsp)
417 movq $0,TF_ADDR(%rsp)
418 movq $0,TF_ERR(%rsp)
419 movq %rdi,TF_RDI(%rsp)
420 movq %rsi,TF_RSI(%rsp)
421 movq %rdx,TF_RDX(%rsp)
422 movq %rcx,TF_RCX(%rsp)
423 movq %r8,TF_R8(%rsp)
424 movq %r9,TF_R9(%rsp)
425 movq %rax,TF_RAX(%rsp)
426 movq %rbx,TF_RBX(%rsp)
427 movq %rbp,TF_RBP(%rsp)
428 movq %r10,TF_R10(%rsp)
429 movq %r11,TF_R11(%rsp)
430 movq %r12,TF_R12(%rsp)
431 movq %r13,TF_R13(%rsp)
432 movq %r14,TF_R14(%rsp)
433 movq %r15,TF_R15(%rsp)
434 movw %fs,TF_FS(%rsp)
435 movw %gs,TF_GS(%rsp)
436 movw %es,TF_ES(%rsp)
437 movw %ds,TF_DS(%rsp)
438 movl $TF_HASSEGS,TF_FLAGS(%rsp)
439 cld
440 xorl %ebx,%ebx
441 testb $SEL_RPL_MASK,TF_CS(%rsp)
442 jnz nmi_fromuserspace
443 /*
444 * We've interrupted the kernel. Preserve GS.base in %r12.
445 */
446 movl $MSR_GSBASE,%ecx
447 rdmsr
448 movq %rax,%r12
449 shlq $32,%rdx
450 orq %rdx,%r12
451 /* Retrieve and load the canonical value for GS.base. */
452 movq TF_SIZE(%rsp),%rdx
453 movl %edx,%eax
454 shrq $32,%rdx
455 wrmsr
456 jmp nmi_calltrap
457 nmi_fromuserspace:
458 incl %ebx
459 swapgs
460 /* Note: this label is also used by ddb and gdb: */
461 nmi_calltrap:
462 FAKE_MCOUNT(TF_RIP(%rsp))
463 movq %rsp,%rdi
464 call trap
465 MEXITCOUNT
466 #ifdef HWPMC_HOOKS
467 /*
468 * Capture a userspace callchain if needed.
469 *
470 * - Check if the current trap was from user mode.
471 * - Check if the current thread is valid.
472 * - Check if the thread requires a user call chain to be
473 * captured.
474 *
475 * We are still in NMI mode at this point.
476 */
477 testl %ebx,%ebx
478 jz nocallchain /* not from userspace */
479 movq PCPU(CURTHREAD),%rax
480 orq %rax,%rax /* curthread present? */
481 jz nocallchain
482 testl $TDP_CALLCHAIN,TD_PFLAGS(%rax) /* flagged for capture? */
483 jz nocallchain
484 /*
485 * A user callchain is to be captured, so:
486 * - Move execution to the regular kernel stack, to allow for
487 * nested NMI interrupts.
488 * - Take the processor out of "NMI" mode by faking an "iret".
489 * - Enable interrupts, so that copyin() can work.
490 */
491 movq %rsp,%rsi /* source stack pointer */
492 movq $TF_SIZE,%rcx
493 movq PCPU(RSP0),%rdx
494 subq %rcx,%rdx
495 movq %rdx,%rdi /* destination stack pointer */
496
497 shrq $3,%rcx /* trap frame size in long words */
498 cld
499 rep
500 movsq /* copy trapframe */
501
502 movl %ss,%eax
503 pushq %rax /* tf_ss */
504 pushq %rdx /* tf_rsp (on kernel stack) */
505 pushfq /* tf_rflags */
506 movl %cs,%eax
507 pushq %rax /* tf_cs */
508 pushq $outofnmi /* tf_rip */
509 iretq
510 outofnmi:
511 /*
512 * At this point the processor has exited NMI mode and is running
513 * with interrupts turned off on the normal kernel stack.
514 *
515 * If a pending NMI gets recognized at or after this point, it
516 * will cause a kernel callchain to be traced.
517 *
518 * We turn interrupts back on, and call the user callchain capture hook.
519 */
520 movq pmc_hook,%rax
521 orq %rax,%rax
522 jz nocallchain
523 movq PCPU(CURTHREAD),%rdi /* thread */
524 movq $PMC_FN_USER_CALLCHAIN,%rsi /* command */
525 movq %rsp,%rdx /* frame */
526 sti
527 call *%rax
528 cli
529 nocallchain:
530 #endif
531 testl %ebx,%ebx
532 jnz doreti_exit
533 nmi_kernelexit:
534 /*
535 * Put back the preserved MSR_GSBASE value.
536 */
537 movl $MSR_GSBASE,%ecx
538 movq %r12,%rdx
539 movl %edx,%eax
540 shrq $32,%rdx
541 wrmsr
542 nmi_restoreregs:
543 movq TF_RDI(%rsp),%rdi
544 movq TF_RSI(%rsp),%rsi
545 movq TF_RDX(%rsp),%rdx
546 movq TF_RCX(%rsp),%rcx
547 movq TF_R8(%rsp),%r8
548 movq TF_R9(%rsp),%r9
549 movq TF_RAX(%rsp),%rax
550 movq TF_RBX(%rsp),%rbx
551 movq TF_RBP(%rsp),%rbp
552 movq TF_R10(%rsp),%r10
553 movq TF_R11(%rsp),%r11
554 movq TF_R12(%rsp),%r12
555 movq TF_R13(%rsp),%r13
556 movq TF_R14(%rsp),%r14
557 movq TF_R15(%rsp),%r15
558 addq $TF_RIP,%rsp
559 jmp doreti_iret
560
561 ENTRY(fork_trampoline)
562 movq %r12,%rdi /* function */
563 movq %rbx,%rsi /* arg1 */
564 movq %rsp,%rdx /* trapframe pointer */
565 call fork_exit
566 MEXITCOUNT
567 jmp doreti /* Handle any ASTs */
568
569 /*
570 * To efficiently implement classification of trap and interrupt handlers
571 * for profiling, there must be only trap handlers between the labels btrap
572 * and bintr, and only interrupt handlers between the labels bintr and
573 * eintr. This is implemented (partly) by including files that contain
574 * some of the handlers. Before including the files, set up a normal asm
575 * environment so that the included files doen't need to know that they are
576 * included.
577 */
578
579 #ifdef COMPAT_FREEBSD32
580 .data
581 .p2align 4
582 .text
583 SUPERALIGN_TEXT
584
585 #include <amd64/ia32/ia32_exception.S>
586 #endif
587
588 .data
589 .p2align 4
590 .text
591 SUPERALIGN_TEXT
592 MCOUNT_LABEL(bintr)
593
594 #include <amd64/amd64/apic_vector.S>
595
596 #ifdef DEV_ATPIC
597 .data
598 .p2align 4
599 .text
600 SUPERALIGN_TEXT
601
602 #include <amd64/amd64/atpic_vector.S>
603 #endif
604
605 .text
606 MCOUNT_LABEL(eintr)
607
608 /*
609 * void doreti(struct trapframe)
610 *
611 * Handle return from interrupts, traps and syscalls.
612 */
613 .text
614 SUPERALIGN_TEXT
615 .type doreti,@function
616 doreti:
617 FAKE_MCOUNT($bintr) /* init "from" bintr -> doreti */
618 /*
619 * Check if ASTs can be handled now.
620 */
621 testb $SEL_RPL_MASK,TF_CS(%rsp) /* are we returning to user mode? */
622 jz doreti_exit /* can't handle ASTs now if not */
623
624 doreti_ast:
625 /*
626 * Check for ASTs atomically with returning. Disabling CPU
627 * interrupts provides sufficient locking eve in the SMP case,
628 * since we will be informed of any new ASTs by an IPI.
629 */
630 cli
631 movq PCPU(CURTHREAD),%rax
632 testl $TDF_ASTPENDING | TDF_NEEDRESCHED,TD_FLAGS(%rax)
633 je doreti_exit
634 sti
635 movq %rsp,%rdi /* pass a pointer to the trapframe */
636 call ast
637 jmp doreti_ast
638
639 /*
640 * doreti_exit: pop registers, iret.
641 *
642 * The segment register pop is a special case, since it may
643 * fault if (for example) a sigreturn specifies bad segment
644 * registers. The fault is handled in trap.c.
645 */
646 doreti_exit:
647 MEXITCOUNT
648 movq PCPU(CURTHREAD),%r8
649 movq TD_PCB(%r8),%r8
650
651 /*
652 * Do not reload segment registers for kernel.
653 * Since we do not reload segments registers with sane
654 * values on kernel entry, descriptors referenced by
655 * segments registers might be not valid. This is fatal
656 * for user mode, but is not a problem for the kernel.
657 */
658 testb $SEL_RPL_MASK,TF_CS(%rsp)
659 jz ld_regs
660 cmpb $0,PCB_FULL_IRET(%r8)
661 je ld_regs
662 testl $TF_HASSEGS,TF_FLAGS(%rsp)
663 je set_segs
664
665 do_segs:
666 /* Restore %fs and fsbase */
667 movw TF_FS(%rsp),%ax
668 .globl ld_fs
669 ld_fs:
670 movw %ax,%fs
671 cmpw $KUF32SEL,%ax
672 jne 1f
673 movl $MSR_FSBASE,%ecx
674 movl PCB_FSBASE(%r8),%eax
675 movl PCB_FSBASE+4(%r8),%edx
676 .globl ld_fsbase
677 ld_fsbase:
678 wrmsr
679 1:
680 /* Restore %gs and gsbase */
681 movw TF_GS(%rsp),%si
682 pushfq
683 cli
684 movl $MSR_GSBASE,%ecx
685 rdmsr
686 .globl ld_gs
687 ld_gs:
688 movw %si,%gs
689 wrmsr
690 popfq
691 cmpw $KUG32SEL,%si
692 jne 1f
693 movl $MSR_KGSBASE,%ecx
694 movl PCB_GSBASE(%r8),%eax
695 movl PCB_GSBASE+4(%r8),%edx
696 .globl ld_gsbase
697 ld_gsbase:
698 wrmsr
699 1:
700 .globl ld_es
701 ld_es:
702 movw TF_ES(%rsp),%es
703 .globl ld_ds
704 ld_ds:
705 movw TF_DS(%rsp),%ds
706 ld_regs:
707 movq TF_RDI(%rsp),%rdi
708 movq TF_RSI(%rsp),%rsi
709 movq TF_RDX(%rsp),%rdx
710 movq TF_RCX(%rsp),%rcx
711 movq TF_R8(%rsp),%r8
712 movq TF_R9(%rsp),%r9
713 movq TF_RAX(%rsp),%rax
714 movq TF_RBX(%rsp),%rbx
715 movq TF_RBP(%rsp),%rbp
716 movq TF_R10(%rsp),%r10
717 movq TF_R11(%rsp),%r11
718 movq TF_R12(%rsp),%r12
719 movq TF_R13(%rsp),%r13
720 movq TF_R14(%rsp),%r14
721 movq TF_R15(%rsp),%r15
722 testb $SEL_RPL_MASK,TF_CS(%rsp) /* Did we come from kernel? */
723 jz 1f /* keep running with kernel GS.base */
724 cli
725 swapgs
726 1:
727 addq $TF_RIP,%rsp /* skip over tf_err, tf_trapno */
728 .globl doreti_iret
729 doreti_iret:
730 iretq
731
732 set_segs:
733 movw $KUDSEL,%ax
734 movw %ax,TF_DS(%rsp)
735 movw %ax,TF_ES(%rsp)
736 movw $KUF32SEL,TF_FS(%rsp)
737 movw $KUG32SEL,TF_GS(%rsp)
738 jmp do_segs
739
740 /*
741 * doreti_iret_fault. Alternative return code for
742 * the case where we get a fault in the doreti_exit code
743 * above. trap() (amd64/amd64/trap.c) catches this specific
744 * case, sends the process a signal and continues in the
745 * corresponding place in the code below.
746 */
747 ALIGN_TEXT
748 .globl doreti_iret_fault
749 doreti_iret_fault:
750 subq $TF_RIP,%rsp /* space including tf_err, tf_trapno */
751 testl $PSL_I,TF_RFLAGS(%rsp)
752 jz 1f
753 sti
754 1:
755 movw %fs,TF_FS(%rsp)
756 movw %gs,TF_GS(%rsp)
757 movw %es,TF_ES(%rsp)
758 movw %ds,TF_DS(%rsp)
759 movl $TF_HASSEGS,TF_FLAGS(%rsp)
760 movq %rdi,TF_RDI(%rsp)
761 movq %rsi,TF_RSI(%rsp)
762 movq %rdx,TF_RDX(%rsp)
763 movq %rcx,TF_RCX(%rsp)
764 movq %r8,TF_R8(%rsp)
765 movq %r9,TF_R9(%rsp)
766 movq %rax,TF_RAX(%rsp)
767 movq %rbx,TF_RBX(%rsp)
768 movq %rbp,TF_RBP(%rsp)
769 movq %r10,TF_R10(%rsp)
770 movq %r11,TF_R11(%rsp)
771 movq %r12,TF_R12(%rsp)
772 movq %r13,TF_R13(%rsp)
773 movq %r14,TF_R14(%rsp)
774 movq %r15,TF_R15(%rsp)
775 movl $T_PROTFLT,TF_TRAPNO(%rsp)
776 movq $0,TF_ERR(%rsp) /* XXX should be the error code */
777 movq $0,TF_ADDR(%rsp)
778 FAKE_MCOUNT(TF_RIP(%rsp))
779 jmp calltrap
780
781 ALIGN_TEXT
782 .globl ds_load_fault
783 ds_load_fault:
784 movl $T_PROTFLT,TF_TRAPNO(%rsp)
785 movq %rsp,%rdi
786 call trap
787 movw $KUDSEL,TF_DS(%rsp)
788 jmp doreti
789
790 ALIGN_TEXT
791 .globl es_load_fault
792 es_load_fault:
793 movl $T_PROTFLT,TF_TRAPNO(%rsp)
794 movq %rsp,%rdi
795 call trap
796 movw $KUDSEL,TF_ES(%rsp)
797 jmp doreti
798
799 ALIGN_TEXT
800 .globl fs_load_fault
801 fs_load_fault:
802 movl $T_PROTFLT,TF_TRAPNO(%rsp)
803 movq %rsp,%rdi
804 call trap
805 movw $KUF32SEL,TF_FS(%rsp)
806 jmp doreti
807
808 ALIGN_TEXT
809 .globl gs_load_fault
810 gs_load_fault:
811 popfq
812 movl $T_PROTFLT,TF_TRAPNO(%rsp)
813 movq %rsp,%rdi
814 call trap
815 movw $KUG32SEL,TF_GS(%rsp)
816 jmp doreti
817
818 ALIGN_TEXT
819 .globl fsbase_load_fault
820 fsbase_load_fault:
821 movl $T_PROTFLT,TF_TRAPNO(%rsp)
822 movq %rsp,%rdi
823 call trap
824 movq PCPU(CURTHREAD),%r8
825 movq TD_PCB(%r8),%r8
826 movq $0,PCB_FSBASE(%r8)
827 jmp doreti
828
829 ALIGN_TEXT
830 .globl gsbase_load_fault
831 gsbase_load_fault:
832 movl $T_PROTFLT,TF_TRAPNO(%rsp)
833 movq %rsp,%rdi
834 call trap
835 movq PCPU(CURTHREAD),%r8
836 movq TD_PCB(%r8),%r8
837 movq $0,PCB_GSBASE(%r8)
838 jmp doreti
839
840 #ifdef HWPMC_HOOKS
841 ENTRY(end_exceptions)
842 #endif
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