The Design and Implementation of the FreeBSD Operating System, Second Edition
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sys/amd64/amd64/fpu.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-3-Clause
    3  *
    4  * Copyright (c) 1990 William Jolitz.
    5  * Copyright (c) 1991 The Regents of the University of California.
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. Neither the name of the University nor the names of its contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   30  * SUCH DAMAGE.
   31  *
   32  *      from: @(#)npx.c 7.2 (Berkeley) 5/12/91
   33  */
   34 
   35 #include <sys/cdefs.h>
   36 __FBSDID("$FreeBSD: head/sys/amd64/amd64/fpu.c 346294 2019-04-16 19:46:02Z kib $");
   37 
   38 #include <sys/param.h>
   39 #include <sys/systm.h>
   40 #include <sys/bus.h>
   41 #include <sys/kernel.h>
   42 #include <sys/lock.h>
   43 #include <sys/malloc.h>
   44 #include <sys/module.h>
   45 #include <sys/mutex.h>
   46 #include <sys/mutex.h>
   47 #include <sys/proc.h>
   48 #include <sys/sysctl.h>
   49 #include <machine/bus.h>
   50 #include <sys/rman.h>
   51 #include <sys/signalvar.h>
   52 #include <vm/uma.h>
   53 
   54 #include <machine/cputypes.h>
   55 #include <machine/frame.h>
   56 #include <machine/intr_machdep.h>
   57 #include <machine/md_var.h>
   58 #include <machine/pcb.h>
   59 #include <machine/psl.h>
   60 #include <machine/resource.h>
   61 #include <machine/specialreg.h>
   62 #include <machine/segments.h>
   63 #include <machine/ucontext.h>
   64 #include <x86/ifunc.h>
   65 
   66 /*
   67  * Floating point support.
   68  */
   69 
   70 #if defined(__GNUCLIKE_ASM) && !defined(lint)
   71 
   72 #define fldcw(cw)               __asm __volatile("fldcw %0" : : "m" (cw))
   73 #define fnclex()                __asm __volatile("fnclex")
   74 #define fninit()                __asm __volatile("fninit")
   75 #define fnstcw(addr)            __asm __volatile("fnstcw %0" : "=m" (*(addr)))
   76 #define fnstsw(addr)            __asm __volatile("fnstsw %0" : "=am" (*(addr)))
   77 #define fxrstor(addr)           __asm __volatile("fxrstor %0" : : "m" (*(addr)))
   78 #define fxsave(addr)            __asm __volatile("fxsave %0" : "=m" (*(addr)))
   79 #define ldmxcsr(csr)            __asm __volatile("ldmxcsr %0" : : "m" (csr))
   80 #define stmxcsr(addr)           __asm __volatile("stmxcsr %0" : : "m" (*(addr)))
   81 
   82 static __inline void
   83 xrstor(char *addr, uint64_t mask)
   84 {
   85         uint32_t low, hi;
   86 
   87         low = mask;
   88         hi = mask >> 32;
   89         __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi));
   90 }
   91 
   92 static __inline void
   93 xsave(char *addr, uint64_t mask)
   94 {
   95         uint32_t low, hi;
   96 
   97         low = mask;
   98         hi = mask >> 32;
   99         __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) :
  100             "memory");
  101 }
  102 
  103 static __inline void
  104 xsaveopt(char *addr, uint64_t mask)
  105 {
  106         uint32_t low, hi;
  107 
  108         low = mask;
  109         hi = mask >> 32;
  110         __asm __volatile("xsaveopt %0" : "=m" (*addr) : "a" (low), "d" (hi) :
  111             "memory");
  112 }
  113 
  114 #else   /* !(__GNUCLIKE_ASM && !lint) */
  115 
  116 void    fldcw(u_short cw);
  117 void    fnclex(void);
  118 void    fninit(void);
  119 void    fnstcw(caddr_t addr);
  120 void    fnstsw(caddr_t addr);
  121 void    fxsave(caddr_t addr);
  122 void    fxrstor(caddr_t addr);
  123 void    ldmxcsr(u_int csr);
  124 void    stmxcsr(u_int *csr);
  125 void    xrstor(char *addr, uint64_t mask);
  126 void    xsave(char *addr, uint64_t mask);
  127 void    xsaveopt(char *addr, uint64_t mask);
  128 
  129 #endif  /* __GNUCLIKE_ASM && !lint */
  130 
  131 #define start_emulating()       load_cr0(rcr0() | CR0_TS)
  132 #define stop_emulating()        clts()
  133 
  134 CTASSERT(sizeof(struct savefpu) == 512);
  135 CTASSERT(sizeof(struct xstate_hdr) == 64);
  136 CTASSERT(sizeof(struct savefpu_ymm) == 832);
  137 
  138 /*
  139  * This requirement is to make it easier for asm code to calculate
  140  * offset of the fpu save area from the pcb address. FPU save area
  141  * must be 64-byte aligned.
  142  */
  143 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0);
  144 
  145 /*
  146  * Ensure the copy of XCR0 saved in a core is contained in the padding
  147  * area.
  148  */
  149 CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savefpu, sv_pad) &&
  150     X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savefpu));
  151 
  152 static  void    fpu_clean_state(void);
  153 
  154 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD,
  155     SYSCTL_NULL_INT_PTR, 1, "Floating point instructions executed in hardware");
  156 
  157 int lazy_fpu_switch = 0;
  158 SYSCTL_INT(_hw, OID_AUTO, lazy_fpu_switch, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
  159     &lazy_fpu_switch, 0,
  160     "Lazily load FPU context after context switch");
  161 
  162 int use_xsave;                  /* non-static for cpu_switch.S */
  163 uint64_t xsave_mask;            /* the same */
  164 static  uma_zone_t fpu_save_area_zone;
  165 static  struct savefpu *fpu_initialstate;
  166 
  167 struct xsave_area_elm_descr {
  168         u_int   offset;
  169         u_int   size;
  170 } *xsave_area_desc;
  171 
  172 static void
  173 fpusave_xsaveopt(void *addr)
  174 {
  175 
  176         xsaveopt((char *)addr, xsave_mask);
  177 }
  178 
  179 static void
  180 fpusave_xsave(void *addr)
  181 {
  182 
  183         xsave((char *)addr, xsave_mask);
  184 }
  185 
  186 static void
  187 fpurestore_xrstor(void *addr)
  188 {
  189 
  190         xrstor((char *)addr, xsave_mask);
  191 }
  192 
  193 static void
  194 fpusave_fxsave(void *addr)
  195 {
  196 
  197         fxsave((char *)addr);
  198 }
  199 
  200 static void
  201 fpurestore_fxrstor(void *addr)
  202 {
  203 
  204         fxrstor((char *)addr);
  205 }
  206 
  207 static void
  208 init_xsave(void)
  209 {
  210 
  211         if (use_xsave)
  212                 return;
  213         if ((cpu_feature2 & CPUID2_XSAVE) == 0)
  214                 return;
  215         use_xsave = 1;
  216         TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave);
  217 }
  218 
  219 DEFINE_IFUNC(, void, fpusave, (void *), static)
  220 {
  221 
  222         init_xsave();
  223         if (use_xsave)
  224                 return ((cpu_stdext_feature & CPUID_EXTSTATE_XSAVEOPT) != 0 ?
  225                     fpusave_xsaveopt : fpusave_xsave);
  226         return (fpusave_fxsave);
  227 }
  228 
  229 DEFINE_IFUNC(, void, fpurestore, (void *), static)
  230 {
  231 
  232         init_xsave();
  233         return (use_xsave ? fpurestore_xrstor : fpurestore_fxrstor);
  234 }
  235 
  236 void
  237 fpususpend(void *addr)
  238 {
  239         u_long cr0;
  240 
  241         cr0 = rcr0();
  242         stop_emulating();
  243         fpusave(addr);
  244         load_cr0(cr0);
  245 }
  246 
  247 void
  248 fpuresume(void *addr)
  249 {
  250         u_long cr0;
  251 
  252         cr0 = rcr0();
  253         stop_emulating();
  254         fninit();
  255         if (use_xsave)
  256                 load_xcr(XCR0, xsave_mask);
  257         fpurestore(addr);
  258         load_cr0(cr0);
  259 }
  260 
  261 /*
  262  * Enable XSAVE if supported and allowed by user.
  263  * Calculate the xsave_mask.
  264  */
  265 static void
  266 fpuinit_bsp1(void)
  267 {
  268         u_int cp[4];
  269         uint64_t xsave_mask_user;
  270         bool old_wp;
  271 
  272         TUNABLE_INT_FETCH("hw.lazy_fpu_switch", &lazy_fpu_switch);
  273         if (!use_xsave)
  274                 return;
  275         cpuid_count(0xd, 0x0, cp);
  276         xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
  277         if ((cp[0] & xsave_mask) != xsave_mask)
  278                 panic("CPU0 does not support X87 or SSE: %x", cp[0]);
  279         xsave_mask = ((uint64_t)cp[3] << 32) | cp[0];
  280         xsave_mask_user = xsave_mask;
  281         TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user);
  282         xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
  283         xsave_mask &= xsave_mask_user;
  284         if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512)
  285                 xsave_mask &= ~XFEATURE_AVX512;
  286         if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX)
  287                 xsave_mask &= ~XFEATURE_MPX;
  288 
  289         cpuid_count(0xd, 0x1, cp);
  290         if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) {
  291                 /*
  292                  * Patch the XSAVE instruction in the cpu_switch code
  293                  * to XSAVEOPT.  We assume that XSAVE encoding used
  294                  * REX byte, and set the bit 4 of the r/m byte.
  295                  *
  296                  * It seems that some BIOSes give control to the OS
  297                  * with CR0.WP already set, making the kernel text
  298                  * read-only before cpu_startup().
  299                  */
  300                 old_wp = disable_wp();
  301                 ctx_switch_xsave[3] |= 0x10;
  302                 restore_wp(old_wp);
  303         }
  304 }
  305 
  306 /*
  307  * Calculate the fpu save area size.
  308  */
  309 static void
  310 fpuinit_bsp2(void)
  311 {
  312         u_int cp[4];
  313 
  314         if (use_xsave) {
  315                 cpuid_count(0xd, 0x0, cp);
  316                 cpu_max_ext_state_size = cp[1];
  317 
  318                 /*
  319                  * Reload the cpu_feature2, since we enabled OSXSAVE.
  320                  */
  321                 do_cpuid(1, cp);
  322                 cpu_feature2 = cp[2];
  323         } else
  324                 cpu_max_ext_state_size = sizeof(struct savefpu);
  325 }
  326 
  327 /*
  328  * Initialize the floating point unit.
  329  */
  330 void
  331 fpuinit(void)
  332 {
  333         register_t saveintr;
  334         u_int mxcsr;
  335         u_short control;
  336 
  337         if (IS_BSP())
  338                 fpuinit_bsp1();
  339 
  340         if (use_xsave) {
  341                 load_cr4(rcr4() | CR4_XSAVE);
  342                 load_xcr(XCR0, xsave_mask);
  343         }
  344 
  345         /*
  346          * XCR0 shall be set up before CPU can report the save area size.
  347          */
  348         if (IS_BSP())
  349                 fpuinit_bsp2();
  350 
  351         /*
  352          * It is too early for critical_enter() to work on AP.
  353          */
  354         saveintr = intr_disable();
  355         stop_emulating();
  356         fninit();
  357         control = __INITIAL_FPUCW__;
  358         fldcw(control);
  359         mxcsr = __INITIAL_MXCSR__;
  360         ldmxcsr(mxcsr);
  361         start_emulating();
  362         intr_restore(saveintr);
  363 }
  364 
  365 /*
  366  * On the boot CPU we generate a clean state that is used to
  367  * initialize the floating point unit when it is first used by a
  368  * process.
  369  */
  370 static void
  371 fpuinitstate(void *arg __unused)
  372 {
  373         uint64_t *xstate_bv;
  374         register_t saveintr;
  375         int cp[4], i, max_ext_n;
  376 
  377         fpu_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF,
  378             M_WAITOK | M_ZERO);
  379         saveintr = intr_disable();
  380         stop_emulating();
  381 
  382         fpusave_fxsave(fpu_initialstate);
  383         if (fpu_initialstate->sv_env.en_mxcsr_mask)
  384                 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask;
  385         else
  386                 cpu_mxcsr_mask = 0xFFBF;
  387 
  388         /*
  389          * The fninit instruction does not modify XMM registers or x87
  390          * registers (MM/ST).  The fpusave call dumped the garbage
  391          * contained in the registers after reset to the initial state
  392          * saved.  Clear XMM and x87 registers file image to make the
  393          * startup program state and signal handler XMM/x87 register
  394          * content predictable.
  395          */
  396         bzero(fpu_initialstate->sv_fp, sizeof(fpu_initialstate->sv_fp));
  397         bzero(fpu_initialstate->sv_xmm, sizeof(fpu_initialstate->sv_xmm));
  398 
  399         /*
  400          * Create a table describing the layout of the CPU Extended
  401          * Save Area.
  402          */
  403         if (use_xsave) {
  404                 xstate_bv = (uint64_t *)((char *)(fpu_initialstate + 1) +
  405                     offsetof(struct xstate_hdr, xstate_bv));
  406                 *xstate_bv = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
  407 
  408                 max_ext_n = flsl(xsave_mask);
  409                 xsave_area_desc = malloc(max_ext_n * sizeof(struct
  410                     xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO);
  411                 /* x87 state */
  412                 xsave_area_desc[0].offset = 0;
  413                 xsave_area_desc[0].size = 160;
  414                 /* XMM */
  415                 xsave_area_desc[1].offset = 160;
  416                 xsave_area_desc[1].size = 288 - 160;
  417 
  418                 for (i = 2; i < max_ext_n; i++) {
  419                         cpuid_count(0xd, i, cp);
  420                         xsave_area_desc[i].offset = cp[1];
  421                         xsave_area_desc[i].size = cp[0];
  422                 }
  423         }
  424 
  425         fpu_save_area_zone = uma_zcreate("FPU_save_area",
  426             cpu_max_ext_state_size, NULL, NULL, NULL, NULL,
  427             XSAVE_AREA_ALIGN - 1, 0);
  428 
  429         start_emulating();
  430         intr_restore(saveintr);
  431 }
  432 /* EFIRT needs this to be initialized before we can enter our EFI environment */
  433 SYSINIT(fpuinitstate, SI_SUB_DRIVERS, SI_ORDER_FIRST, fpuinitstate, NULL);
  434 
  435 /*
  436  * Free coprocessor (if we have it).
  437  */
  438 void
  439 fpuexit(struct thread *td)
  440 {
  441 
  442         critical_enter();
  443         if (curthread == PCPU_GET(fpcurthread)) {
  444                 stop_emulating();
  445                 fpusave(curpcb->pcb_save);
  446                 start_emulating();
  447                 PCPU_SET(fpcurthread, NULL);
  448         }
  449         critical_exit();
  450 }
  451 
  452 int
  453 fpuformat(void)
  454 {
  455 
  456         return (_MC_FPFMT_XMM);
  457 }
  458 
  459 /* 
  460  * The following mechanism is used to ensure that the FPE_... value
  461  * that is passed as a trapcode to the signal handler of the user
  462  * process does not have more than one bit set.
  463  * 
  464  * Multiple bits may be set if the user process modifies the control
  465  * word while a status word bit is already set.  While this is a sign
  466  * of bad coding, we have no choise than to narrow them down to one
  467  * bit, since we must not send a trapcode that is not exactly one of
  468  * the FPE_ macros.
  469  *
  470  * The mechanism has a static table with 127 entries.  Each combination
  471  * of the 7 FPU status word exception bits directly translates to a
  472  * position in this table, where a single FPE_... value is stored.
  473  * This FPE_... value stored there is considered the "most important"
  474  * of the exception bits and will be sent as the signal code.  The
  475  * precedence of the bits is based upon Intel Document "Numerical
  476  * Applications", Chapter "Special Computational Situations".
  477  *
  478  * The macro to choose one of these values does these steps: 1) Throw
  479  * away status word bits that cannot be masked.  2) Throw away the bits
  480  * currently masked in the control word, assuming the user isn't
  481  * interested in them anymore.  3) Reinsert status word bit 7 (stack
  482  * fault) if it is set, which cannot be masked but must be presered.
  483  * 4) Use the remaining bits to point into the trapcode table.
  484  *
  485  * The 6 maskable bits in order of their preference, as stated in the
  486  * above referenced Intel manual:
  487  * 1  Invalid operation (FP_X_INV)
  488  * 1a   Stack underflow
  489  * 1b   Stack overflow
  490  * 1c   Operand of unsupported format
  491  * 1d   SNaN operand.
  492  * 2  QNaN operand (not an exception, irrelavant here)
  493  * 3  Any other invalid-operation not mentioned above or zero divide
  494  *      (FP_X_INV, FP_X_DZ)
  495  * 4  Denormal operand (FP_X_DNML)
  496  * 5  Numeric over/underflow (FP_X_OFL, FP_X_UFL)
  497  * 6  Inexact result (FP_X_IMP) 
  498  */
  499 static char fpetable[128] = {
  500         0,
  501         FPE_FLTINV,     /*  1 - INV */
  502         FPE_FLTUND,     /*  2 - DNML */
  503         FPE_FLTINV,     /*  3 - INV | DNML */
  504         FPE_FLTDIV,     /*  4 - DZ */
  505         FPE_FLTINV,     /*  5 - INV | DZ */
  506         FPE_FLTDIV,     /*  6 - DNML | DZ */
  507         FPE_FLTINV,     /*  7 - INV | DNML | DZ */
  508         FPE_FLTOVF,     /*  8 - OFL */
  509         FPE_FLTINV,     /*  9 - INV | OFL */
  510         FPE_FLTUND,     /*  A - DNML | OFL */
  511         FPE_FLTINV,     /*  B - INV | DNML | OFL */
  512         FPE_FLTDIV,     /*  C - DZ | OFL */
  513         FPE_FLTINV,     /*  D - INV | DZ | OFL */
  514         FPE_FLTDIV,     /*  E - DNML | DZ | OFL */
  515         FPE_FLTINV,     /*  F - INV | DNML | DZ | OFL */
  516         FPE_FLTUND,     /* 10 - UFL */
  517         FPE_FLTINV,     /* 11 - INV | UFL */
  518         FPE_FLTUND,     /* 12 - DNML | UFL */
  519         FPE_FLTINV,     /* 13 - INV | DNML | UFL */
  520         FPE_FLTDIV,     /* 14 - DZ | UFL */
  521         FPE_FLTINV,     /* 15 - INV | DZ | UFL */
  522         FPE_FLTDIV,     /* 16 - DNML | DZ | UFL */
  523         FPE_FLTINV,     /* 17 - INV | DNML | DZ | UFL */
  524         FPE_FLTOVF,     /* 18 - OFL | UFL */
  525         FPE_FLTINV,     /* 19 - INV | OFL | UFL */
  526         FPE_FLTUND,     /* 1A - DNML | OFL | UFL */
  527         FPE_FLTINV,     /* 1B - INV | DNML | OFL | UFL */
  528         FPE_FLTDIV,     /* 1C - DZ | OFL | UFL */
  529         FPE_FLTINV,     /* 1D - INV | DZ | OFL | UFL */
  530         FPE_FLTDIV,     /* 1E - DNML | DZ | OFL | UFL */
  531         FPE_FLTINV,     /* 1F - INV | DNML | DZ | OFL | UFL */
  532         FPE_FLTRES,     /* 20 - IMP */
  533         FPE_FLTINV,     /* 21 - INV | IMP */
  534         FPE_FLTUND,     /* 22 - DNML | IMP */
  535         FPE_FLTINV,     /* 23 - INV | DNML | IMP */
  536         FPE_FLTDIV,     /* 24 - DZ | IMP */
  537         FPE_FLTINV,     /* 25 - INV | DZ | IMP */
  538         FPE_FLTDIV,     /* 26 - DNML | DZ | IMP */
  539         FPE_FLTINV,     /* 27 - INV | DNML | DZ | IMP */
  540         FPE_FLTOVF,     /* 28 - OFL | IMP */
  541         FPE_FLTINV,     /* 29 - INV | OFL | IMP */
  542         FPE_FLTUND,     /* 2A - DNML | OFL | IMP */
  543         FPE_FLTINV,     /* 2B - INV | DNML | OFL | IMP */
  544         FPE_FLTDIV,     /* 2C - DZ | OFL | IMP */
  545         FPE_FLTINV,     /* 2D - INV | DZ | OFL | IMP */
  546         FPE_FLTDIV,     /* 2E - DNML | DZ | OFL | IMP */
  547         FPE_FLTINV,     /* 2F - INV | DNML | DZ | OFL | IMP */
  548         FPE_FLTUND,     /* 30 - UFL | IMP */
  549         FPE_FLTINV,     /* 31 - INV | UFL | IMP */
  550         FPE_FLTUND,     /* 32 - DNML | UFL | IMP */
  551         FPE_FLTINV,     /* 33 - INV | DNML | UFL | IMP */
  552         FPE_FLTDIV,     /* 34 - DZ | UFL | IMP */
  553         FPE_FLTINV,     /* 35 - INV | DZ | UFL | IMP */
  554         FPE_FLTDIV,     /* 36 - DNML | DZ | UFL | IMP */
  555         FPE_FLTINV,     /* 37 - INV | DNML | DZ | UFL | IMP */
  556         FPE_FLTOVF,     /* 38 - OFL | UFL | IMP */
  557         FPE_FLTINV,     /* 39 - INV | OFL | UFL | IMP */
  558         FPE_FLTUND,     /* 3A - DNML | OFL | UFL | IMP */
  559         FPE_FLTINV,     /* 3B - INV | DNML | OFL | UFL | IMP */
  560         FPE_FLTDIV,     /* 3C - DZ | OFL | UFL | IMP */
  561         FPE_FLTINV,     /* 3D - INV | DZ | OFL | UFL | IMP */
  562         FPE_FLTDIV,     /* 3E - DNML | DZ | OFL | UFL | IMP */
  563         FPE_FLTINV,     /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
  564         FPE_FLTSUB,     /* 40 - STK */
  565         FPE_FLTSUB,     /* 41 - INV | STK */
  566         FPE_FLTUND,     /* 42 - DNML | STK */
  567         FPE_FLTSUB,     /* 43 - INV | DNML | STK */
  568         FPE_FLTDIV,     /* 44 - DZ | STK */
  569         FPE_FLTSUB,     /* 45 - INV | DZ | STK */
  570         FPE_FLTDIV,     /* 46 - DNML | DZ | STK */
  571         FPE_FLTSUB,     /* 47 - INV | DNML | DZ | STK */
  572         FPE_FLTOVF,     /* 48 - OFL | STK */
  573         FPE_FLTSUB,     /* 49 - INV | OFL | STK */
  574         FPE_FLTUND,     /* 4A - DNML | OFL | STK */
  575         FPE_FLTSUB,     /* 4B - INV | DNML | OFL | STK */
  576         FPE_FLTDIV,     /* 4C - DZ | OFL | STK */
  577         FPE_FLTSUB,     /* 4D - INV | DZ | OFL | STK */
  578         FPE_FLTDIV,     /* 4E - DNML | DZ | OFL | STK */
  579         FPE_FLTSUB,     /* 4F - INV | DNML | DZ | OFL | STK */
  580         FPE_FLTUND,     /* 50 - UFL | STK */
  581         FPE_FLTSUB,     /* 51 - INV | UFL | STK */
  582         FPE_FLTUND,     /* 52 - DNML | UFL | STK */
  583         FPE_FLTSUB,     /* 53 - INV | DNML | UFL | STK */
  584         FPE_FLTDIV,     /* 54 - DZ | UFL | STK */
  585         FPE_FLTSUB,     /* 55 - INV | DZ | UFL | STK */
  586         FPE_FLTDIV,     /* 56 - DNML | DZ | UFL | STK */
  587         FPE_FLTSUB,     /* 57 - INV | DNML | DZ | UFL | STK */
  588         FPE_FLTOVF,     /* 58 - OFL | UFL | STK */
  589         FPE_FLTSUB,     /* 59 - INV | OFL | UFL | STK */
  590         FPE_FLTUND,     /* 5A - DNML | OFL | UFL | STK */
  591         FPE_FLTSUB,     /* 5B - INV | DNML | OFL | UFL | STK */
  592         FPE_FLTDIV,     /* 5C - DZ | OFL | UFL | STK */
  593         FPE_FLTSUB,     /* 5D - INV | DZ | OFL | UFL | STK */
  594         FPE_FLTDIV,     /* 5E - DNML | DZ | OFL | UFL | STK */
  595         FPE_FLTSUB,     /* 5F - INV | DNML | DZ | OFL | UFL | STK */
  596         FPE_FLTRES,     /* 60 - IMP | STK */
  597         FPE_FLTSUB,     /* 61 - INV | IMP | STK */
  598         FPE_FLTUND,     /* 62 - DNML | IMP | STK */
  599         FPE_FLTSUB,     /* 63 - INV | DNML | IMP | STK */
  600         FPE_FLTDIV,     /* 64 - DZ | IMP | STK */
  601         FPE_FLTSUB,     /* 65 - INV | DZ | IMP | STK */
  602         FPE_FLTDIV,     /* 66 - DNML | DZ | IMP | STK */
  603         FPE_FLTSUB,     /* 67 - INV | DNML | DZ | IMP | STK */
  604         FPE_FLTOVF,     /* 68 - OFL | IMP | STK */
  605         FPE_FLTSUB,     /* 69 - INV | OFL | IMP | STK */
  606         FPE_FLTUND,     /* 6A - DNML | OFL | IMP | STK */
  607         FPE_FLTSUB,     /* 6B - INV | DNML | OFL | IMP | STK */
  608         FPE_FLTDIV,     /* 6C - DZ | OFL | IMP | STK */
  609         FPE_FLTSUB,     /* 6D - INV | DZ | OFL | IMP | STK */
  610         FPE_FLTDIV,     /* 6E - DNML | DZ | OFL | IMP | STK */
  611         FPE_FLTSUB,     /* 6F - INV | DNML | DZ | OFL | IMP | STK */
  612         FPE_FLTUND,     /* 70 - UFL | IMP | STK */
  613         FPE_FLTSUB,     /* 71 - INV | UFL | IMP | STK */
  614         FPE_FLTUND,     /* 72 - DNML | UFL | IMP | STK */
  615         FPE_FLTSUB,     /* 73 - INV | DNML | UFL | IMP | STK */
  616         FPE_FLTDIV,     /* 74 - DZ | UFL | IMP | STK */
  617         FPE_FLTSUB,     /* 75 - INV | DZ | UFL | IMP | STK */
  618         FPE_FLTDIV,     /* 76 - DNML | DZ | UFL | IMP | STK */
  619         FPE_FLTSUB,     /* 77 - INV | DNML | DZ | UFL | IMP | STK */
  620         FPE_FLTOVF,     /* 78 - OFL | UFL | IMP | STK */
  621         FPE_FLTSUB,     /* 79 - INV | OFL | UFL | IMP | STK */
  622         FPE_FLTUND,     /* 7A - DNML | OFL | UFL | IMP | STK */
  623         FPE_FLTSUB,     /* 7B - INV | DNML | OFL | UFL | IMP | STK */
  624         FPE_FLTDIV,     /* 7C - DZ | OFL | UFL | IMP | STK */
  625         FPE_FLTSUB,     /* 7D - INV | DZ | OFL | UFL | IMP | STK */
  626         FPE_FLTDIV,     /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
  627         FPE_FLTSUB,     /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
  628 };
  629 
  630 /*
  631  * Read the FP status and control words, then generate si_code value
  632  * for SIGFPE.  The error code chosen will be one of the
  633  * FPE_... macros.  It will be sent as the second argument to old
  634  * BSD-style signal handlers and as "siginfo_t->si_code" (second
  635  * argument) to SA_SIGINFO signal handlers.
  636  *
  637  * Some time ago, we cleared the x87 exceptions with FNCLEX there.
  638  * Clearing exceptions was necessary mainly to avoid IRQ13 bugs.  The
  639  * usermode code which understands the FPU hardware enough to enable
  640  * the exceptions, can also handle clearing the exception state in the
  641  * handler.  The only consequence of not clearing the exception is the
  642  * rethrow of the SIGFPE on return from the signal handler and
  643  * reexecution of the corresponding instruction.
  644  *
  645  * For XMM traps, the exceptions were never cleared.
  646  */
  647 int
  648 fputrap_x87(void)
  649 {
  650         struct savefpu *pcb_save;
  651         u_short control, status;
  652 
  653         critical_enter();
  654 
  655         /*
  656          * Interrupt handling (for another interrupt) may have pushed the
  657          * state to memory.  Fetch the relevant parts of the state from
  658          * wherever they are.
  659          */
  660         if (PCPU_GET(fpcurthread) != curthread) {
  661                 pcb_save = curpcb->pcb_save;
  662                 control = pcb_save->sv_env.en_cw;
  663                 status = pcb_save->sv_env.en_sw;
  664         } else {
  665                 fnstcw(&control);
  666                 fnstsw(&status);
  667         }
  668 
  669         critical_exit();
  670         return (fpetable[status & ((~control & 0x3f) | 0x40)]);
  671 }
  672 
  673 int
  674 fputrap_sse(void)
  675 {
  676         u_int mxcsr;
  677 
  678         critical_enter();
  679         if (PCPU_GET(fpcurthread) != curthread)
  680                 mxcsr = curpcb->pcb_save->sv_env.en_mxcsr;
  681         else
  682                 stmxcsr(&mxcsr);
  683         critical_exit();
  684         return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]);
  685 }
  686 
  687 static void
  688 restore_fpu_curthread(struct thread *td)
  689 {
  690         struct pcb *pcb;
  691 
  692         /*
  693          * Record new context early in case frstor causes a trap.
  694          */
  695         PCPU_SET(fpcurthread, td);
  696 
  697         stop_emulating();
  698         fpu_clean_state();
  699         pcb = td->td_pcb;
  700 
  701         if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) {
  702                 /*
  703                  * This is the first time this thread has used the FPU or
  704                  * the PCB doesn't contain a clean FPU state.  Explicitly
  705                  * load an initial state.
  706                  *
  707                  * We prefer to restore the state from the actual save
  708                  * area in PCB instead of directly loading from
  709                  * fpu_initialstate, to ignite the XSAVEOPT
  710                  * tracking engine.
  711                  */
  712                 bcopy(fpu_initialstate, pcb->pcb_save,
  713                     cpu_max_ext_state_size);
  714                 fpurestore(pcb->pcb_save);
  715                 if (pcb->pcb_initial_fpucw != __INITIAL_FPUCW__)
  716                         fldcw(pcb->pcb_initial_fpucw);
  717                 if (PCB_USER_FPU(pcb))
  718                         set_pcb_flags(pcb, PCB_FPUINITDONE |
  719                             PCB_USERFPUINITDONE);
  720                 else
  721                         set_pcb_flags(pcb, PCB_FPUINITDONE);
  722         } else
  723                 fpurestore(pcb->pcb_save);
  724 }
  725 
  726 /*
  727  * Device Not Available (DNA, #NM) exception handler.
  728  *
  729  * It would be better to switch FP context here (if curthread !=
  730  * fpcurthread) and not necessarily for every context switch, but it
  731  * is too hard to access foreign pcb's.
  732  */
  733 void
  734 fpudna(void)
  735 {
  736         struct thread *td;
  737 
  738         td = curthread;
  739         /*
  740          * This handler is entered with interrupts enabled, so context
  741          * switches may occur before critical_enter() is executed.  If
  742          * a context switch occurs, then when we regain control, our
  743          * state will have been completely restored.  The CPU may
  744          * change underneath us, but the only part of our context that
  745          * lives in the CPU is CR0.TS and that will be "restored" by
  746          * setting it on the new CPU.
  747          */
  748         critical_enter();
  749 
  750         KASSERT((curpcb->pcb_flags & PCB_FPUNOSAVE) == 0,
  751             ("fpudna while in fpu_kern_enter(FPU_KERN_NOCTX)"));
  752         if (__predict_false(PCPU_GET(fpcurthread) == td)) {
  753                 /*
  754                  * Some virtual machines seems to set %cr0.TS at
  755                  * arbitrary moments.  Silently clear the TS bit
  756                  * regardless of the eager/lazy FPU context switch
  757                  * mode.
  758                  */
  759                 stop_emulating();
  760         } else {
  761                 if (__predict_false(PCPU_GET(fpcurthread) != NULL)) {
  762                         panic(
  763                     "fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n",
  764                             PCPU_GET(fpcurthread),
  765                             PCPU_GET(fpcurthread)->td_tid, td, td->td_tid);
  766                 }
  767                 restore_fpu_curthread(td);
  768         }
  769         critical_exit();
  770 }
  771 
  772 void fpu_activate_sw(struct thread *td); /* Called from the context switch */
  773 void
  774 fpu_activate_sw(struct thread *td)
  775 {
  776 
  777         if (lazy_fpu_switch || (td->td_pflags & TDP_KTHREAD) != 0 ||
  778             !PCB_USER_FPU(td->td_pcb)) {
  779                 PCPU_SET(fpcurthread, NULL);
  780                 start_emulating();
  781         } else if (PCPU_GET(fpcurthread) != td) {
  782                 restore_fpu_curthread(td);
  783         }
  784 }
  785 
  786 void
  787 fpudrop(void)
  788 {
  789         struct thread *td;
  790 
  791         td = PCPU_GET(fpcurthread);
  792         KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread"));
  793         CRITICAL_ASSERT(td);
  794         PCPU_SET(fpcurthread, NULL);
  795         clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE);
  796         start_emulating();
  797 }
  798 
  799 /*
  800  * Get the user state of the FPU into pcb->pcb_user_save without
  801  * dropping ownership (if possible).  It returns the FPU ownership
  802  * status.
  803  */
  804 int
  805 fpugetregs(struct thread *td)
  806 {
  807         struct pcb *pcb;
  808         uint64_t *xstate_bv, bit;
  809         char *sa;
  810         int max_ext_n, i, owned;
  811 
  812         pcb = td->td_pcb;
  813         critical_enter();
  814         if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) {
  815                 bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb),
  816                     cpu_max_ext_state_size);
  817                 get_pcb_user_save_pcb(pcb)->sv_env.en_cw =
  818                     pcb->pcb_initial_fpucw;
  819                 fpuuserinited(td);
  820                 critical_exit();
  821                 return (_MC_FPOWNED_PCB);
  822         }
  823         if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
  824                 fpusave(get_pcb_user_save_pcb(pcb));
  825                 owned = _MC_FPOWNED_FPU;
  826         } else {
  827                 owned = _MC_FPOWNED_PCB;
  828         }
  829         if (use_xsave) {
  830                 /*
  831                  * Handle partially saved state.
  832                  */
  833                 sa = (char *)get_pcb_user_save_pcb(pcb);
  834                 xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) +
  835                     offsetof(struct xstate_hdr, xstate_bv));
  836                 max_ext_n = flsl(xsave_mask);
  837                 for (i = 0; i < max_ext_n; i++) {
  838                         bit = 1ULL << i;
  839                         if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0)
  840                                 continue;
  841                         bcopy((char *)fpu_initialstate +
  842                             xsave_area_desc[i].offset,
  843                             sa + xsave_area_desc[i].offset,
  844                             xsave_area_desc[i].size);
  845                         *xstate_bv |= bit;
  846                 }
  847         }
  848         critical_exit();
  849         return (owned);
  850 }
  851 
  852 void
  853 fpuuserinited(struct thread *td)
  854 {
  855         struct pcb *pcb;
  856 
  857         CRITICAL_ASSERT(td);
  858         pcb = td->td_pcb;
  859         if (PCB_USER_FPU(pcb))
  860                 set_pcb_flags(pcb,
  861                     PCB_FPUINITDONE | PCB_USERFPUINITDONE);
  862         else
  863                 set_pcb_flags(pcb, PCB_FPUINITDONE);
  864 }
  865 
  866 int
  867 fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size)
  868 {
  869         struct xstate_hdr *hdr, *ehdr;
  870         size_t len, max_len;
  871         uint64_t bv;
  872 
  873         /* XXXKIB should we clear all extended state in xstate_bv instead ? */
  874         if (xfpustate == NULL)
  875                 return (0);
  876         if (!use_xsave)
  877                 return (EOPNOTSUPP);
  878 
  879         len = xfpustate_size;
  880         if (len < sizeof(struct xstate_hdr))
  881                 return (EINVAL);
  882         max_len = cpu_max_ext_state_size - sizeof(struct savefpu);
  883         if (len > max_len)
  884                 return (EINVAL);
  885 
  886         ehdr = (struct xstate_hdr *)xfpustate;
  887         bv = ehdr->xstate_bv;
  888 
  889         /*
  890          * Avoid #gp.
  891          */
  892         if (bv & ~xsave_mask)
  893                 return (EINVAL);
  894 
  895         hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1);
  896 
  897         hdr->xstate_bv = bv;
  898         bcopy(xfpustate + sizeof(struct xstate_hdr),
  899             (char *)(hdr + 1), len - sizeof(struct xstate_hdr));
  900 
  901         return (0);
  902 }
  903 
  904 /*
  905  * Set the state of the FPU.
  906  */
  907 int
  908 fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate,
  909     size_t xfpustate_size)
  910 {
  911         struct pcb *pcb;
  912         int error;
  913 
  914         addr->sv_env.en_mxcsr &= cpu_mxcsr_mask;
  915         pcb = td->td_pcb;
  916         error = 0;
  917         critical_enter();
  918         if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
  919                 error = fpusetxstate(td, xfpustate, xfpustate_size);
  920                 if (error == 0) {
  921                         bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
  922                         fpurestore(get_pcb_user_save_td(td));
  923                         set_pcb_flags(pcb, PCB_FPUINITDONE |
  924                             PCB_USERFPUINITDONE);
  925                 }
  926         } else {
  927                 error = fpusetxstate(td, xfpustate, xfpustate_size);
  928                 if (error == 0) {
  929                         bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
  930                         fpuuserinited(td);
  931                 }
  932         }
  933         critical_exit();
  934         return (error);
  935 }
  936 
  937 /*
  938  * On AuthenticAMD processors, the fxrstor instruction does not restore
  939  * the x87's stored last instruction pointer, last data pointer, and last
  940  * opcode values, except in the rare case in which the exception summary
  941  * (ES) bit in the x87 status word is set to 1.
  942  *
  943  * In order to avoid leaking this information across processes, we clean
  944  * these values by performing a dummy load before executing fxrstor().
  945  */
  946 static void
  947 fpu_clean_state(void)
  948 {
  949         static float dummy_variable = 0.0;
  950         u_short status;
  951 
  952         /*
  953          * Clear the ES bit in the x87 status word if it is currently
  954          * set, in order to avoid causing a fault in the upcoming load.
  955          */
  956         fnstsw(&status);
  957         if (status & 0x80)
  958                 fnclex();
  959 
  960         /*
  961          * Load the dummy variable into the x87 stack.  This mangles
  962          * the x87 stack, but we don't care since we're about to call
  963          * fxrstor() anyway.
  964          */
  965         __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable));
  966 }
  967 
  968 /*
  969  * This really sucks.  We want the acpi version only, but it requires
  970  * the isa_if.h file in order to get the definitions.
  971  */
  972 #include "opt_isa.h"
  973 #ifdef DEV_ISA
  974 #include <isa/isavar.h>
  975 /*
  976  * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
  977  */
  978 static struct isa_pnp_id fpupnp_ids[] = {
  979         { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
  980         { 0 }
  981 };
  982 
  983 static int
  984 fpupnp_probe(device_t dev)
  985 {
  986         int result;
  987 
  988         result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids);
  989         if (result <= 0)
  990                 device_quiet(dev);
  991         return (result);
  992 }
  993 
  994 static int
  995 fpupnp_attach(device_t dev)
  996 {
  997 
  998         return (0);
  999 }
 1000 
 1001 static device_method_t fpupnp_methods[] = {
 1002         /* Device interface */
 1003         DEVMETHOD(device_probe,         fpupnp_probe),
 1004         DEVMETHOD(device_attach,        fpupnp_attach),
 1005         DEVMETHOD(device_detach,        bus_generic_detach),
 1006         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 1007         DEVMETHOD(device_suspend,       bus_generic_suspend),
 1008         DEVMETHOD(device_resume,        bus_generic_resume),
 1009         
 1010         { 0, 0 }
 1011 };
 1012 
 1013 static driver_t fpupnp_driver = {
 1014         "fpupnp",
 1015         fpupnp_methods,
 1016         1,                      /* no softc */
 1017 };
 1018 
 1019 static devclass_t fpupnp_devclass;
 1020 
 1021 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0);
 1022 ISA_PNP_INFO(fpupnp_ids);
 1023 #endif  /* DEV_ISA */
 1024 
 1025 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx",
 1026     "Kernel contexts for FPU state");
 1027 
 1028 #define FPU_KERN_CTX_FPUINITDONE 0x01
 1029 #define FPU_KERN_CTX_DUMMY       0x02   /* avoided save for the kern thread */
 1030 #define FPU_KERN_CTX_INUSE       0x04
 1031 
 1032 struct fpu_kern_ctx {
 1033         struct savefpu *prev;
 1034         uint32_t flags;
 1035         char hwstate1[];
 1036 };
 1037 
 1038 struct fpu_kern_ctx *
 1039 fpu_kern_alloc_ctx(u_int flags)
 1040 {
 1041         struct fpu_kern_ctx *res;
 1042         size_t sz;
 1043 
 1044         sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN +
 1045             cpu_max_ext_state_size;
 1046         res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ?
 1047             M_NOWAIT : M_WAITOK) | M_ZERO);
 1048         return (res);
 1049 }
 1050 
 1051 void
 1052 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx)
 1053 {
 1054 
 1055         KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx"));
 1056         /* XXXKIB clear the memory ? */
 1057         free(ctx, M_FPUKERN_CTX);
 1058 }
 1059 
 1060 static struct savefpu *
 1061 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx)
 1062 {
 1063         vm_offset_t p;
 1064 
 1065         p = (vm_offset_t)&ctx->hwstate1;
 1066         p = roundup2(p, XSAVE_AREA_ALIGN);
 1067         return ((struct savefpu *)p);
 1068 }
 1069 
 1070 void
 1071 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags)
 1072 {
 1073         struct pcb *pcb;
 1074 
 1075         pcb = td->td_pcb;
 1076         KASSERT((flags & FPU_KERN_NOCTX) != 0 || ctx != NULL,
 1077             ("ctx is required when !FPU_KERN_NOCTX"));
 1078         KASSERT(ctx == NULL || (ctx->flags & FPU_KERN_CTX_INUSE) == 0,
 1079             ("using inuse ctx"));
 1080         KASSERT((pcb->pcb_flags & PCB_FPUNOSAVE) == 0,
 1081             ("recursive fpu_kern_enter while in PCB_FPUNOSAVE state"));
 1082 
 1083         if ((flags & FPU_KERN_NOCTX) != 0) {
 1084                 critical_enter();
 1085                 stop_emulating();
 1086                 if (curthread == PCPU_GET(fpcurthread)) {
 1087                         fpusave(curpcb->pcb_save);
 1088                         PCPU_SET(fpcurthread, NULL);
 1089                 } else {
 1090                         KASSERT(PCPU_GET(fpcurthread) == NULL,
 1091                             ("invalid fpcurthread"));
 1092                 }
 1093 
 1094                 /*
 1095                  * This breaks XSAVEOPT tracker, but
 1096                  * PCB_FPUNOSAVE state is supposed to never need to
 1097                  * save FPU context at all.
 1098                  */
 1099                 fpurestore(fpu_initialstate);
 1100                 set_pcb_flags(pcb, PCB_KERNFPU | PCB_FPUNOSAVE |
 1101                     PCB_FPUINITDONE);
 1102                 return;
 1103         }
 1104         if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) {
 1105                 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE;
 1106                 return;
 1107         }
 1108         critical_enter();
 1109         KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save ==
 1110             get_pcb_user_save_pcb(pcb), ("mangled pcb_save"));
 1111         ctx->flags = FPU_KERN_CTX_INUSE;
 1112         if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0)
 1113                 ctx->flags |= FPU_KERN_CTX_FPUINITDONE;
 1114         fpuexit(td);
 1115         ctx->prev = pcb->pcb_save;
 1116         pcb->pcb_save = fpu_kern_ctx_savefpu(ctx);
 1117         set_pcb_flags(pcb, PCB_KERNFPU);
 1118         clear_pcb_flags(pcb, PCB_FPUINITDONE);
 1119         critical_exit();
 1120 }
 1121 
 1122 int
 1123 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx)
 1124 {
 1125         struct pcb *pcb;
 1126 
 1127         pcb = td->td_pcb;
 1128 
 1129         if ((pcb->pcb_flags & PCB_FPUNOSAVE) != 0) {
 1130                 KASSERT(ctx == NULL, ("non-null ctx after FPU_KERN_NOCTX"));
 1131                 KASSERT(PCPU_GET(fpcurthread) == NULL,
 1132                     ("non-NULL fpcurthread for PCB_FPUNOSAVE"));
 1133                 CRITICAL_ASSERT(td);
 1134 
 1135                 clear_pcb_flags(pcb,  PCB_FPUNOSAVE | PCB_FPUINITDONE);
 1136                 start_emulating();
 1137         } else {
 1138                 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0,
 1139                     ("leaving not inuse ctx"));
 1140                 ctx->flags &= ~FPU_KERN_CTX_INUSE;
 1141 
 1142                 if (is_fpu_kern_thread(0) &&
 1143                     (ctx->flags & FPU_KERN_CTX_DUMMY) != 0)
 1144                         return (0);
 1145                 KASSERT((ctx->flags & FPU_KERN_CTX_DUMMY) == 0,
 1146                     ("dummy ctx"));
 1147                 critical_enter();
 1148                 if (curthread == PCPU_GET(fpcurthread))
 1149                         fpudrop();
 1150                 pcb->pcb_save = ctx->prev;
 1151         }
 1152 
 1153         if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) {
 1154                 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) {
 1155                         set_pcb_flags(pcb, PCB_FPUINITDONE);
 1156                         clear_pcb_flags(pcb, PCB_KERNFPU);
 1157                 } else
 1158                         clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU);
 1159         } else {
 1160                 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0)
 1161                         set_pcb_flags(pcb, PCB_FPUINITDONE);
 1162                 else
 1163                         clear_pcb_flags(pcb, PCB_FPUINITDONE);
 1164                 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave"));
 1165         }
 1166         critical_exit();
 1167         return (0);
 1168 }
 1169 
 1170 int
 1171 fpu_kern_thread(u_int flags)
 1172 {
 1173 
 1174         KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0,
 1175             ("Only kthread may use fpu_kern_thread"));
 1176         KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb),
 1177             ("mangled pcb_save"));
 1178         KASSERT(PCB_USER_FPU(curpcb), ("recursive call"));
 1179 
 1180         set_pcb_flags(curpcb, PCB_KERNFPU);
 1181         return (0);
 1182 }
 1183 
 1184 int
 1185 is_fpu_kern_thread(u_int flags)
 1186 {
 1187 
 1188         if ((curthread->td_pflags & TDP_KTHREAD) == 0)
 1189                 return (0);
 1190         return ((curpcb->pcb_flags & PCB_KERNFPU) != 0);
 1191 }
 1192 
 1193 /*
 1194  * FPU save area alloc/free/init utility routines
 1195  */
 1196 struct savefpu *
 1197 fpu_save_area_alloc(void)
 1198 {
 1199 
 1200         return (uma_zalloc(fpu_save_area_zone, 0));
 1201 }
 1202 
 1203 void
 1204 fpu_save_area_free(struct savefpu *fsa)
 1205 {
 1206 
 1207         uma_zfree(fpu_save_area_zone, fsa);
 1208 }
 1209 
 1210 void
 1211 fpu_save_area_reset(struct savefpu *fsa)
 1212 {
 1213 
 1214         bcopy(fpu_initialstate, fsa, cpu_max_ext_state_size);
 1215 }

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