FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/fpu.c
1 /*-
2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 4. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: releng/10.0/sys/amd64/amd64/fpu.c 250415 2013-05-09 17:25:29Z kib $");
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/bus.h>
39 #include <sys/kernel.h>
40 #include <sys/lock.h>
41 #include <sys/malloc.h>
42 #include <sys/module.h>
43 #include <sys/mutex.h>
44 #include <sys/mutex.h>
45 #include <sys/proc.h>
46 #include <sys/sysctl.h>
47 #include <machine/bus.h>
48 #include <sys/rman.h>
49 #include <sys/signalvar.h>
50 #include <vm/uma.h>
51
52 #include <machine/cputypes.h>
53 #include <machine/frame.h>
54 #include <machine/intr_machdep.h>
55 #include <machine/md_var.h>
56 #include <machine/pcb.h>
57 #include <machine/psl.h>
58 #include <machine/resource.h>
59 #include <machine/specialreg.h>
60 #include <machine/segments.h>
61 #include <machine/ucontext.h>
62
63 /*
64 * Floating point support.
65 */
66
67 #if defined(__GNUCLIKE_ASM) && !defined(lint)
68
69 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw))
70 #define fnclex() __asm __volatile("fnclex")
71 #define fninit() __asm __volatile("fninit")
72 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
73 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr)))
74 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr)))
75 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
76 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr))
77 #define stmxcsr(addr) __asm __volatile("stmxcsr %0" : : "m" (*(addr)))
78
79 static __inline void
80 xrstor(char *addr, uint64_t mask)
81 {
82 uint32_t low, hi;
83
84 low = mask;
85 hi = mask >> 32;
86 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi));
87 }
88
89 static __inline void
90 xsave(char *addr, uint64_t mask)
91 {
92 uint32_t low, hi;
93
94 low = mask;
95 hi = mask >> 32;
96 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) :
97 "memory");
98 }
99
100 #else /* !(__GNUCLIKE_ASM && !lint) */
101
102 void fldcw(u_short cw);
103 void fnclex(void);
104 void fninit(void);
105 void fnstcw(caddr_t addr);
106 void fnstsw(caddr_t addr);
107 void fxsave(caddr_t addr);
108 void fxrstor(caddr_t addr);
109 void ldmxcsr(u_int csr);
110 void stmxcsr(u_int *csr);
111 void xrstor(char *addr, uint64_t mask);
112 void xsave(char *addr, uint64_t mask);
113
114 #endif /* __GNUCLIKE_ASM && !lint */
115
116 #define start_emulating() load_cr0(rcr0() | CR0_TS)
117 #define stop_emulating() clts()
118
119 CTASSERT(sizeof(struct savefpu) == 512);
120 CTASSERT(sizeof(struct xstate_hdr) == 64);
121 CTASSERT(sizeof(struct savefpu_ymm) == 832);
122
123 /*
124 * This requirement is to make it easier for asm code to calculate
125 * offset of the fpu save area from the pcb address. FPU save area
126 * must be 64-byte aligned.
127 */
128 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0);
129
130 static void fpu_clean_state(void);
131
132 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD,
133 NULL, 1, "Floating point instructions executed in hardware");
134
135 int use_xsave; /* non-static for cpu_switch.S */
136 uint64_t xsave_mask; /* the same */
137 static uma_zone_t fpu_save_area_zone;
138 static struct savefpu *fpu_initialstate;
139
140 struct xsave_area_elm_descr {
141 u_int offset;
142 u_int size;
143 } *xsave_area_desc;
144
145 void
146 fpusave(void *addr)
147 {
148
149 if (use_xsave)
150 xsave((char *)addr, xsave_mask);
151 else
152 fxsave((char *)addr);
153 }
154
155 void
156 fpurestore(void *addr)
157 {
158
159 if (use_xsave)
160 xrstor((char *)addr, xsave_mask);
161 else
162 fxrstor((char *)addr);
163 }
164
165 /*
166 * Enable XSAVE if supported and allowed by user.
167 * Calculate the xsave_mask.
168 */
169 static void
170 fpuinit_bsp1(void)
171 {
172 u_int cp[4];
173 uint64_t xsave_mask_user;
174
175 if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
176 use_xsave = 1;
177 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave);
178 }
179 if (!use_xsave)
180 return;
181
182 cpuid_count(0xd, 0x0, cp);
183 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
184 if ((cp[0] & xsave_mask) != xsave_mask)
185 panic("CPU0 does not support X87 or SSE: %x", cp[0]);
186 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0];
187 xsave_mask_user = xsave_mask;
188 TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user);
189 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
190 xsave_mask &= xsave_mask_user;
191
192 cpuid_count(0xd, 0x1, cp);
193 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) {
194 /*
195 * Patch the XSAVE instruction in the cpu_switch code
196 * to XSAVEOPT. We assume that XSAVE encoding used
197 * REX byte, and set the bit 4 of the r/m byte.
198 */
199 ctx_switch_xsave[3] |= 0x10;
200 }
201 }
202
203 /*
204 * Calculate the fpu save area size.
205 */
206 static void
207 fpuinit_bsp2(void)
208 {
209 u_int cp[4];
210
211 if (use_xsave) {
212 cpuid_count(0xd, 0x0, cp);
213 cpu_max_ext_state_size = cp[1];
214
215 /*
216 * Reload the cpu_feature2, since we enabled OSXSAVE.
217 */
218 do_cpuid(1, cp);
219 cpu_feature2 = cp[2];
220 } else
221 cpu_max_ext_state_size = sizeof(struct savefpu);
222 }
223
224 /*
225 * Initialize the floating point unit.
226 */
227 void
228 fpuinit(void)
229 {
230 register_t saveintr;
231 u_int mxcsr;
232 u_short control;
233
234 if (IS_BSP())
235 fpuinit_bsp1();
236
237 if (use_xsave) {
238 load_cr4(rcr4() | CR4_XSAVE);
239 load_xcr(XCR0, xsave_mask);
240 }
241
242 /*
243 * XCR0 shall be set up before CPU can report the save area size.
244 */
245 if (IS_BSP())
246 fpuinit_bsp2();
247
248 /*
249 * It is too early for critical_enter() to work on AP.
250 */
251 saveintr = intr_disable();
252 stop_emulating();
253 fninit();
254 control = __INITIAL_FPUCW__;
255 fldcw(control);
256 mxcsr = __INITIAL_MXCSR__;
257 ldmxcsr(mxcsr);
258 start_emulating();
259 intr_restore(saveintr);
260 }
261
262 /*
263 * On the boot CPU we generate a clean state that is used to
264 * initialize the floating point unit when it is first used by a
265 * process.
266 */
267 static void
268 fpuinitstate(void *arg __unused)
269 {
270 register_t saveintr;
271 int cp[4], i, max_ext_n;
272
273 fpu_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF,
274 M_WAITOK | M_ZERO);
275 saveintr = intr_disable();
276 stop_emulating();
277
278 fpusave(fpu_initialstate);
279 if (fpu_initialstate->sv_env.en_mxcsr_mask)
280 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask;
281 else
282 cpu_mxcsr_mask = 0xFFBF;
283
284 /*
285 * The fninit instruction does not modify XMM registers. The
286 * fpusave call dumped the garbage contained in the registers
287 * after reset to the initial state saved. Clear XMM
288 * registers file image to make the startup program state and
289 * signal handler XMM register content predictable.
290 */
291 bzero(&fpu_initialstate->sv_xmm[0], sizeof(struct xmmacc));
292
293 /*
294 * Create a table describing the layout of the CPU Extended
295 * Save Area.
296 */
297 if (use_xsave) {
298 max_ext_n = flsl(xsave_mask);
299 xsave_area_desc = malloc(max_ext_n * sizeof(struct
300 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO);
301 /* x87 state */
302 xsave_area_desc[0].offset = 0;
303 xsave_area_desc[0].size = 160;
304 /* XMM */
305 xsave_area_desc[1].offset = 160;
306 xsave_area_desc[1].size = 288 - 160;
307
308 for (i = 2; i < max_ext_n; i++) {
309 cpuid_count(0xd, i, cp);
310 xsave_area_desc[i].offset = cp[1];
311 xsave_area_desc[i].size = cp[0];
312 }
313 }
314
315 fpu_save_area_zone = uma_zcreate("FPU_save_area",
316 cpu_max_ext_state_size, NULL, NULL, NULL, NULL,
317 XSAVE_AREA_ALIGN - 1, 0);
318
319 start_emulating();
320 intr_restore(saveintr);
321 }
322 SYSINIT(fpuinitstate, SI_SUB_DRIVERS, SI_ORDER_ANY, fpuinitstate, NULL);
323
324 /*
325 * Free coprocessor (if we have it).
326 */
327 void
328 fpuexit(struct thread *td)
329 {
330
331 critical_enter();
332 if (curthread == PCPU_GET(fpcurthread)) {
333 stop_emulating();
334 fpusave(curpcb->pcb_save);
335 start_emulating();
336 PCPU_SET(fpcurthread, 0);
337 }
338 critical_exit();
339 }
340
341 int
342 fpuformat()
343 {
344
345 return (_MC_FPFMT_XMM);
346 }
347
348 /*
349 * The following mechanism is used to ensure that the FPE_... value
350 * that is passed as a trapcode to the signal handler of the user
351 * process does not have more than one bit set.
352 *
353 * Multiple bits may be set if the user process modifies the control
354 * word while a status word bit is already set. While this is a sign
355 * of bad coding, we have no choise than to narrow them down to one
356 * bit, since we must not send a trapcode that is not exactly one of
357 * the FPE_ macros.
358 *
359 * The mechanism has a static table with 127 entries. Each combination
360 * of the 7 FPU status word exception bits directly translates to a
361 * position in this table, where a single FPE_... value is stored.
362 * This FPE_... value stored there is considered the "most important"
363 * of the exception bits and will be sent as the signal code. The
364 * precedence of the bits is based upon Intel Document "Numerical
365 * Applications", Chapter "Special Computational Situations".
366 *
367 * The macro to choose one of these values does these steps: 1) Throw
368 * away status word bits that cannot be masked. 2) Throw away the bits
369 * currently masked in the control word, assuming the user isn't
370 * interested in them anymore. 3) Reinsert status word bit 7 (stack
371 * fault) if it is set, which cannot be masked but must be presered.
372 * 4) Use the remaining bits to point into the trapcode table.
373 *
374 * The 6 maskable bits in order of their preference, as stated in the
375 * above referenced Intel manual:
376 * 1 Invalid operation (FP_X_INV)
377 * 1a Stack underflow
378 * 1b Stack overflow
379 * 1c Operand of unsupported format
380 * 1d SNaN operand.
381 * 2 QNaN operand (not an exception, irrelavant here)
382 * 3 Any other invalid-operation not mentioned above or zero divide
383 * (FP_X_INV, FP_X_DZ)
384 * 4 Denormal operand (FP_X_DNML)
385 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
386 * 6 Inexact result (FP_X_IMP)
387 */
388 static char fpetable[128] = {
389 0,
390 FPE_FLTINV, /* 1 - INV */
391 FPE_FLTUND, /* 2 - DNML */
392 FPE_FLTINV, /* 3 - INV | DNML */
393 FPE_FLTDIV, /* 4 - DZ */
394 FPE_FLTINV, /* 5 - INV | DZ */
395 FPE_FLTDIV, /* 6 - DNML | DZ */
396 FPE_FLTINV, /* 7 - INV | DNML | DZ */
397 FPE_FLTOVF, /* 8 - OFL */
398 FPE_FLTINV, /* 9 - INV | OFL */
399 FPE_FLTUND, /* A - DNML | OFL */
400 FPE_FLTINV, /* B - INV | DNML | OFL */
401 FPE_FLTDIV, /* C - DZ | OFL */
402 FPE_FLTINV, /* D - INV | DZ | OFL */
403 FPE_FLTDIV, /* E - DNML | DZ | OFL */
404 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
405 FPE_FLTUND, /* 10 - UFL */
406 FPE_FLTINV, /* 11 - INV | UFL */
407 FPE_FLTUND, /* 12 - DNML | UFL */
408 FPE_FLTINV, /* 13 - INV | DNML | UFL */
409 FPE_FLTDIV, /* 14 - DZ | UFL */
410 FPE_FLTINV, /* 15 - INV | DZ | UFL */
411 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
412 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
413 FPE_FLTOVF, /* 18 - OFL | UFL */
414 FPE_FLTINV, /* 19 - INV | OFL | UFL */
415 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
416 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
417 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
418 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
419 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
420 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
421 FPE_FLTRES, /* 20 - IMP */
422 FPE_FLTINV, /* 21 - INV | IMP */
423 FPE_FLTUND, /* 22 - DNML | IMP */
424 FPE_FLTINV, /* 23 - INV | DNML | IMP */
425 FPE_FLTDIV, /* 24 - DZ | IMP */
426 FPE_FLTINV, /* 25 - INV | DZ | IMP */
427 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
428 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
429 FPE_FLTOVF, /* 28 - OFL | IMP */
430 FPE_FLTINV, /* 29 - INV | OFL | IMP */
431 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
432 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
433 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
434 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
435 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
436 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
437 FPE_FLTUND, /* 30 - UFL | IMP */
438 FPE_FLTINV, /* 31 - INV | UFL | IMP */
439 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
440 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
441 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
442 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
443 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
444 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
445 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
446 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
447 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
448 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
449 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
450 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
451 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
452 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
453 FPE_FLTSUB, /* 40 - STK */
454 FPE_FLTSUB, /* 41 - INV | STK */
455 FPE_FLTUND, /* 42 - DNML | STK */
456 FPE_FLTSUB, /* 43 - INV | DNML | STK */
457 FPE_FLTDIV, /* 44 - DZ | STK */
458 FPE_FLTSUB, /* 45 - INV | DZ | STK */
459 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
460 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
461 FPE_FLTOVF, /* 48 - OFL | STK */
462 FPE_FLTSUB, /* 49 - INV | OFL | STK */
463 FPE_FLTUND, /* 4A - DNML | OFL | STK */
464 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
465 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
466 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
467 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
468 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
469 FPE_FLTUND, /* 50 - UFL | STK */
470 FPE_FLTSUB, /* 51 - INV | UFL | STK */
471 FPE_FLTUND, /* 52 - DNML | UFL | STK */
472 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
473 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
474 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
475 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
476 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
477 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
478 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
479 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
480 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
481 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
482 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
483 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
484 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
485 FPE_FLTRES, /* 60 - IMP | STK */
486 FPE_FLTSUB, /* 61 - INV | IMP | STK */
487 FPE_FLTUND, /* 62 - DNML | IMP | STK */
488 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
489 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
490 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
491 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
492 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
493 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
494 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
495 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
496 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
497 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
498 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
499 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
500 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
501 FPE_FLTUND, /* 70 - UFL | IMP | STK */
502 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
503 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
504 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
505 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
506 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
507 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
508 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
509 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
510 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
511 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
512 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
513 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
514 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
515 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
516 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
517 };
518
519 /*
520 * Read the FP status and control words, then generate si_code value
521 * for SIGFPE. The error code chosen will be one of the
522 * FPE_... macros. It will be sent as the second argument to old
523 * BSD-style signal handlers and as "siginfo_t->si_code" (second
524 * argument) to SA_SIGINFO signal handlers.
525 *
526 * Some time ago, we cleared the x87 exceptions with FNCLEX there.
527 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The
528 * usermode code which understands the FPU hardware enough to enable
529 * the exceptions, can also handle clearing the exception state in the
530 * handler. The only consequence of not clearing the exception is the
531 * rethrow of the SIGFPE on return from the signal handler and
532 * reexecution of the corresponding instruction.
533 *
534 * For XMM traps, the exceptions were never cleared.
535 */
536 int
537 fputrap_x87(void)
538 {
539 struct savefpu *pcb_save;
540 u_short control, status;
541
542 critical_enter();
543
544 /*
545 * Interrupt handling (for another interrupt) may have pushed the
546 * state to memory. Fetch the relevant parts of the state from
547 * wherever they are.
548 */
549 if (PCPU_GET(fpcurthread) != curthread) {
550 pcb_save = curpcb->pcb_save;
551 control = pcb_save->sv_env.en_cw;
552 status = pcb_save->sv_env.en_sw;
553 } else {
554 fnstcw(&control);
555 fnstsw(&status);
556 }
557
558 critical_exit();
559 return (fpetable[status & ((~control & 0x3f) | 0x40)]);
560 }
561
562 int
563 fputrap_sse(void)
564 {
565 u_int mxcsr;
566
567 critical_enter();
568 if (PCPU_GET(fpcurthread) != curthread)
569 mxcsr = curpcb->pcb_save->sv_env.en_mxcsr;
570 else
571 stmxcsr(&mxcsr);
572 critical_exit();
573 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]);
574 }
575
576 /*
577 * Implement device not available (DNA) exception
578 *
579 * It would be better to switch FP context here (if curthread != fpcurthread)
580 * and not necessarily for every context switch, but it is too hard to
581 * access foreign pcb's.
582 */
583
584 static int err_count = 0;
585
586 void
587 fpudna(void)
588 {
589
590 critical_enter();
591 if (PCPU_GET(fpcurthread) == curthread) {
592 printf("fpudna: fpcurthread == curthread %d times\n",
593 ++err_count);
594 stop_emulating();
595 critical_exit();
596 return;
597 }
598 if (PCPU_GET(fpcurthread) != NULL) {
599 printf("fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n",
600 PCPU_GET(fpcurthread),
601 PCPU_GET(fpcurthread)->td_proc->p_pid,
602 curthread, curthread->td_proc->p_pid);
603 panic("fpudna");
604 }
605 stop_emulating();
606 /*
607 * Record new context early in case frstor causes a trap.
608 */
609 PCPU_SET(fpcurthread, curthread);
610
611 fpu_clean_state();
612
613 if ((curpcb->pcb_flags & PCB_FPUINITDONE) == 0) {
614 /*
615 * This is the first time this thread has used the FPU or
616 * the PCB doesn't contain a clean FPU state. Explicitly
617 * load an initial state.
618 *
619 * We prefer to restore the state from the actual save
620 * area in PCB instead of directly loading from
621 * fpu_initialstate, to ignite the XSAVEOPT
622 * tracking engine.
623 */
624 bcopy(fpu_initialstate, curpcb->pcb_save, cpu_max_ext_state_size);
625 fpurestore(curpcb->pcb_save);
626 if (curpcb->pcb_initial_fpucw != __INITIAL_FPUCW__)
627 fldcw(curpcb->pcb_initial_fpucw);
628 if (PCB_USER_FPU(curpcb))
629 set_pcb_flags(curpcb,
630 PCB_FPUINITDONE | PCB_USERFPUINITDONE);
631 else
632 set_pcb_flags(curpcb, PCB_FPUINITDONE);
633 } else
634 fpurestore(curpcb->pcb_save);
635 critical_exit();
636 }
637
638 void
639 fpudrop()
640 {
641 struct thread *td;
642
643 td = PCPU_GET(fpcurthread);
644 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread"));
645 CRITICAL_ASSERT(td);
646 PCPU_SET(fpcurthread, NULL);
647 clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE);
648 start_emulating();
649 }
650
651 /*
652 * Get the user state of the FPU into pcb->pcb_user_save without
653 * dropping ownership (if possible). It returns the FPU ownership
654 * status.
655 */
656 int
657 fpugetregs(struct thread *td)
658 {
659 struct pcb *pcb;
660 uint64_t *xstate_bv, bit;
661 char *sa;
662 int max_ext_n, i, owned;
663
664 pcb = td->td_pcb;
665 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) {
666 bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb),
667 cpu_max_ext_state_size);
668 get_pcb_user_save_pcb(pcb)->sv_env.en_cw =
669 pcb->pcb_initial_fpucw;
670 fpuuserinited(td);
671 return (_MC_FPOWNED_PCB);
672 }
673 critical_enter();
674 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
675 fpusave(get_pcb_user_save_pcb(pcb));
676 owned = _MC_FPOWNED_FPU;
677 } else {
678 owned = _MC_FPOWNED_PCB;
679 }
680 critical_exit();
681 if (use_xsave) {
682 /*
683 * Handle partially saved state.
684 */
685 sa = (char *)get_pcb_user_save_pcb(pcb);
686 xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) +
687 offsetof(struct xstate_hdr, xstate_bv));
688 max_ext_n = flsl(xsave_mask);
689 for (i = 0; i < max_ext_n; i++) {
690 bit = 1ULL << i;
691 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0)
692 continue;
693 bcopy((char *)fpu_initialstate +
694 xsave_area_desc[i].offset,
695 sa + xsave_area_desc[i].offset,
696 xsave_area_desc[i].size);
697 *xstate_bv |= bit;
698 }
699 }
700 return (owned);
701 }
702
703 void
704 fpuuserinited(struct thread *td)
705 {
706 struct pcb *pcb;
707
708 pcb = td->td_pcb;
709 if (PCB_USER_FPU(pcb))
710 set_pcb_flags(pcb,
711 PCB_FPUINITDONE | PCB_USERFPUINITDONE);
712 else
713 set_pcb_flags(pcb, PCB_FPUINITDONE);
714 }
715
716 int
717 fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size)
718 {
719 struct xstate_hdr *hdr, *ehdr;
720 size_t len, max_len;
721 uint64_t bv;
722
723 /* XXXKIB should we clear all extended state in xstate_bv instead ? */
724 if (xfpustate == NULL)
725 return (0);
726 if (!use_xsave)
727 return (EOPNOTSUPP);
728
729 len = xfpustate_size;
730 if (len < sizeof(struct xstate_hdr))
731 return (EINVAL);
732 max_len = cpu_max_ext_state_size - sizeof(struct savefpu);
733 if (len > max_len)
734 return (EINVAL);
735
736 ehdr = (struct xstate_hdr *)xfpustate;
737 bv = ehdr->xstate_bv;
738
739 /*
740 * Avoid #gp.
741 */
742 if (bv & ~xsave_mask)
743 return (EINVAL);
744
745 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1);
746
747 hdr->xstate_bv = bv;
748 bcopy(xfpustate + sizeof(struct xstate_hdr),
749 (char *)(hdr + 1), len - sizeof(struct xstate_hdr));
750
751 return (0);
752 }
753
754 /*
755 * Set the state of the FPU.
756 */
757 int
758 fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate,
759 size_t xfpustate_size)
760 {
761 struct pcb *pcb;
762 int error;
763
764 pcb = td->td_pcb;
765 critical_enter();
766 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
767 error = fpusetxstate(td, xfpustate, xfpustate_size);
768 if (error != 0) {
769 critical_exit();
770 return (error);
771 }
772 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
773 fpurestore(get_pcb_user_save_td(td));
774 critical_exit();
775 set_pcb_flags(pcb, PCB_FPUINITDONE | PCB_USERFPUINITDONE);
776 } else {
777 critical_exit();
778 error = fpusetxstate(td, xfpustate, xfpustate_size);
779 if (error != 0)
780 return (error);
781 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
782 fpuuserinited(td);
783 }
784 return (0);
785 }
786
787 /*
788 * On AuthenticAMD processors, the fxrstor instruction does not restore
789 * the x87's stored last instruction pointer, last data pointer, and last
790 * opcode values, except in the rare case in which the exception summary
791 * (ES) bit in the x87 status word is set to 1.
792 *
793 * In order to avoid leaking this information across processes, we clean
794 * these values by performing a dummy load before executing fxrstor().
795 */
796 static void
797 fpu_clean_state(void)
798 {
799 static float dummy_variable = 0.0;
800 u_short status;
801
802 /*
803 * Clear the ES bit in the x87 status word if it is currently
804 * set, in order to avoid causing a fault in the upcoming load.
805 */
806 fnstsw(&status);
807 if (status & 0x80)
808 fnclex();
809
810 /*
811 * Load the dummy variable into the x87 stack. This mangles
812 * the x87 stack, but we don't care since we're about to call
813 * fxrstor() anyway.
814 */
815 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable));
816 }
817
818 /*
819 * This really sucks. We want the acpi version only, but it requires
820 * the isa_if.h file in order to get the definitions.
821 */
822 #include "opt_isa.h"
823 #ifdef DEV_ISA
824 #include <isa/isavar.h>
825 /*
826 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
827 */
828 static struct isa_pnp_id fpupnp_ids[] = {
829 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
830 { 0 }
831 };
832
833 static int
834 fpupnp_probe(device_t dev)
835 {
836 int result;
837
838 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids);
839 if (result <= 0)
840 device_quiet(dev);
841 return (result);
842 }
843
844 static int
845 fpupnp_attach(device_t dev)
846 {
847
848 return (0);
849 }
850
851 static device_method_t fpupnp_methods[] = {
852 /* Device interface */
853 DEVMETHOD(device_probe, fpupnp_probe),
854 DEVMETHOD(device_attach, fpupnp_attach),
855 DEVMETHOD(device_detach, bus_generic_detach),
856 DEVMETHOD(device_shutdown, bus_generic_shutdown),
857 DEVMETHOD(device_suspend, bus_generic_suspend),
858 DEVMETHOD(device_resume, bus_generic_resume),
859
860 { 0, 0 }
861 };
862
863 static driver_t fpupnp_driver = {
864 "fpupnp",
865 fpupnp_methods,
866 1, /* no softc */
867 };
868
869 static devclass_t fpupnp_devclass;
870
871 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0);
872 #endif /* DEV_ISA */
873
874 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx",
875 "Kernel contexts for FPU state");
876
877 #define FPU_KERN_CTX_FPUINITDONE 0x01
878
879 struct fpu_kern_ctx {
880 struct savefpu *prev;
881 uint32_t flags;
882 char hwstate1[];
883 };
884
885 struct fpu_kern_ctx *
886 fpu_kern_alloc_ctx(u_int flags)
887 {
888 struct fpu_kern_ctx *res;
889 size_t sz;
890
891 sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN +
892 cpu_max_ext_state_size;
893 res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ?
894 M_NOWAIT : M_WAITOK) | M_ZERO);
895 return (res);
896 }
897
898 void
899 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx)
900 {
901
902 /* XXXKIB clear the memory ? */
903 free(ctx, M_FPUKERN_CTX);
904 }
905
906 static struct savefpu *
907 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx)
908 {
909 vm_offset_t p;
910
911 p = (vm_offset_t)&ctx->hwstate1;
912 p = roundup2(p, XSAVE_AREA_ALIGN);
913 return ((struct savefpu *)p);
914 }
915
916 int
917 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags)
918 {
919 struct pcb *pcb;
920
921 pcb = td->td_pcb;
922 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save ==
923 get_pcb_user_save_pcb(pcb), ("mangled pcb_save"));
924 ctx->flags = 0;
925 if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0)
926 ctx->flags |= FPU_KERN_CTX_FPUINITDONE;
927 fpuexit(td);
928 ctx->prev = pcb->pcb_save;
929 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx);
930 set_pcb_flags(pcb, PCB_KERNFPU);
931 clear_pcb_flags(pcb, PCB_FPUINITDONE);
932 return (0);
933 }
934
935 int
936 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx)
937 {
938 struct pcb *pcb;
939
940 pcb = td->td_pcb;
941 critical_enter();
942 if (curthread == PCPU_GET(fpcurthread))
943 fpudrop();
944 critical_exit();
945 pcb->pcb_save = ctx->prev;
946 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) {
947 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) {
948 set_pcb_flags(pcb, PCB_FPUINITDONE);
949 clear_pcb_flags(pcb, PCB_KERNFPU);
950 } else
951 clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU);
952 } else {
953 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0)
954 set_pcb_flags(pcb, PCB_FPUINITDONE);
955 else
956 clear_pcb_flags(pcb, PCB_FPUINITDONE);
957 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave"));
958 }
959 return (0);
960 }
961
962 int
963 fpu_kern_thread(u_int flags)
964 {
965
966 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0,
967 ("Only kthread may use fpu_kern_thread"));
968 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb),
969 ("mangled pcb_save"));
970 KASSERT(PCB_USER_FPU(curpcb), ("recursive call"));
971
972 set_pcb_flags(curpcb, PCB_KERNFPU);
973 return (0);
974 }
975
976 int
977 is_fpu_kern_thread(u_int flags)
978 {
979
980 if ((curthread->td_pflags & TDP_KTHREAD) == 0)
981 return (0);
982 return ((curpcb->pcb_flags & PCB_KERNFPU) != 0);
983 }
984
985 /*
986 * FPU save area alloc/free/init utility routines
987 */
988 struct savefpu *
989 fpu_save_area_alloc(void)
990 {
991
992 return (uma_zalloc(fpu_save_area_zone, 0));
993 }
994
995 void
996 fpu_save_area_free(struct savefpu *fsa)
997 {
998
999 uma_zfree(fpu_save_area_zone, fsa);
1000 }
1001
1002 void
1003 fpu_save_area_reset(struct savefpu *fsa)
1004 {
1005
1006 bcopy(fpu_initialstate, fsa, cpu_max_ext_state_size);
1007 }
Cache object: 824bbb9b801340b3da08992fd70c76f6
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