The Design and Implementation of the FreeBSD Operating System, Second Edition
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sys/amd64/amd64/fpu.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-3-Clause
    3  *
    4  * Copyright (c) 1990 William Jolitz.
    5  * Copyright (c) 1991 The Regents of the University of California.
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. Neither the name of the University nor the names of its contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   30  * SUCH DAMAGE.
   31  *
   32  *      from: @(#)npx.c 7.2 (Berkeley) 5/12/91
   33  */
   34 
   35 #include <sys/cdefs.h>
   36 __FBSDID("$FreeBSD: stable/12/sys/amd64/amd64/fpu.c 349304 2019-06-23 11:09:08Z kib $");
   37 
   38 #include <sys/param.h>
   39 #include <sys/systm.h>
   40 #include <sys/bus.h>
   41 #include <sys/kernel.h>
   42 #include <sys/lock.h>
   43 #include <sys/malloc.h>
   44 #include <sys/module.h>
   45 #include <sys/mutex.h>
   46 #include <sys/mutex.h>
   47 #include <sys/proc.h>
   48 #include <sys/sysctl.h>
   49 #include <machine/bus.h>
   50 #include <sys/rman.h>
   51 #include <sys/signalvar.h>
   52 #include <vm/uma.h>
   53 
   54 #include <machine/cputypes.h>
   55 #include <machine/frame.h>
   56 #include <machine/intr_machdep.h>
   57 #include <machine/md_var.h>
   58 #include <machine/pcb.h>
   59 #include <machine/psl.h>
   60 #include <machine/resource.h>
   61 #include <machine/specialreg.h>
   62 #include <machine/segments.h>
   63 #include <machine/ucontext.h>
   64 #include <x86/ifunc.h>
   65 
   66 /*
   67  * Floating point support.
   68  */
   69 
   70 #if defined(__GNUCLIKE_ASM) && !defined(lint)
   71 
   72 #define fldcw(cw)               __asm __volatile("fldcw %0" : : "m" (cw))
   73 #define fnclex()                __asm __volatile("fnclex")
   74 #define fninit()                __asm __volatile("fninit")
   75 #define fnstcw(addr)            __asm __volatile("fnstcw %0" : "=m" (*(addr)))
   76 #define fnstsw(addr)            __asm __volatile("fnstsw %0" : "=am" (*(addr)))
   77 #define fxrstor(addr)           __asm __volatile("fxrstor %0" : : "m" (*(addr)))
   78 #define fxsave(addr)            __asm __volatile("fxsave %0" : "=m" (*(addr)))
   79 #define ldmxcsr(csr)            __asm __volatile("ldmxcsr %0" : : "m" (csr))
   80 #define stmxcsr(addr)           __asm __volatile("stmxcsr %0" : : "m" (*(addr)))
   81 
   82 static __inline void
   83 xrstor(char *addr, uint64_t mask)
   84 {
   85         uint32_t low, hi;
   86 
   87         low = mask;
   88         hi = mask >> 32;
   89         __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi));
   90 }
   91 
   92 static __inline void
   93 xsave(char *addr, uint64_t mask)
   94 {
   95         uint32_t low, hi;
   96 
   97         low = mask;
   98         hi = mask >> 32;
   99         __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) :
  100             "memory");
  101 }
  102 
  103 static __inline void
  104 xsaveopt(char *addr, uint64_t mask)
  105 {
  106         uint32_t low, hi;
  107 
  108         low = mask;
  109         hi = mask >> 32;
  110         __asm __volatile("xsaveopt %0" : "=m" (*addr) : "a" (low), "d" (hi) :
  111             "memory");
  112 }
  113 
  114 #else   /* !(__GNUCLIKE_ASM && !lint) */
  115 
  116 void    fldcw(u_short cw);
  117 void    fnclex(void);
  118 void    fninit(void);
  119 void    fnstcw(caddr_t addr);
  120 void    fnstsw(caddr_t addr);
  121 void    fxsave(caddr_t addr);
  122 void    fxrstor(caddr_t addr);
  123 void    ldmxcsr(u_int csr);
  124 void    stmxcsr(u_int *csr);
  125 void    xrstor(char *addr, uint64_t mask);
  126 void    xsave(char *addr, uint64_t mask);
  127 void    xsaveopt(char *addr, uint64_t mask);
  128 
  129 #endif  /* __GNUCLIKE_ASM && !lint */
  130 
  131 #define start_emulating()       load_cr0(rcr0() | CR0_TS)
  132 #define stop_emulating()        clts()
  133 
  134 CTASSERT(sizeof(struct savefpu) == 512);
  135 CTASSERT(sizeof(struct xstate_hdr) == 64);
  136 CTASSERT(sizeof(struct savefpu_ymm) == 832);
  137 
  138 /*
  139  * This requirement is to make it easier for asm code to calculate
  140  * offset of the fpu save area from the pcb address. FPU save area
  141  * must be 64-byte aligned.
  142  */
  143 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0);
  144 
  145 /*
  146  * Ensure the copy of XCR0 saved in a core is contained in the padding
  147  * area.
  148  */
  149 CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savefpu, sv_pad) &&
  150     X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savefpu));
  151 
  152 static  void    fpu_clean_state(void);
  153 
  154 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD,
  155     SYSCTL_NULL_INT_PTR, 1, "Floating point instructions executed in hardware");
  156 
  157 int lazy_fpu_switch = 0;
  158 SYSCTL_INT(_hw, OID_AUTO, lazy_fpu_switch, CTLFLAG_RD,
  159     &lazy_fpu_switch, 0,
  160     "Lazily load FPU context after context switch");
  161 
  162 int use_xsave;                  /* non-static for cpu_switch.S */
  163 uint64_t xsave_mask;            /* the same */
  164 static  uma_zone_t fpu_save_area_zone;
  165 static  struct savefpu *fpu_initialstate;
  166 
  167 struct xsave_area_elm_descr {
  168         u_int   offset;
  169         u_int   size;
  170 } *xsave_area_desc;
  171 
  172 static void
  173 fpusave_xsaveopt(void *addr)
  174 {
  175 
  176         xsaveopt((char *)addr, xsave_mask);
  177 }
  178 
  179 static void
  180 fpusave_xsave(void *addr)
  181 {
  182 
  183         xsave((char *)addr, xsave_mask);
  184 }
  185 
  186 static void
  187 fpurestore_xrstor(void *addr)
  188 {
  189 
  190         xrstor((char *)addr, xsave_mask);
  191 }
  192 
  193 static void
  194 fpusave_fxsave(void *addr)
  195 {
  196 
  197         fxsave((char *)addr);
  198 }
  199 
  200 static void
  201 fpurestore_fxrstor(void *addr)
  202 {
  203 
  204         fxrstor((char *)addr);
  205 }
  206 
  207 static void
  208 init_xsave(void)
  209 {
  210 
  211         if (use_xsave)
  212                 return;
  213         if ((cpu_feature2 & CPUID2_XSAVE) == 0)
  214                 return;
  215         use_xsave = 1;
  216         TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave);
  217 }
  218 
  219 DEFINE_IFUNC(, void, fpusave, (void *), static)
  220 {
  221 
  222         init_xsave();
  223         if (use_xsave)
  224                 return ((cpu_stdext_feature & CPUID_EXTSTATE_XSAVEOPT) != 0 ?
  225                     fpusave_xsaveopt : fpusave_xsave);
  226         return (fpusave_fxsave);
  227 }
  228 
  229 DEFINE_IFUNC(, void, fpurestore, (void *), static)
  230 {
  231 
  232         init_xsave();
  233         return (use_xsave ? fpurestore_xrstor : fpurestore_fxrstor);
  234 }
  235 
  236 void
  237 fpususpend(void *addr)
  238 {
  239         u_long cr0;
  240 
  241         cr0 = rcr0();
  242         stop_emulating();
  243         fpusave(addr);
  244         load_cr0(cr0);
  245 }
  246 
  247 void
  248 fpuresume(void *addr)
  249 {
  250         u_long cr0;
  251 
  252         cr0 = rcr0();
  253         stop_emulating();
  254         fninit();
  255         if (use_xsave)
  256                 load_xcr(XCR0, xsave_mask);
  257         fpurestore(addr);
  258         load_cr0(cr0);
  259 }
  260 
  261 /*
  262  * Enable XSAVE if supported and allowed by user.
  263  * Calculate the xsave_mask.
  264  */
  265 static void
  266 fpuinit_bsp1(void)
  267 {
  268         u_int cp[4];
  269         uint64_t xsave_mask_user;
  270         bool old_wp;
  271 
  272         if (!use_xsave)
  273                 return;
  274         cpuid_count(0xd, 0x0, cp);
  275         xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
  276         if ((cp[0] & xsave_mask) != xsave_mask)
  277                 panic("CPU0 does not support X87 or SSE: %x", cp[0]);
  278         xsave_mask = ((uint64_t)cp[3] << 32) | cp[0];
  279         xsave_mask_user = xsave_mask;
  280         TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user);
  281         xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
  282         xsave_mask &= xsave_mask_user;
  283         if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512)
  284                 xsave_mask &= ~XFEATURE_AVX512;
  285         if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX)
  286                 xsave_mask &= ~XFEATURE_MPX;
  287 
  288         cpuid_count(0xd, 0x1, cp);
  289         if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) {
  290                 /*
  291                  * Patch the XSAVE instruction in the cpu_switch code
  292                  * to XSAVEOPT.  We assume that XSAVE encoding used
  293                  * REX byte, and set the bit 4 of the r/m byte.
  294                  *
  295                  * It seems that some BIOSes give control to the OS
  296                  * with CR0.WP already set, making the kernel text
  297                  * read-only before cpu_startup().
  298                  */
  299                 old_wp = disable_wp();
  300                 ctx_switch_xsave[3] |= 0x10;
  301                 restore_wp(old_wp);
  302         }
  303 }
  304 
  305 /*
  306  * Calculate the fpu save area size.
  307  */
  308 static void
  309 fpuinit_bsp2(void)
  310 {
  311         u_int cp[4];
  312 
  313         if (use_xsave) {
  314                 cpuid_count(0xd, 0x0, cp);
  315                 cpu_max_ext_state_size = cp[1];
  316 
  317                 /*
  318                  * Reload the cpu_feature2, since we enabled OSXSAVE.
  319                  */
  320                 do_cpuid(1, cp);
  321                 cpu_feature2 = cp[2];
  322         } else
  323                 cpu_max_ext_state_size = sizeof(struct savefpu);
  324 }
  325 
  326 /*
  327  * Initialize the floating point unit.
  328  */
  329 void
  330 fpuinit(void)
  331 {
  332         register_t saveintr;
  333         u_int mxcsr;
  334         u_short control;
  335 
  336         if (IS_BSP())
  337                 fpuinit_bsp1();
  338 
  339         if (use_xsave) {
  340                 load_cr4(rcr4() | CR4_XSAVE);
  341                 load_xcr(XCR0, xsave_mask);
  342         }
  343 
  344         /*
  345          * XCR0 shall be set up before CPU can report the save area size.
  346          */
  347         if (IS_BSP())
  348                 fpuinit_bsp2();
  349 
  350         /*
  351          * It is too early for critical_enter() to work on AP.
  352          */
  353         saveintr = intr_disable();
  354         stop_emulating();
  355         fninit();
  356         control = __INITIAL_FPUCW__;
  357         fldcw(control);
  358         mxcsr = __INITIAL_MXCSR__;
  359         ldmxcsr(mxcsr);
  360         start_emulating();
  361         intr_restore(saveintr);
  362 }
  363 
  364 /*
  365  * On the boot CPU we generate a clean state that is used to
  366  * initialize the floating point unit when it is first used by a
  367  * process.
  368  */
  369 static void
  370 fpuinitstate(void *arg __unused)
  371 {
  372         uint64_t *xstate_bv;
  373         register_t saveintr;
  374         int cp[4], i, max_ext_n;
  375 
  376         fpu_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF,
  377             M_WAITOK | M_ZERO);
  378         saveintr = intr_disable();
  379         stop_emulating();
  380 
  381         fpusave_fxsave(fpu_initialstate);
  382         if (fpu_initialstate->sv_env.en_mxcsr_mask)
  383                 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask;
  384         else
  385                 cpu_mxcsr_mask = 0xFFBF;
  386 
  387         /*
  388          * The fninit instruction does not modify XMM registers or x87
  389          * registers (MM/ST).  The fpusave call dumped the garbage
  390          * contained in the registers after reset to the initial state
  391          * saved.  Clear XMM and x87 registers file image to make the
  392          * startup program state and signal handler XMM/x87 register
  393          * content predictable.
  394          */
  395         bzero(fpu_initialstate->sv_fp, sizeof(fpu_initialstate->sv_fp));
  396         bzero(fpu_initialstate->sv_xmm, sizeof(fpu_initialstate->sv_xmm));
  397 
  398         /*
  399          * Create a table describing the layout of the CPU Extended
  400          * Save Area.
  401          */
  402         if (use_xsave) {
  403                 xstate_bv = (uint64_t *)((char *)(fpu_initialstate + 1) +
  404                     offsetof(struct xstate_hdr, xstate_bv));
  405                 *xstate_bv = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
  406 
  407                 max_ext_n = flsl(xsave_mask);
  408                 xsave_area_desc = malloc(max_ext_n * sizeof(struct
  409                     xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO);
  410                 /* x87 state */
  411                 xsave_area_desc[0].offset = 0;
  412                 xsave_area_desc[0].size = 160;
  413                 /* XMM */
  414                 xsave_area_desc[1].offset = 160;
  415                 xsave_area_desc[1].size = 288 - 160;
  416 
  417                 for (i = 2; i < max_ext_n; i++) {
  418                         cpuid_count(0xd, i, cp);
  419                         xsave_area_desc[i].offset = cp[1];
  420                         xsave_area_desc[i].size = cp[0];
  421                 }
  422         }
  423 
  424         fpu_save_area_zone = uma_zcreate("FPU_save_area",
  425             cpu_max_ext_state_size, NULL, NULL, NULL, NULL,
  426             XSAVE_AREA_ALIGN - 1, 0);
  427 
  428         start_emulating();
  429         intr_restore(saveintr);
  430 }
  431 /* EFIRT needs this to be initialized before we can enter our EFI environment */
  432 SYSINIT(fpuinitstate, SI_SUB_DRIVERS, SI_ORDER_FIRST, fpuinitstate, NULL);
  433 
  434 /*
  435  * Free coprocessor (if we have it).
  436  */
  437 void
  438 fpuexit(struct thread *td)
  439 {
  440 
  441         critical_enter();
  442         if (curthread == PCPU_GET(fpcurthread)) {
  443                 stop_emulating();
  444                 fpusave(curpcb->pcb_save);
  445                 start_emulating();
  446                 PCPU_SET(fpcurthread, NULL);
  447         }
  448         critical_exit();
  449 }
  450 
  451 int
  452 fpuformat(void)
  453 {
  454 
  455         return (_MC_FPFMT_XMM);
  456 }
  457 
  458 /* 
  459  * The following mechanism is used to ensure that the FPE_... value
  460  * that is passed as a trapcode to the signal handler of the user
  461  * process does not have more than one bit set.
  462  * 
  463  * Multiple bits may be set if the user process modifies the control
  464  * word while a status word bit is already set.  While this is a sign
  465  * of bad coding, we have no choise than to narrow them down to one
  466  * bit, since we must not send a trapcode that is not exactly one of
  467  * the FPE_ macros.
  468  *
  469  * The mechanism has a static table with 127 entries.  Each combination
  470  * of the 7 FPU status word exception bits directly translates to a
  471  * position in this table, where a single FPE_... value is stored.
  472  * This FPE_... value stored there is considered the "most important"
  473  * of the exception bits and will be sent as the signal code.  The
  474  * precedence of the bits is based upon Intel Document "Numerical
  475  * Applications", Chapter "Special Computational Situations".
  476  *
  477  * The macro to choose one of these values does these steps: 1) Throw
  478  * away status word bits that cannot be masked.  2) Throw away the bits
  479  * currently masked in the control word, assuming the user isn't
  480  * interested in them anymore.  3) Reinsert status word bit 7 (stack
  481  * fault) if it is set, which cannot be masked but must be presered.
  482  * 4) Use the remaining bits to point into the trapcode table.
  483  *
  484  * The 6 maskable bits in order of their preference, as stated in the
  485  * above referenced Intel manual:
  486  * 1  Invalid operation (FP_X_INV)
  487  * 1a   Stack underflow
  488  * 1b   Stack overflow
  489  * 1c   Operand of unsupported format
  490  * 1d   SNaN operand.
  491  * 2  QNaN operand (not an exception, irrelavant here)
  492  * 3  Any other invalid-operation not mentioned above or zero divide
  493  *      (FP_X_INV, FP_X_DZ)
  494  * 4  Denormal operand (FP_X_DNML)
  495  * 5  Numeric over/underflow (FP_X_OFL, FP_X_UFL)
  496  * 6  Inexact result (FP_X_IMP) 
  497  */
  498 static char fpetable[128] = {
  499         0,
  500         FPE_FLTINV,     /*  1 - INV */
  501         FPE_FLTUND,     /*  2 - DNML */
  502         FPE_FLTINV,     /*  3 - INV | DNML */
  503         FPE_FLTDIV,     /*  4 - DZ */
  504         FPE_FLTINV,     /*  5 - INV | DZ */
  505         FPE_FLTDIV,     /*  6 - DNML | DZ */
  506         FPE_FLTINV,     /*  7 - INV | DNML | DZ */
  507         FPE_FLTOVF,     /*  8 - OFL */
  508         FPE_FLTINV,     /*  9 - INV | OFL */
  509         FPE_FLTUND,     /*  A - DNML | OFL */
  510         FPE_FLTINV,     /*  B - INV | DNML | OFL */
  511         FPE_FLTDIV,     /*  C - DZ | OFL */
  512         FPE_FLTINV,     /*  D - INV | DZ | OFL */
  513         FPE_FLTDIV,     /*  E - DNML | DZ | OFL */
  514         FPE_FLTINV,     /*  F - INV | DNML | DZ | OFL */
  515         FPE_FLTUND,     /* 10 - UFL */
  516         FPE_FLTINV,     /* 11 - INV | UFL */
  517         FPE_FLTUND,     /* 12 - DNML | UFL */
  518         FPE_FLTINV,     /* 13 - INV | DNML | UFL */
  519         FPE_FLTDIV,     /* 14 - DZ | UFL */
  520         FPE_FLTINV,     /* 15 - INV | DZ | UFL */
  521         FPE_FLTDIV,     /* 16 - DNML | DZ | UFL */
  522         FPE_FLTINV,     /* 17 - INV | DNML | DZ | UFL */
  523         FPE_FLTOVF,     /* 18 - OFL | UFL */
  524         FPE_FLTINV,     /* 19 - INV | OFL | UFL */
  525         FPE_FLTUND,     /* 1A - DNML | OFL | UFL */
  526         FPE_FLTINV,     /* 1B - INV | DNML | OFL | UFL */
  527         FPE_FLTDIV,     /* 1C - DZ | OFL | UFL */
  528         FPE_FLTINV,     /* 1D - INV | DZ | OFL | UFL */
  529         FPE_FLTDIV,     /* 1E - DNML | DZ | OFL | UFL */
  530         FPE_FLTINV,     /* 1F - INV | DNML | DZ | OFL | UFL */
  531         FPE_FLTRES,     /* 20 - IMP */
  532         FPE_FLTINV,     /* 21 - INV | IMP */
  533         FPE_FLTUND,     /* 22 - DNML | IMP */
  534         FPE_FLTINV,     /* 23 - INV | DNML | IMP */
  535         FPE_FLTDIV,     /* 24 - DZ | IMP */
  536         FPE_FLTINV,     /* 25 - INV | DZ | IMP */
  537         FPE_FLTDIV,     /* 26 - DNML | DZ | IMP */
  538         FPE_FLTINV,     /* 27 - INV | DNML | DZ | IMP */
  539         FPE_FLTOVF,     /* 28 - OFL | IMP */
  540         FPE_FLTINV,     /* 29 - INV | OFL | IMP */
  541         FPE_FLTUND,     /* 2A - DNML | OFL | IMP */
  542         FPE_FLTINV,     /* 2B - INV | DNML | OFL | IMP */
  543         FPE_FLTDIV,     /* 2C - DZ | OFL | IMP */
  544         FPE_FLTINV,     /* 2D - INV | DZ | OFL | IMP */
  545         FPE_FLTDIV,     /* 2E - DNML | DZ | OFL | IMP */
  546         FPE_FLTINV,     /* 2F - INV | DNML | DZ | OFL | IMP */
  547         FPE_FLTUND,     /* 30 - UFL | IMP */
  548         FPE_FLTINV,     /* 31 - INV | UFL | IMP */
  549         FPE_FLTUND,     /* 32 - DNML | UFL | IMP */
  550         FPE_FLTINV,     /* 33 - INV | DNML | UFL | IMP */
  551         FPE_FLTDIV,     /* 34 - DZ | UFL | IMP */
  552         FPE_FLTINV,     /* 35 - INV | DZ | UFL | IMP */
  553         FPE_FLTDIV,     /* 36 - DNML | DZ | UFL | IMP */
  554         FPE_FLTINV,     /* 37 - INV | DNML | DZ | UFL | IMP */
  555         FPE_FLTOVF,     /* 38 - OFL | UFL | IMP */
  556         FPE_FLTINV,     /* 39 - INV | OFL | UFL | IMP */
  557         FPE_FLTUND,     /* 3A - DNML | OFL | UFL | IMP */
  558         FPE_FLTINV,     /* 3B - INV | DNML | OFL | UFL | IMP */
  559         FPE_FLTDIV,     /* 3C - DZ | OFL | UFL | IMP */
  560         FPE_FLTINV,     /* 3D - INV | DZ | OFL | UFL | IMP */
  561         FPE_FLTDIV,     /* 3E - DNML | DZ | OFL | UFL | IMP */
  562         FPE_FLTINV,     /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
  563         FPE_FLTSUB,     /* 40 - STK */
  564         FPE_FLTSUB,     /* 41 - INV | STK */
  565         FPE_FLTUND,     /* 42 - DNML | STK */
  566         FPE_FLTSUB,     /* 43 - INV | DNML | STK */
  567         FPE_FLTDIV,     /* 44 - DZ | STK */
  568         FPE_FLTSUB,     /* 45 - INV | DZ | STK */
  569         FPE_FLTDIV,     /* 46 - DNML | DZ | STK */
  570         FPE_FLTSUB,     /* 47 - INV | DNML | DZ | STK */
  571         FPE_FLTOVF,     /* 48 - OFL | STK */
  572         FPE_FLTSUB,     /* 49 - INV | OFL | STK */
  573         FPE_FLTUND,     /* 4A - DNML | OFL | STK */
  574         FPE_FLTSUB,     /* 4B - INV | DNML | OFL | STK */
  575         FPE_FLTDIV,     /* 4C - DZ | OFL | STK */
  576         FPE_FLTSUB,     /* 4D - INV | DZ | OFL | STK */
  577         FPE_FLTDIV,     /* 4E - DNML | DZ | OFL | STK */
  578         FPE_FLTSUB,     /* 4F - INV | DNML | DZ | OFL | STK */
  579         FPE_FLTUND,     /* 50 - UFL | STK */
  580         FPE_FLTSUB,     /* 51 - INV | UFL | STK */
  581         FPE_FLTUND,     /* 52 - DNML | UFL | STK */
  582         FPE_FLTSUB,     /* 53 - INV | DNML | UFL | STK */
  583         FPE_FLTDIV,     /* 54 - DZ | UFL | STK */
  584         FPE_FLTSUB,     /* 55 - INV | DZ | UFL | STK */
  585         FPE_FLTDIV,     /* 56 - DNML | DZ | UFL | STK */
  586         FPE_FLTSUB,     /* 57 - INV | DNML | DZ | UFL | STK */
  587         FPE_FLTOVF,     /* 58 - OFL | UFL | STK */
  588         FPE_FLTSUB,     /* 59 - INV | OFL | UFL | STK */
  589         FPE_FLTUND,     /* 5A - DNML | OFL | UFL | STK */
  590         FPE_FLTSUB,     /* 5B - INV | DNML | OFL | UFL | STK */
  591         FPE_FLTDIV,     /* 5C - DZ | OFL | UFL | STK */
  592         FPE_FLTSUB,     /* 5D - INV | DZ | OFL | UFL | STK */
  593         FPE_FLTDIV,     /* 5E - DNML | DZ | OFL | UFL | STK */
  594         FPE_FLTSUB,     /* 5F - INV | DNML | DZ | OFL | UFL | STK */
  595         FPE_FLTRES,     /* 60 - IMP | STK */
  596         FPE_FLTSUB,     /* 61 - INV | IMP | STK */
  597         FPE_FLTUND,     /* 62 - DNML | IMP | STK */
  598         FPE_FLTSUB,     /* 63 - INV | DNML | IMP | STK */
  599         FPE_FLTDIV,     /* 64 - DZ | IMP | STK */
  600         FPE_FLTSUB,     /* 65 - INV | DZ | IMP | STK */
  601         FPE_FLTDIV,     /* 66 - DNML | DZ | IMP | STK */
  602         FPE_FLTSUB,     /* 67 - INV | DNML | DZ | IMP | STK */
  603         FPE_FLTOVF,     /* 68 - OFL | IMP | STK */
  604         FPE_FLTSUB,     /* 69 - INV | OFL | IMP | STK */
  605         FPE_FLTUND,     /* 6A - DNML | OFL | IMP | STK */
  606         FPE_FLTSUB,     /* 6B - INV | DNML | OFL | IMP | STK */
  607         FPE_FLTDIV,     /* 6C - DZ | OFL | IMP | STK */
  608         FPE_FLTSUB,     /* 6D - INV | DZ | OFL | IMP | STK */
  609         FPE_FLTDIV,     /* 6E - DNML | DZ | OFL | IMP | STK */
  610         FPE_FLTSUB,     /* 6F - INV | DNML | DZ | OFL | IMP | STK */
  611         FPE_FLTUND,     /* 70 - UFL | IMP | STK */
  612         FPE_FLTSUB,     /* 71 - INV | UFL | IMP | STK */
  613         FPE_FLTUND,     /* 72 - DNML | UFL | IMP | STK */
  614         FPE_FLTSUB,     /* 73 - INV | DNML | UFL | IMP | STK */
  615         FPE_FLTDIV,     /* 74 - DZ | UFL | IMP | STK */
  616         FPE_FLTSUB,     /* 75 - INV | DZ | UFL | IMP | STK */
  617         FPE_FLTDIV,     /* 76 - DNML | DZ | UFL | IMP | STK */
  618         FPE_FLTSUB,     /* 77 - INV | DNML | DZ | UFL | IMP | STK */
  619         FPE_FLTOVF,     /* 78 - OFL | UFL | IMP | STK */
  620         FPE_FLTSUB,     /* 79 - INV | OFL | UFL | IMP | STK */
  621         FPE_FLTUND,     /* 7A - DNML | OFL | UFL | IMP | STK */
  622         FPE_FLTSUB,     /* 7B - INV | DNML | OFL | UFL | IMP | STK */
  623         FPE_FLTDIV,     /* 7C - DZ | OFL | UFL | IMP | STK */
  624         FPE_FLTSUB,     /* 7D - INV | DZ | OFL | UFL | IMP | STK */
  625         FPE_FLTDIV,     /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
  626         FPE_FLTSUB,     /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
  627 };
  628 
  629 /*
  630  * Read the FP status and control words, then generate si_code value
  631  * for SIGFPE.  The error code chosen will be one of the
  632  * FPE_... macros.  It will be sent as the second argument to old
  633  * BSD-style signal handlers and as "siginfo_t->si_code" (second
  634  * argument) to SA_SIGINFO signal handlers.
  635  *
  636  * Some time ago, we cleared the x87 exceptions with FNCLEX there.
  637  * Clearing exceptions was necessary mainly to avoid IRQ13 bugs.  The
  638  * usermode code which understands the FPU hardware enough to enable
  639  * the exceptions, can also handle clearing the exception state in the
  640  * handler.  The only consequence of not clearing the exception is the
  641  * rethrow of the SIGFPE on return from the signal handler and
  642  * reexecution of the corresponding instruction.
  643  *
  644  * For XMM traps, the exceptions were never cleared.
  645  */
  646 int
  647 fputrap_x87(void)
  648 {
  649         struct savefpu *pcb_save;
  650         u_short control, status;
  651 
  652         critical_enter();
  653 
  654         /*
  655          * Interrupt handling (for another interrupt) may have pushed the
  656          * state to memory.  Fetch the relevant parts of the state from
  657          * wherever they are.
  658          */
  659         if (PCPU_GET(fpcurthread) != curthread) {
  660                 pcb_save = curpcb->pcb_save;
  661                 control = pcb_save->sv_env.en_cw;
  662                 status = pcb_save->sv_env.en_sw;
  663         } else {
  664                 fnstcw(&control);
  665                 fnstsw(&status);
  666         }
  667 
  668         critical_exit();
  669         return (fpetable[status & ((~control & 0x3f) | 0x40)]);
  670 }
  671 
  672 int
  673 fputrap_sse(void)
  674 {
  675         u_int mxcsr;
  676 
  677         critical_enter();
  678         if (PCPU_GET(fpcurthread) != curthread)
  679                 mxcsr = curpcb->pcb_save->sv_env.en_mxcsr;
  680         else
  681                 stmxcsr(&mxcsr);
  682         critical_exit();
  683         return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]);
  684 }
  685 
  686 static void
  687 restore_fpu_curthread(struct thread *td)
  688 {
  689         struct pcb *pcb;
  690 
  691         /*
  692          * Record new context early in case frstor causes a trap.
  693          */
  694         PCPU_SET(fpcurthread, td);
  695 
  696         stop_emulating();
  697         fpu_clean_state();
  698         pcb = td->td_pcb;
  699 
  700         if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) {
  701                 /*
  702                  * This is the first time this thread has used the FPU or
  703                  * the PCB doesn't contain a clean FPU state.  Explicitly
  704                  * load an initial state.
  705                  *
  706                  * We prefer to restore the state from the actual save
  707                  * area in PCB instead of directly loading from
  708                  * fpu_initialstate, to ignite the XSAVEOPT
  709                  * tracking engine.
  710                  */
  711                 bcopy(fpu_initialstate, pcb->pcb_save,
  712                     cpu_max_ext_state_size);
  713                 fpurestore(pcb->pcb_save);
  714                 if (pcb->pcb_initial_fpucw != __INITIAL_FPUCW__)
  715                         fldcw(pcb->pcb_initial_fpucw);
  716                 if (PCB_USER_FPU(pcb))
  717                         set_pcb_flags(pcb, PCB_FPUINITDONE |
  718                             PCB_USERFPUINITDONE);
  719                 else
  720                         set_pcb_flags(pcb, PCB_FPUINITDONE);
  721         } else
  722                 fpurestore(pcb->pcb_save);
  723 }
  724 
  725 /*
  726  * Device Not Available (DNA, #NM) exception handler.
  727  *
  728  * It would be better to switch FP context here (if curthread !=
  729  * fpcurthread) and not necessarily for every context switch, but it
  730  * is too hard to access foreign pcb's.
  731  */
  732 void
  733 fpudna(void)
  734 {
  735         struct thread *td;
  736 
  737         td = curthread;
  738         /*
  739          * This handler is entered with interrupts enabled, so context
  740          * switches may occur before critical_enter() is executed.  If
  741          * a context switch occurs, then when we regain control, our
  742          * state will have been completely restored.  The CPU may
  743          * change underneath us, but the only part of our context that
  744          * lives in the CPU is CR0.TS and that will be "restored" by
  745          * setting it on the new CPU.
  746          */
  747         critical_enter();
  748 
  749         KASSERT((curpcb->pcb_flags & PCB_FPUNOSAVE) == 0,
  750             ("fpudna while in fpu_kern_enter(FPU_KERN_NOCTX)"));
  751         if (__predict_false(PCPU_GET(fpcurthread) == td)) {
  752                 /*
  753                  * Some virtual machines seems to set %cr0.TS at
  754                  * arbitrary moments.  Silently clear the TS bit
  755                  * regardless of the eager/lazy FPU context switch
  756                  * mode.
  757                  */
  758                 stop_emulating();
  759         } else {
  760                 if (__predict_false(PCPU_GET(fpcurthread) != NULL)) {
  761                         panic(
  762                     "fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n",
  763                             PCPU_GET(fpcurthread),
  764                             PCPU_GET(fpcurthread)->td_tid, td, td->td_tid);
  765                 }
  766                 restore_fpu_curthread(td);
  767         }
  768         critical_exit();
  769 }
  770 
  771 void fpu_activate_sw(struct thread *td); /* Called from the context switch */
  772 void
  773 fpu_activate_sw(struct thread *td)
  774 {
  775 
  776         if ((td->td_pflags & TDP_KTHREAD) != 0 || !PCB_USER_FPU(td->td_pcb)) {
  777                 PCPU_SET(fpcurthread, NULL);
  778                 start_emulating();
  779         } else if (PCPU_GET(fpcurthread) != td) {
  780                 restore_fpu_curthread(td);
  781         }
  782 }
  783 
  784 void
  785 fpudrop(void)
  786 {
  787         struct thread *td;
  788 
  789         td = PCPU_GET(fpcurthread);
  790         KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread"));
  791         CRITICAL_ASSERT(td);
  792         PCPU_SET(fpcurthread, NULL);
  793         clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE);
  794         start_emulating();
  795 }
  796 
  797 /*
  798  * Get the user state of the FPU into pcb->pcb_user_save without
  799  * dropping ownership (if possible).  It returns the FPU ownership
  800  * status.
  801  */
  802 int
  803 fpugetregs(struct thread *td)
  804 {
  805         struct pcb *pcb;
  806         uint64_t *xstate_bv, bit;
  807         char *sa;
  808         int max_ext_n, i, owned;
  809 
  810         pcb = td->td_pcb;
  811         critical_enter();
  812         if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) {
  813                 bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb),
  814                     cpu_max_ext_state_size);
  815                 get_pcb_user_save_pcb(pcb)->sv_env.en_cw =
  816                     pcb->pcb_initial_fpucw;
  817                 fpuuserinited(td);
  818                 critical_exit();
  819                 return (_MC_FPOWNED_PCB);
  820         }
  821         if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
  822                 fpusave(get_pcb_user_save_pcb(pcb));
  823                 owned = _MC_FPOWNED_FPU;
  824         } else {
  825                 owned = _MC_FPOWNED_PCB;
  826         }
  827         if (use_xsave) {
  828                 /*
  829                  * Handle partially saved state.
  830                  */
  831                 sa = (char *)get_pcb_user_save_pcb(pcb);
  832                 xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) +
  833                     offsetof(struct xstate_hdr, xstate_bv));
  834                 max_ext_n = flsl(xsave_mask);
  835                 for (i = 0; i < max_ext_n; i++) {
  836                         bit = 1ULL << i;
  837                         if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0)
  838                                 continue;
  839                         bcopy((char *)fpu_initialstate +
  840                             xsave_area_desc[i].offset,
  841                             sa + xsave_area_desc[i].offset,
  842                             xsave_area_desc[i].size);
  843                         *xstate_bv |= bit;
  844                 }
  845         }
  846         critical_exit();
  847         return (owned);
  848 }
  849 
  850 void
  851 fpuuserinited(struct thread *td)
  852 {
  853         struct pcb *pcb;
  854 
  855         CRITICAL_ASSERT(td);
  856         pcb = td->td_pcb;
  857         if (PCB_USER_FPU(pcb))
  858                 set_pcb_flags(pcb,
  859                     PCB_FPUINITDONE | PCB_USERFPUINITDONE);
  860         else
  861                 set_pcb_flags(pcb, PCB_FPUINITDONE);
  862 }
  863 
  864 int
  865 fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size)
  866 {
  867         struct xstate_hdr *hdr, *ehdr;
  868         size_t len, max_len;
  869         uint64_t bv;
  870 
  871         /* XXXKIB should we clear all extended state in xstate_bv instead ? */
  872         if (xfpustate == NULL)
  873                 return (0);
  874         if (!use_xsave)
  875                 return (EOPNOTSUPP);
  876 
  877         len = xfpustate_size;
  878         if (len < sizeof(struct xstate_hdr))
  879                 return (EINVAL);
  880         max_len = cpu_max_ext_state_size - sizeof(struct savefpu);
  881         if (len > max_len)
  882                 return (EINVAL);
  883 
  884         ehdr = (struct xstate_hdr *)xfpustate;
  885         bv = ehdr->xstate_bv;
  886 
  887         /*
  888          * Avoid #gp.
  889          */
  890         if (bv & ~xsave_mask)
  891                 return (EINVAL);
  892 
  893         hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1);
  894 
  895         hdr->xstate_bv = bv;
  896         bcopy(xfpustate + sizeof(struct xstate_hdr),
  897             (char *)(hdr + 1), len - sizeof(struct xstate_hdr));
  898 
  899         return (0);
  900 }
  901 
  902 /*
  903  * Set the state of the FPU.
  904  */
  905 int
  906 fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate,
  907     size_t xfpustate_size)
  908 {
  909         struct pcb *pcb;
  910         int error;
  911 
  912         addr->sv_env.en_mxcsr &= cpu_mxcsr_mask;
  913         pcb = td->td_pcb;
  914         error = 0;
  915         critical_enter();
  916         if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
  917                 error = fpusetxstate(td, xfpustate, xfpustate_size);
  918                 if (error == 0) {
  919                         bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
  920                         fpurestore(get_pcb_user_save_td(td));
  921                         set_pcb_flags(pcb, PCB_FPUINITDONE |
  922                             PCB_USERFPUINITDONE);
  923                 }
  924         } else {
  925                 error = fpusetxstate(td, xfpustate, xfpustate_size);
  926                 if (error == 0) {
  927                         bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
  928                         fpuuserinited(td);
  929                 }
  930         }
  931         critical_exit();
  932         return (error);
  933 }
  934 
  935 /*
  936  * On AuthenticAMD processors, the fxrstor instruction does not restore
  937  * the x87's stored last instruction pointer, last data pointer, and last
  938  * opcode values, except in the rare case in which the exception summary
  939  * (ES) bit in the x87 status word is set to 1.
  940  *
  941  * In order to avoid leaking this information across processes, we clean
  942  * these values by performing a dummy load before executing fxrstor().
  943  */
  944 static void
  945 fpu_clean_state(void)
  946 {
  947         static float dummy_variable = 0.0;
  948         u_short status;
  949 
  950         /*
  951          * Clear the ES bit in the x87 status word if it is currently
  952          * set, in order to avoid causing a fault in the upcoming load.
  953          */
  954         fnstsw(&status);
  955         if (status & 0x80)
  956                 fnclex();
  957 
  958         /*
  959          * Load the dummy variable into the x87 stack.  This mangles
  960          * the x87 stack, but we don't care since we're about to call
  961          * fxrstor() anyway.
  962          */
  963         __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable));
  964 }
  965 
  966 /*
  967  * This really sucks.  We want the acpi version only, but it requires
  968  * the isa_if.h file in order to get the definitions.
  969  */
  970 #include "opt_isa.h"
  971 #ifdef DEV_ISA
  972 #include <isa/isavar.h>
  973 /*
  974  * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
  975  */
  976 static struct isa_pnp_id fpupnp_ids[] = {
  977         { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
  978         { 0 }
  979 };
  980 
  981 static int
  982 fpupnp_probe(device_t dev)
  983 {
  984         int result;
  985 
  986         result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids);
  987         if (result <= 0)
  988                 device_quiet(dev);
  989         return (result);
  990 }
  991 
  992 static int
  993 fpupnp_attach(device_t dev)
  994 {
  995 
  996         return (0);
  997 }
  998 
  999 static device_method_t fpupnp_methods[] = {
 1000         /* Device interface */
 1001         DEVMETHOD(device_probe,         fpupnp_probe),
 1002         DEVMETHOD(device_attach,        fpupnp_attach),
 1003         DEVMETHOD(device_detach,        bus_generic_detach),
 1004         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 1005         DEVMETHOD(device_suspend,       bus_generic_suspend),
 1006         DEVMETHOD(device_resume,        bus_generic_resume),
 1007         
 1008         { 0, 0 }
 1009 };
 1010 
 1011 static driver_t fpupnp_driver = {
 1012         "fpupnp",
 1013         fpupnp_methods,
 1014         1,                      /* no softc */
 1015 };
 1016 
 1017 static devclass_t fpupnp_devclass;
 1018 
 1019 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0);
 1020 ISA_PNP_INFO(fpupnp_ids);
 1021 #endif  /* DEV_ISA */
 1022 
 1023 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx",
 1024     "Kernel contexts for FPU state");
 1025 
 1026 #define FPU_KERN_CTX_FPUINITDONE 0x01
 1027 #define FPU_KERN_CTX_DUMMY       0x02   /* avoided save for the kern thread */
 1028 #define FPU_KERN_CTX_INUSE       0x04
 1029 
 1030 struct fpu_kern_ctx {
 1031         struct savefpu *prev;
 1032         uint32_t flags;
 1033         char hwstate1[];
 1034 };
 1035 
 1036 struct fpu_kern_ctx *
 1037 fpu_kern_alloc_ctx(u_int flags)
 1038 {
 1039         struct fpu_kern_ctx *res;
 1040         size_t sz;
 1041 
 1042         sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN +
 1043             cpu_max_ext_state_size;
 1044         res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ?
 1045             M_NOWAIT : M_WAITOK) | M_ZERO);
 1046         return (res);
 1047 }
 1048 
 1049 void
 1050 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx)
 1051 {
 1052 
 1053         KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx"));
 1054         /* XXXKIB clear the memory ? */
 1055         free(ctx, M_FPUKERN_CTX);
 1056 }
 1057 
 1058 static struct savefpu *
 1059 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx)
 1060 {
 1061         vm_offset_t p;
 1062 
 1063         p = (vm_offset_t)&ctx->hwstate1;
 1064         p = roundup2(p, XSAVE_AREA_ALIGN);
 1065         return ((struct savefpu *)p);
 1066 }
 1067 
 1068 void
 1069 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags)
 1070 {
 1071         struct pcb *pcb;
 1072 
 1073         pcb = td->td_pcb;
 1074         KASSERT((flags & FPU_KERN_NOCTX) != 0 || ctx != NULL,
 1075             ("ctx is required when !FPU_KERN_NOCTX"));
 1076         KASSERT(ctx == NULL || (ctx->flags & FPU_KERN_CTX_INUSE) == 0,
 1077             ("using inuse ctx"));
 1078         KASSERT((pcb->pcb_flags & PCB_FPUNOSAVE) == 0,
 1079             ("recursive fpu_kern_enter while in PCB_FPUNOSAVE state"));
 1080 
 1081         if ((flags & FPU_KERN_NOCTX) != 0) {
 1082                 critical_enter();
 1083                 stop_emulating();
 1084                 if (curthread == PCPU_GET(fpcurthread)) {
 1085                         fpusave(curpcb->pcb_save);
 1086                         PCPU_SET(fpcurthread, NULL);
 1087                 } else {
 1088                         KASSERT(PCPU_GET(fpcurthread) == NULL,
 1089                             ("invalid fpcurthread"));
 1090                 }
 1091 
 1092                 /*
 1093                  * This breaks XSAVEOPT tracker, but
 1094                  * PCB_FPUNOSAVE state is supposed to never need to
 1095                  * save FPU context at all.
 1096                  */
 1097                 fpurestore(fpu_initialstate);
 1098                 set_pcb_flags(pcb, PCB_KERNFPU | PCB_FPUNOSAVE |
 1099                     PCB_FPUINITDONE);
 1100                 return;
 1101         }
 1102         if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) {
 1103                 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE;
 1104                 return;
 1105         }
 1106         critical_enter();
 1107         KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save ==
 1108             get_pcb_user_save_pcb(pcb), ("mangled pcb_save"));
 1109         ctx->flags = FPU_KERN_CTX_INUSE;
 1110         if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0)
 1111                 ctx->flags |= FPU_KERN_CTX_FPUINITDONE;
 1112         fpuexit(td);
 1113         ctx->prev = pcb->pcb_save;
 1114         pcb->pcb_save = fpu_kern_ctx_savefpu(ctx);
 1115         set_pcb_flags(pcb, PCB_KERNFPU);
 1116         clear_pcb_flags(pcb, PCB_FPUINITDONE);
 1117         critical_exit();
 1118 }
 1119 
 1120 int
 1121 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx)
 1122 {
 1123         struct pcb *pcb;
 1124 
 1125         pcb = td->td_pcb;
 1126 
 1127         if ((pcb->pcb_flags & PCB_FPUNOSAVE) != 0) {
 1128                 KASSERT(ctx == NULL, ("non-null ctx after FPU_KERN_NOCTX"));
 1129                 KASSERT(PCPU_GET(fpcurthread) == NULL,
 1130                     ("non-NULL fpcurthread for PCB_FPUNOSAVE"));
 1131                 CRITICAL_ASSERT(td);
 1132 
 1133                 clear_pcb_flags(pcb,  PCB_FPUNOSAVE | PCB_FPUINITDONE);
 1134                 start_emulating();
 1135         } else {
 1136                 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0,
 1137                     ("leaving not inuse ctx"));
 1138                 ctx->flags &= ~FPU_KERN_CTX_INUSE;
 1139 
 1140                 if (is_fpu_kern_thread(0) &&
 1141                     (ctx->flags & FPU_KERN_CTX_DUMMY) != 0)
 1142                         return (0);
 1143                 KASSERT((ctx->flags & FPU_KERN_CTX_DUMMY) == 0,
 1144                     ("dummy ctx"));
 1145                 critical_enter();
 1146                 if (curthread == PCPU_GET(fpcurthread))
 1147                         fpudrop();
 1148                 pcb->pcb_save = ctx->prev;
 1149         }
 1150 
 1151         if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) {
 1152                 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) {
 1153                         set_pcb_flags(pcb, PCB_FPUINITDONE);
 1154                         clear_pcb_flags(pcb, PCB_KERNFPU);
 1155                 } else
 1156                         clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU);
 1157         } else {
 1158                 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0)
 1159                         set_pcb_flags(pcb, PCB_FPUINITDONE);
 1160                 else
 1161                         clear_pcb_flags(pcb, PCB_FPUINITDONE);
 1162                 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave"));
 1163         }
 1164         critical_exit();
 1165         return (0);
 1166 }
 1167 
 1168 int
 1169 fpu_kern_thread(u_int flags)
 1170 {
 1171 
 1172         KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0,
 1173             ("Only kthread may use fpu_kern_thread"));
 1174         KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb),
 1175             ("mangled pcb_save"));
 1176         KASSERT(PCB_USER_FPU(curpcb), ("recursive call"));
 1177 
 1178         set_pcb_flags(curpcb, PCB_KERNFPU);
 1179         return (0);
 1180 }
 1181 
 1182 int
 1183 is_fpu_kern_thread(u_int flags)
 1184 {
 1185 
 1186         if ((curthread->td_pflags & TDP_KTHREAD) == 0)
 1187                 return (0);
 1188         return ((curpcb->pcb_flags & PCB_KERNFPU) != 0);
 1189 }
 1190 
 1191 /*
 1192  * FPU save area alloc/free/init utility routines
 1193  */
 1194 struct savefpu *
 1195 fpu_save_area_alloc(void)
 1196 {
 1197 
 1198         return (uma_zalloc(fpu_save_area_zone, 0));
 1199 }
 1200 
 1201 void
 1202 fpu_save_area_free(struct savefpu *fsa)
 1203 {
 1204 
 1205         uma_zfree(fpu_save_area_zone, fsa);
 1206 }
 1207 
 1208 void
 1209 fpu_save_area_reset(struct savefpu *fsa)
 1210 {
 1211 
 1212         bcopy(fpu_initialstate, fsa, cpu_max_ext_state_size);
 1213 }

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