The Design and Implementation of the FreeBSD Operating System, Second Edition
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sys/amd64/amd64/fpu.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-3-Clause
    3  *
    4  * Copyright (c) 1990 William Jolitz.
    5  * Copyright (c) 1991 The Regents of the University of California.
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. Neither the name of the University nor the names of its contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   30  * SUCH DAMAGE.
   31  *
   32  *      from: @(#)npx.c 7.2 (Berkeley) 5/12/91
   33  */
   34 
   35 #include <sys/cdefs.h>
   36 __FBSDID("$FreeBSD: stable/12/sys/amd64/amd64/fpu.c 366910 2020-10-21 15:06:44Z kib $");
   37 
   38 #include <sys/param.h>
   39 #include <sys/systm.h>
   40 #include <sys/bus.h>
   41 #include <sys/kernel.h>
   42 #include <sys/lock.h>
   43 #include <sys/malloc.h>
   44 #include <sys/module.h>
   45 #include <sys/mutex.h>
   46 #include <sys/mutex.h>
   47 #include <sys/proc.h>
   48 #include <sys/sysctl.h>
   49 #include <sys/sysent.h>
   50 #include <machine/bus.h>
   51 #include <sys/rman.h>
   52 #include <sys/signalvar.h>
   53 #include <vm/uma.h>
   54 
   55 #include <machine/cputypes.h>
   56 #include <machine/frame.h>
   57 #include <machine/intr_machdep.h>
   58 #include <machine/md_var.h>
   59 #include <machine/pcb.h>
   60 #include <machine/psl.h>
   61 #include <machine/resource.h>
   62 #include <machine/specialreg.h>
   63 #include <machine/segments.h>
   64 #include <machine/ucontext.h>
   65 #include <x86/ifunc.h>
   66 
   67 /*
   68  * Floating point support.
   69  */
   70 
   71 #if defined(__GNUCLIKE_ASM) && !defined(lint)
   72 
   73 #define fldcw(cw)               __asm __volatile("fldcw %0" : : "m" (cw))
   74 #define fnclex()                __asm __volatile("fnclex")
   75 #define fninit()                __asm __volatile("fninit")
   76 #define fnstcw(addr)            __asm __volatile("fnstcw %0" : "=m" (*(addr)))
   77 #define fnstsw(addr)            __asm __volatile("fnstsw %0" : "=am" (*(addr)))
   78 #define fxrstor(addr)           __asm __volatile("fxrstor %0" : : "m" (*(addr)))
   79 #define fxsave(addr)            __asm __volatile("fxsave %0" : "=m" (*(addr)))
   80 #define ldmxcsr(csr)            __asm __volatile("ldmxcsr %0" : : "m" (csr))
   81 #define stmxcsr(addr)           __asm __volatile("stmxcsr %0" : : "m" (*(addr)))
   82 
   83 static __inline void
   84 xrstor32(char *addr, uint64_t mask)
   85 {
   86         uint32_t low, hi;
   87 
   88         low = mask;
   89         hi = mask >> 32;
   90         __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi));
   91 }
   92 
   93 static __inline void
   94 xrstor64(char *addr, uint64_t mask)
   95 {
   96         uint32_t low, hi;
   97 
   98         low = mask;
   99         hi = mask >> 32;
  100         __asm __volatile("xrstor64 %0" : : "m" (*addr), "a" (low), "d" (hi));
  101 }
  102 
  103 static __inline void
  104 xsave32(char *addr, uint64_t mask)
  105 {
  106         uint32_t low, hi;
  107 
  108         low = mask;
  109         hi = mask >> 32;
  110         __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) :
  111             "memory");
  112 }
  113 
  114 static __inline void
  115 xsave64(char *addr, uint64_t mask)
  116 {
  117         uint32_t low, hi;
  118 
  119         low = mask;
  120         hi = mask >> 32;
  121         __asm __volatile("xsave64 %0" : "=m" (*addr) : "a" (low), "d" (hi) :
  122             "memory");
  123 }
  124 
  125 static __inline void
  126 xsaveopt32(char *addr, uint64_t mask)
  127 {
  128         uint32_t low, hi;
  129 
  130         low = mask;
  131         hi = mask >> 32;
  132         __asm __volatile("xsaveopt %0" : "=m" (*addr) : "a" (low), "d" (hi) :
  133             "memory");
  134 }
  135 
  136 static __inline void
  137 xsaveopt64(char *addr, uint64_t mask)
  138 {
  139         uint32_t low, hi;
  140 
  141         low = mask;
  142         hi = mask >> 32;
  143         __asm __volatile("xsaveopt64 %0" : "=m" (*addr) : "a" (low), "d" (hi) :
  144             "memory");
  145 }
  146 
  147 #else   /* !(__GNUCLIKE_ASM && !lint) */
  148 
  149 void    fldcw(u_short cw);
  150 void    fnclex(void);
  151 void    fninit(void);
  152 void    fnstcw(caddr_t addr);
  153 void    fnstsw(caddr_t addr);
  154 void    fxsave(caddr_t addr);
  155 void    fxrstor(caddr_t addr);
  156 void    ldmxcsr(u_int csr);
  157 void    stmxcsr(u_int *csr);
  158 void    xrstor32(char *addr, uint64_t mask);
  159 void    xrstor64(char *addr, uint64_t mask);
  160 void    xsave32(char *addr, uint64_t mask);
  161 void    xsave64(char *addr, uint64_t mask);
  162 void    xsaveopt32(char *addr, uint64_t mask);
  163 void    xsaveopt64(char *addr, uint64_t mask);
  164 
  165 #endif  /* __GNUCLIKE_ASM && !lint */
  166 
  167 #define start_emulating()       load_cr0(rcr0() | CR0_TS)
  168 #define stop_emulating()        clts()
  169 
  170 CTASSERT(sizeof(struct savefpu) == 512);
  171 CTASSERT(sizeof(struct xstate_hdr) == 64);
  172 CTASSERT(sizeof(struct savefpu_ymm) == 832);
  173 
  174 /*
  175  * This requirement is to make it easier for asm code to calculate
  176  * offset of the fpu save area from the pcb address. FPU save area
  177  * must be 64-byte aligned.
  178  */
  179 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0);
  180 
  181 /*
  182  * Ensure the copy of XCR0 saved in a core is contained in the padding
  183  * area.
  184  */
  185 CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savefpu, sv_pad) &&
  186     X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savefpu));
  187 
  188 static  void    fpu_clean_state(void);
  189 
  190 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD,
  191     SYSCTL_NULL_INT_PTR, 1, "Floating point instructions executed in hardware");
  192 
  193 int lazy_fpu_switch = 0;
  194 SYSCTL_INT(_hw, OID_AUTO, lazy_fpu_switch, CTLFLAG_RD,
  195     &lazy_fpu_switch, 0,
  196     "Lazily load FPU context after context switch");
  197 
  198 int use_xsave;                  /* non-static for cpu_switch.S */
  199 uint64_t xsave_mask;            /* the same */
  200 static  uma_zone_t fpu_save_area_zone;
  201 static  struct savefpu *fpu_initialstate;
  202 
  203 struct xsave_area_elm_descr {
  204         u_int   offset;
  205         u_int   size;
  206 } *xsave_area_desc;
  207 
  208 static void
  209 fpusave_xsaveopt64(void *addr)
  210 {
  211         xsaveopt64((char *)addr, xsave_mask);
  212 }
  213 
  214 static void
  215 fpusave_xsaveopt3264(void *addr)
  216 {
  217         if (SV_CURPROC_FLAG(SV_ILP32))
  218                 xsaveopt32((char *)addr, xsave_mask);
  219         else
  220                 xsaveopt64((char *)addr, xsave_mask);
  221 }
  222 
  223 static void
  224 fpusave_xsave64(void *addr)
  225 {
  226         xsave64((char *)addr, xsave_mask);
  227 }
  228 
  229 static void
  230 fpusave_xsave3264(void *addr)
  231 {
  232         if (SV_CURPROC_FLAG(SV_ILP32))
  233                 xsave32((char *)addr, xsave_mask);
  234         else
  235                 xsave64((char *)addr, xsave_mask);
  236 }
  237 
  238 static void
  239 fpurestore_xrstor64(void *addr)
  240 {
  241         xrstor64((char *)addr, xsave_mask);
  242 }
  243 
  244 static void
  245 fpurestore_xrstor3264(void *addr)
  246 {
  247         if (SV_CURPROC_FLAG(SV_ILP32))
  248                 xrstor32((char *)addr, xsave_mask);
  249         else
  250                 xrstor64((char *)addr, xsave_mask);
  251 }
  252 
  253 static void
  254 fpusave_fxsave(void *addr)
  255 {
  256 
  257         fxsave((char *)addr);
  258 }
  259 
  260 static void
  261 fpurestore_fxrstor(void *addr)
  262 {
  263 
  264         fxrstor((char *)addr);
  265 }
  266 
  267 static void
  268 init_xsave(void)
  269 {
  270 
  271         if (use_xsave)
  272                 return;
  273         if ((cpu_feature2 & CPUID2_XSAVE) == 0)
  274                 return;
  275         use_xsave = 1;
  276         TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave);
  277 }
  278 
  279 DEFINE_IFUNC(, void, fpusave, (void *), static)
  280 {
  281 
  282         init_xsave();
  283         if (!use_xsave)
  284                 return (fpusave_fxsave);
  285         if ((cpu_stdext_feature & CPUID_EXTSTATE_XSAVEOPT) != 0) {
  286                 return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ?
  287                     fpusave_xsaveopt64 : fpusave_xsaveopt3264);
  288         }
  289         return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ?
  290             fpusave_xsave64 : fpusave_xsave3264);
  291 }
  292 
  293 DEFINE_IFUNC(, void, fpurestore, (void *), static)
  294 {
  295 
  296         init_xsave();
  297         if (!use_xsave)
  298                 return (fpurestore_fxrstor);
  299         return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ?
  300             fpurestore_xrstor64 : fpurestore_xrstor3264);
  301 }
  302 
  303 void
  304 fpususpend(void *addr)
  305 {
  306         u_long cr0;
  307 
  308         cr0 = rcr0();
  309         stop_emulating();
  310         fpusave(addr);
  311         load_cr0(cr0);
  312 }
  313 
  314 void
  315 fpuresume(void *addr)
  316 {
  317         u_long cr0;
  318 
  319         cr0 = rcr0();
  320         stop_emulating();
  321         fninit();
  322         if (use_xsave)
  323                 load_xcr(XCR0, xsave_mask);
  324         fpurestore(addr);
  325         load_cr0(cr0);
  326 }
  327 
  328 /*
  329  * Enable XSAVE if supported and allowed by user.
  330  * Calculate the xsave_mask.
  331  */
  332 static void
  333 fpuinit_bsp1(void)
  334 {
  335         u_int cp[4];
  336         uint64_t xsave_mask_user;
  337         bool old_wp;
  338 
  339         if (!use_xsave)
  340                 return;
  341         cpuid_count(0xd, 0x0, cp);
  342         xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
  343         if ((cp[0] & xsave_mask) != xsave_mask)
  344                 panic("CPU0 does not support X87 or SSE: %x", cp[0]);
  345         xsave_mask = ((uint64_t)cp[3] << 32) | cp[0];
  346         xsave_mask_user = xsave_mask;
  347         TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user);
  348         xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
  349         xsave_mask &= xsave_mask_user;
  350         if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512)
  351                 xsave_mask &= ~XFEATURE_AVX512;
  352         if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX)
  353                 xsave_mask &= ~XFEATURE_MPX;
  354 
  355         cpuid_count(0xd, 0x1, cp);
  356         if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) {
  357                 /*
  358                  * Patch the XSAVE instruction in the cpu_switch code
  359                  * to XSAVEOPT.  We assume that XSAVE encoding used
  360                  * REX byte, and set the bit 4 of the r/m byte.
  361                  *
  362                  * It seems that some BIOSes give control to the OS
  363                  * with CR0.WP already set, making the kernel text
  364                  * read-only before cpu_startup().
  365                  */
  366                 old_wp = disable_wp();
  367                 ctx_switch_xsave32[3] |= 0x10;
  368                 ctx_switch_xsave[3] |= 0x10;
  369                 restore_wp(old_wp);
  370         }
  371 }
  372 
  373 /*
  374  * Calculate the fpu save area size.
  375  */
  376 static void
  377 fpuinit_bsp2(void)
  378 {
  379         u_int cp[4];
  380 
  381         if (use_xsave) {
  382                 cpuid_count(0xd, 0x0, cp);
  383                 cpu_max_ext_state_size = cp[1];
  384 
  385                 /*
  386                  * Reload the cpu_feature2, since we enabled OSXSAVE.
  387                  */
  388                 do_cpuid(1, cp);
  389                 cpu_feature2 = cp[2];
  390         } else
  391                 cpu_max_ext_state_size = sizeof(struct savefpu);
  392 }
  393 
  394 /*
  395  * Initialize the floating point unit.
  396  */
  397 void
  398 fpuinit(void)
  399 {
  400         register_t saveintr;
  401         u_int mxcsr;
  402         u_short control;
  403 
  404         if (IS_BSP())
  405                 fpuinit_bsp1();
  406 
  407         if (use_xsave) {
  408                 load_cr4(rcr4() | CR4_XSAVE);
  409                 load_xcr(XCR0, xsave_mask);
  410         }
  411 
  412         /*
  413          * XCR0 shall be set up before CPU can report the save area size.
  414          */
  415         if (IS_BSP())
  416                 fpuinit_bsp2();
  417 
  418         /*
  419          * It is too early for critical_enter() to work on AP.
  420          */
  421         saveintr = intr_disable();
  422         stop_emulating();
  423         fninit();
  424         control = __INITIAL_FPUCW__;
  425         fldcw(control);
  426         mxcsr = __INITIAL_MXCSR__;
  427         ldmxcsr(mxcsr);
  428         start_emulating();
  429         intr_restore(saveintr);
  430 }
  431 
  432 /*
  433  * On the boot CPU we generate a clean state that is used to
  434  * initialize the floating point unit when it is first used by a
  435  * process.
  436  */
  437 static void
  438 fpuinitstate(void *arg __unused)
  439 {
  440         uint64_t *xstate_bv;
  441         register_t saveintr;
  442         int cp[4], i, max_ext_n;
  443 
  444         fpu_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF,
  445             M_WAITOK | M_ZERO);
  446         saveintr = intr_disable();
  447         stop_emulating();
  448 
  449         fpusave_fxsave(fpu_initialstate);
  450         if (fpu_initialstate->sv_env.en_mxcsr_mask)
  451                 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask;
  452         else
  453                 cpu_mxcsr_mask = 0xFFBF;
  454 
  455         /*
  456          * The fninit instruction does not modify XMM registers or x87
  457          * registers (MM/ST).  The fpusave call dumped the garbage
  458          * contained in the registers after reset to the initial state
  459          * saved.  Clear XMM and x87 registers file image to make the
  460          * startup program state and signal handler XMM/x87 register
  461          * content predictable.
  462          */
  463         bzero(fpu_initialstate->sv_fp, sizeof(fpu_initialstate->sv_fp));
  464         bzero(fpu_initialstate->sv_xmm, sizeof(fpu_initialstate->sv_xmm));
  465 
  466         /*
  467          * Create a table describing the layout of the CPU Extended
  468          * Save Area.
  469          */
  470         if (use_xsave) {
  471                 xstate_bv = (uint64_t *)((char *)(fpu_initialstate + 1) +
  472                     offsetof(struct xstate_hdr, xstate_bv));
  473                 *xstate_bv = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
  474 
  475                 max_ext_n = flsl(xsave_mask);
  476                 xsave_area_desc = malloc(max_ext_n * sizeof(struct
  477                     xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO);
  478                 /* x87 state */
  479                 xsave_area_desc[0].offset = 0;
  480                 xsave_area_desc[0].size = 160;
  481                 /* XMM */
  482                 xsave_area_desc[1].offset = 160;
  483                 xsave_area_desc[1].size = 288 - 160;
  484 
  485                 for (i = 2; i < max_ext_n; i++) {
  486                         cpuid_count(0xd, i, cp);
  487                         xsave_area_desc[i].offset = cp[1];
  488                         xsave_area_desc[i].size = cp[0];
  489                 }
  490         }
  491 
  492         fpu_save_area_zone = uma_zcreate("FPU_save_area",
  493             cpu_max_ext_state_size, NULL, NULL, NULL, NULL,
  494             XSAVE_AREA_ALIGN - 1, 0);
  495 
  496         start_emulating();
  497         intr_restore(saveintr);
  498 }
  499 /* EFIRT needs this to be initialized before we can enter our EFI environment */
  500 SYSINIT(fpuinitstate, SI_SUB_DRIVERS, SI_ORDER_FIRST, fpuinitstate, NULL);
  501 
  502 /*
  503  * Free coprocessor (if we have it).
  504  */
  505 void
  506 fpuexit(struct thread *td)
  507 {
  508 
  509         critical_enter();
  510         if (curthread == PCPU_GET(fpcurthread)) {
  511                 stop_emulating();
  512                 fpusave(curpcb->pcb_save);
  513                 start_emulating();
  514                 PCPU_SET(fpcurthread, NULL);
  515         }
  516         critical_exit();
  517 }
  518 
  519 int
  520 fpuformat(void)
  521 {
  522 
  523         return (_MC_FPFMT_XMM);
  524 }
  525 
  526 /* 
  527  * The following mechanism is used to ensure that the FPE_... value
  528  * that is passed as a trapcode to the signal handler of the user
  529  * process does not have more than one bit set.
  530  * 
  531  * Multiple bits may be set if the user process modifies the control
  532  * word while a status word bit is already set.  While this is a sign
  533  * of bad coding, we have no choise than to narrow them down to one
  534  * bit, since we must not send a trapcode that is not exactly one of
  535  * the FPE_ macros.
  536  *
  537  * The mechanism has a static table with 127 entries.  Each combination
  538  * of the 7 FPU status word exception bits directly translates to a
  539  * position in this table, where a single FPE_... value is stored.
  540  * This FPE_... value stored there is considered the "most important"
  541  * of the exception bits and will be sent as the signal code.  The
  542  * precedence of the bits is based upon Intel Document "Numerical
  543  * Applications", Chapter "Special Computational Situations".
  544  *
  545  * The macro to choose one of these values does these steps: 1) Throw
  546  * away status word bits that cannot be masked.  2) Throw away the bits
  547  * currently masked in the control word, assuming the user isn't
  548  * interested in them anymore.  3) Reinsert status word bit 7 (stack
  549  * fault) if it is set, which cannot be masked but must be presered.
  550  * 4) Use the remaining bits to point into the trapcode table.
  551  *
  552  * The 6 maskable bits in order of their preference, as stated in the
  553  * above referenced Intel manual:
  554  * 1  Invalid operation (FP_X_INV)
  555  * 1a   Stack underflow
  556  * 1b   Stack overflow
  557  * 1c   Operand of unsupported format
  558  * 1d   SNaN operand.
  559  * 2  QNaN operand (not an exception, irrelavant here)
  560  * 3  Any other invalid-operation not mentioned above or zero divide
  561  *      (FP_X_INV, FP_X_DZ)
  562  * 4  Denormal operand (FP_X_DNML)
  563  * 5  Numeric over/underflow (FP_X_OFL, FP_X_UFL)
  564  * 6  Inexact result (FP_X_IMP) 
  565  */
  566 static char fpetable[128] = {
  567         0,
  568         FPE_FLTINV,     /*  1 - INV */
  569         FPE_FLTUND,     /*  2 - DNML */
  570         FPE_FLTINV,     /*  3 - INV | DNML */
  571         FPE_FLTDIV,     /*  4 - DZ */
  572         FPE_FLTINV,     /*  5 - INV | DZ */
  573         FPE_FLTDIV,     /*  6 - DNML | DZ */
  574         FPE_FLTINV,     /*  7 - INV | DNML | DZ */
  575         FPE_FLTOVF,     /*  8 - OFL */
  576         FPE_FLTINV,     /*  9 - INV | OFL */
  577         FPE_FLTUND,     /*  A - DNML | OFL */
  578         FPE_FLTINV,     /*  B - INV | DNML | OFL */
  579         FPE_FLTDIV,     /*  C - DZ | OFL */
  580         FPE_FLTINV,     /*  D - INV | DZ | OFL */
  581         FPE_FLTDIV,     /*  E - DNML | DZ | OFL */
  582         FPE_FLTINV,     /*  F - INV | DNML | DZ | OFL */
  583         FPE_FLTUND,     /* 10 - UFL */
  584         FPE_FLTINV,     /* 11 - INV | UFL */
  585         FPE_FLTUND,     /* 12 - DNML | UFL */
  586         FPE_FLTINV,     /* 13 - INV | DNML | UFL */
  587         FPE_FLTDIV,     /* 14 - DZ | UFL */
  588         FPE_FLTINV,     /* 15 - INV | DZ | UFL */
  589         FPE_FLTDIV,     /* 16 - DNML | DZ | UFL */
  590         FPE_FLTINV,     /* 17 - INV | DNML | DZ | UFL */
  591         FPE_FLTOVF,     /* 18 - OFL | UFL */
  592         FPE_FLTINV,     /* 19 - INV | OFL | UFL */
  593         FPE_FLTUND,     /* 1A - DNML | OFL | UFL */
  594         FPE_FLTINV,     /* 1B - INV | DNML | OFL | UFL */
  595         FPE_FLTDIV,     /* 1C - DZ | OFL | UFL */
  596         FPE_FLTINV,     /* 1D - INV | DZ | OFL | UFL */
  597         FPE_FLTDIV,     /* 1E - DNML | DZ | OFL | UFL */
  598         FPE_FLTINV,     /* 1F - INV | DNML | DZ | OFL | UFL */
  599         FPE_FLTRES,     /* 20 - IMP */
  600         FPE_FLTINV,     /* 21 - INV | IMP */
  601         FPE_FLTUND,     /* 22 - DNML | IMP */
  602         FPE_FLTINV,     /* 23 - INV | DNML | IMP */
  603         FPE_FLTDIV,     /* 24 - DZ | IMP */
  604         FPE_FLTINV,     /* 25 - INV | DZ | IMP */
  605         FPE_FLTDIV,     /* 26 - DNML | DZ | IMP */
  606         FPE_FLTINV,     /* 27 - INV | DNML | DZ | IMP */
  607         FPE_FLTOVF,     /* 28 - OFL | IMP */
  608         FPE_FLTINV,     /* 29 - INV | OFL | IMP */
  609         FPE_FLTUND,     /* 2A - DNML | OFL | IMP */
  610         FPE_FLTINV,     /* 2B - INV | DNML | OFL | IMP */
  611         FPE_FLTDIV,     /* 2C - DZ | OFL | IMP */
  612         FPE_FLTINV,     /* 2D - INV | DZ | OFL | IMP */
  613         FPE_FLTDIV,     /* 2E - DNML | DZ | OFL | IMP */
  614         FPE_FLTINV,     /* 2F - INV | DNML | DZ | OFL | IMP */
  615         FPE_FLTUND,     /* 30 - UFL | IMP */
  616         FPE_FLTINV,     /* 31 - INV | UFL | IMP */
  617         FPE_FLTUND,     /* 32 - DNML | UFL | IMP */
  618         FPE_FLTINV,     /* 33 - INV | DNML | UFL | IMP */
  619         FPE_FLTDIV,     /* 34 - DZ | UFL | IMP */
  620         FPE_FLTINV,     /* 35 - INV | DZ | UFL | IMP */
  621         FPE_FLTDIV,     /* 36 - DNML | DZ | UFL | IMP */
  622         FPE_FLTINV,     /* 37 - INV | DNML | DZ | UFL | IMP */
  623         FPE_FLTOVF,     /* 38 - OFL | UFL | IMP */
  624         FPE_FLTINV,     /* 39 - INV | OFL | UFL | IMP */
  625         FPE_FLTUND,     /* 3A - DNML | OFL | UFL | IMP */
  626         FPE_FLTINV,     /* 3B - INV | DNML | OFL | UFL | IMP */
  627         FPE_FLTDIV,     /* 3C - DZ | OFL | UFL | IMP */
  628         FPE_FLTINV,     /* 3D - INV | DZ | OFL | UFL | IMP */
  629         FPE_FLTDIV,     /* 3E - DNML | DZ | OFL | UFL | IMP */
  630         FPE_FLTINV,     /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
  631         FPE_FLTSUB,     /* 40 - STK */
  632         FPE_FLTSUB,     /* 41 - INV | STK */
  633         FPE_FLTUND,     /* 42 - DNML | STK */
  634         FPE_FLTSUB,     /* 43 - INV | DNML | STK */
  635         FPE_FLTDIV,     /* 44 - DZ | STK */
  636         FPE_FLTSUB,     /* 45 - INV | DZ | STK */
  637         FPE_FLTDIV,     /* 46 - DNML | DZ | STK */
  638         FPE_FLTSUB,     /* 47 - INV | DNML | DZ | STK */
  639         FPE_FLTOVF,     /* 48 - OFL | STK */
  640         FPE_FLTSUB,     /* 49 - INV | OFL | STK */
  641         FPE_FLTUND,     /* 4A - DNML | OFL | STK */
  642         FPE_FLTSUB,     /* 4B - INV | DNML | OFL | STK */
  643         FPE_FLTDIV,     /* 4C - DZ | OFL | STK */
  644         FPE_FLTSUB,     /* 4D - INV | DZ | OFL | STK */
  645         FPE_FLTDIV,     /* 4E - DNML | DZ | OFL | STK */
  646         FPE_FLTSUB,     /* 4F - INV | DNML | DZ | OFL | STK */
  647         FPE_FLTUND,     /* 50 - UFL | STK */
  648         FPE_FLTSUB,     /* 51 - INV | UFL | STK */
  649         FPE_FLTUND,     /* 52 - DNML | UFL | STK */
  650         FPE_FLTSUB,     /* 53 - INV | DNML | UFL | STK */
  651         FPE_FLTDIV,     /* 54 - DZ | UFL | STK */
  652         FPE_FLTSUB,     /* 55 - INV | DZ | UFL | STK */
  653         FPE_FLTDIV,     /* 56 - DNML | DZ | UFL | STK */
  654         FPE_FLTSUB,     /* 57 - INV | DNML | DZ | UFL | STK */
  655         FPE_FLTOVF,     /* 58 - OFL | UFL | STK */
  656         FPE_FLTSUB,     /* 59 - INV | OFL | UFL | STK */
  657         FPE_FLTUND,     /* 5A - DNML | OFL | UFL | STK */
  658         FPE_FLTSUB,     /* 5B - INV | DNML | OFL | UFL | STK */
  659         FPE_FLTDIV,     /* 5C - DZ | OFL | UFL | STK */
  660         FPE_FLTSUB,     /* 5D - INV | DZ | OFL | UFL | STK */
  661         FPE_FLTDIV,     /* 5E - DNML | DZ | OFL | UFL | STK */
  662         FPE_FLTSUB,     /* 5F - INV | DNML | DZ | OFL | UFL | STK */
  663         FPE_FLTRES,     /* 60 - IMP | STK */
  664         FPE_FLTSUB,     /* 61 - INV | IMP | STK */
  665         FPE_FLTUND,     /* 62 - DNML | IMP | STK */
  666         FPE_FLTSUB,     /* 63 - INV | DNML | IMP | STK */
  667         FPE_FLTDIV,     /* 64 - DZ | IMP | STK */
  668         FPE_FLTSUB,     /* 65 - INV | DZ | IMP | STK */
  669         FPE_FLTDIV,     /* 66 - DNML | DZ | IMP | STK */
  670         FPE_FLTSUB,     /* 67 - INV | DNML | DZ | IMP | STK */
  671         FPE_FLTOVF,     /* 68 - OFL | IMP | STK */
  672         FPE_FLTSUB,     /* 69 - INV | OFL | IMP | STK */
  673         FPE_FLTUND,     /* 6A - DNML | OFL | IMP | STK */
  674         FPE_FLTSUB,     /* 6B - INV | DNML | OFL | IMP | STK */
  675         FPE_FLTDIV,     /* 6C - DZ | OFL | IMP | STK */
  676         FPE_FLTSUB,     /* 6D - INV | DZ | OFL | IMP | STK */
  677         FPE_FLTDIV,     /* 6E - DNML | DZ | OFL | IMP | STK */
  678         FPE_FLTSUB,     /* 6F - INV | DNML | DZ | OFL | IMP | STK */
  679         FPE_FLTUND,     /* 70 - UFL | IMP | STK */
  680         FPE_FLTSUB,     /* 71 - INV | UFL | IMP | STK */
  681         FPE_FLTUND,     /* 72 - DNML | UFL | IMP | STK */
  682         FPE_FLTSUB,     /* 73 - INV | DNML | UFL | IMP | STK */
  683         FPE_FLTDIV,     /* 74 - DZ | UFL | IMP | STK */
  684         FPE_FLTSUB,     /* 75 - INV | DZ | UFL | IMP | STK */
  685         FPE_FLTDIV,     /* 76 - DNML | DZ | UFL | IMP | STK */
  686         FPE_FLTSUB,     /* 77 - INV | DNML | DZ | UFL | IMP | STK */
  687         FPE_FLTOVF,     /* 78 - OFL | UFL | IMP | STK */
  688         FPE_FLTSUB,     /* 79 - INV | OFL | UFL | IMP | STK */
  689         FPE_FLTUND,     /* 7A - DNML | OFL | UFL | IMP | STK */
  690         FPE_FLTSUB,     /* 7B - INV | DNML | OFL | UFL | IMP | STK */
  691         FPE_FLTDIV,     /* 7C - DZ | OFL | UFL | IMP | STK */
  692         FPE_FLTSUB,     /* 7D - INV | DZ | OFL | UFL | IMP | STK */
  693         FPE_FLTDIV,     /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
  694         FPE_FLTSUB,     /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
  695 };
  696 
  697 /*
  698  * Read the FP status and control words, then generate si_code value
  699  * for SIGFPE.  The error code chosen will be one of the
  700  * FPE_... macros.  It will be sent as the second argument to old
  701  * BSD-style signal handlers and as "siginfo_t->si_code" (second
  702  * argument) to SA_SIGINFO signal handlers.
  703  *
  704  * Some time ago, we cleared the x87 exceptions with FNCLEX there.
  705  * Clearing exceptions was necessary mainly to avoid IRQ13 bugs.  The
  706  * usermode code which understands the FPU hardware enough to enable
  707  * the exceptions, can also handle clearing the exception state in the
  708  * handler.  The only consequence of not clearing the exception is the
  709  * rethrow of the SIGFPE on return from the signal handler and
  710  * reexecution of the corresponding instruction.
  711  *
  712  * For XMM traps, the exceptions were never cleared.
  713  */
  714 int
  715 fputrap_x87(void)
  716 {
  717         struct savefpu *pcb_save;
  718         u_short control, status;
  719 
  720         critical_enter();
  721 
  722         /*
  723          * Interrupt handling (for another interrupt) may have pushed the
  724          * state to memory.  Fetch the relevant parts of the state from
  725          * wherever they are.
  726          */
  727         if (PCPU_GET(fpcurthread) != curthread) {
  728                 pcb_save = curpcb->pcb_save;
  729                 control = pcb_save->sv_env.en_cw;
  730                 status = pcb_save->sv_env.en_sw;
  731         } else {
  732                 fnstcw(&control);
  733                 fnstsw(&status);
  734         }
  735 
  736         critical_exit();
  737         return (fpetable[status & ((~control & 0x3f) | 0x40)]);
  738 }
  739 
  740 int
  741 fputrap_sse(void)
  742 {
  743         u_int mxcsr;
  744 
  745         critical_enter();
  746         if (PCPU_GET(fpcurthread) != curthread)
  747                 mxcsr = curpcb->pcb_save->sv_env.en_mxcsr;
  748         else
  749                 stmxcsr(&mxcsr);
  750         critical_exit();
  751         return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]);
  752 }
  753 
  754 static void
  755 restore_fpu_curthread(struct thread *td)
  756 {
  757         struct pcb *pcb;
  758 
  759         /*
  760          * Record new context early in case frstor causes a trap.
  761          */
  762         PCPU_SET(fpcurthread, td);
  763 
  764         stop_emulating();
  765         fpu_clean_state();
  766         pcb = td->td_pcb;
  767 
  768         if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) {
  769                 /*
  770                  * This is the first time this thread has used the FPU or
  771                  * the PCB doesn't contain a clean FPU state.  Explicitly
  772                  * load an initial state.
  773                  *
  774                  * We prefer to restore the state from the actual save
  775                  * area in PCB instead of directly loading from
  776                  * fpu_initialstate, to ignite the XSAVEOPT
  777                  * tracking engine.
  778                  */
  779                 bcopy(fpu_initialstate, pcb->pcb_save,
  780                     cpu_max_ext_state_size);
  781                 fpurestore(pcb->pcb_save);
  782                 if (pcb->pcb_initial_fpucw != __INITIAL_FPUCW__)
  783                         fldcw(pcb->pcb_initial_fpucw);
  784                 if (PCB_USER_FPU(pcb))
  785                         set_pcb_flags(pcb, PCB_FPUINITDONE |
  786                             PCB_USERFPUINITDONE);
  787                 else
  788                         set_pcb_flags(pcb, PCB_FPUINITDONE);
  789         } else
  790                 fpurestore(pcb->pcb_save);
  791 }
  792 
  793 /*
  794  * Device Not Available (DNA, #NM) exception handler.
  795  *
  796  * It would be better to switch FP context here (if curthread !=
  797  * fpcurthread) and not necessarily for every context switch, but it
  798  * is too hard to access foreign pcb's.
  799  */
  800 void
  801 fpudna(void)
  802 {
  803         struct thread *td;
  804 
  805         td = curthread;
  806         /*
  807          * This handler is entered with interrupts enabled, so context
  808          * switches may occur before critical_enter() is executed.  If
  809          * a context switch occurs, then when we regain control, our
  810          * state will have been completely restored.  The CPU may
  811          * change underneath us, but the only part of our context that
  812          * lives in the CPU is CR0.TS and that will be "restored" by
  813          * setting it on the new CPU.
  814          */
  815         critical_enter();
  816 
  817         KASSERT((curpcb->pcb_flags & PCB_FPUNOSAVE) == 0,
  818             ("fpudna while in fpu_kern_enter(FPU_KERN_NOCTX)"));
  819         if (__predict_false(PCPU_GET(fpcurthread) == td)) {
  820                 /*
  821                  * Some virtual machines seems to set %cr0.TS at
  822                  * arbitrary moments.  Silently clear the TS bit
  823                  * regardless of the eager/lazy FPU context switch
  824                  * mode.
  825                  */
  826                 stop_emulating();
  827         } else {
  828                 if (__predict_false(PCPU_GET(fpcurthread) != NULL)) {
  829                         panic(
  830                     "fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n",
  831                             PCPU_GET(fpcurthread),
  832                             PCPU_GET(fpcurthread)->td_tid, td, td->td_tid);
  833                 }
  834                 restore_fpu_curthread(td);
  835         }
  836         critical_exit();
  837 }
  838 
  839 void fpu_activate_sw(struct thread *td); /* Called from the context switch */
  840 void
  841 fpu_activate_sw(struct thread *td)
  842 {
  843 
  844         if ((td->td_pflags & TDP_KTHREAD) != 0 || !PCB_USER_FPU(td->td_pcb)) {
  845                 PCPU_SET(fpcurthread, NULL);
  846                 start_emulating();
  847         } else if (PCPU_GET(fpcurthread) != td) {
  848                 restore_fpu_curthread(td);
  849         }
  850 }
  851 
  852 void
  853 fpudrop(void)
  854 {
  855         struct thread *td;
  856 
  857         td = PCPU_GET(fpcurthread);
  858         KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread"));
  859         CRITICAL_ASSERT(td);
  860         PCPU_SET(fpcurthread, NULL);
  861         clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE);
  862         start_emulating();
  863 }
  864 
  865 /*
  866  * Get the user state of the FPU into pcb->pcb_user_save without
  867  * dropping ownership (if possible).  It returns the FPU ownership
  868  * status.
  869  */
  870 int
  871 fpugetregs(struct thread *td)
  872 {
  873         struct pcb *pcb;
  874         uint64_t *xstate_bv, bit;
  875         char *sa;
  876         int max_ext_n, i, owned;
  877 
  878         pcb = td->td_pcb;
  879         critical_enter();
  880         if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) {
  881                 bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb),
  882                     cpu_max_ext_state_size);
  883                 get_pcb_user_save_pcb(pcb)->sv_env.en_cw =
  884                     pcb->pcb_initial_fpucw;
  885                 fpuuserinited(td);
  886                 critical_exit();
  887                 return (_MC_FPOWNED_PCB);
  888         }
  889         if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
  890                 fpusave(get_pcb_user_save_pcb(pcb));
  891                 owned = _MC_FPOWNED_FPU;
  892         } else {
  893                 owned = _MC_FPOWNED_PCB;
  894         }
  895         if (use_xsave) {
  896                 /*
  897                  * Handle partially saved state.
  898                  */
  899                 sa = (char *)get_pcb_user_save_pcb(pcb);
  900                 xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) +
  901                     offsetof(struct xstate_hdr, xstate_bv));
  902                 max_ext_n = flsl(xsave_mask);
  903                 for (i = 0; i < max_ext_n; i++) {
  904                         bit = 1ULL << i;
  905                         if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0)
  906                                 continue;
  907                         bcopy((char *)fpu_initialstate +
  908                             xsave_area_desc[i].offset,
  909                             sa + xsave_area_desc[i].offset,
  910                             xsave_area_desc[i].size);
  911                         *xstate_bv |= bit;
  912                 }
  913         }
  914         critical_exit();
  915         return (owned);
  916 }
  917 
  918 void
  919 fpuuserinited(struct thread *td)
  920 {
  921         struct pcb *pcb;
  922 
  923         CRITICAL_ASSERT(td);
  924         pcb = td->td_pcb;
  925         if (PCB_USER_FPU(pcb))
  926                 set_pcb_flags(pcb,
  927                     PCB_FPUINITDONE | PCB_USERFPUINITDONE);
  928         else
  929                 set_pcb_flags(pcb, PCB_FPUINITDONE);
  930 }
  931 
  932 int
  933 fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size)
  934 {
  935         struct xstate_hdr *hdr, *ehdr;
  936         size_t len, max_len;
  937         uint64_t bv;
  938 
  939         /* XXXKIB should we clear all extended state in xstate_bv instead ? */
  940         if (xfpustate == NULL)
  941                 return (0);
  942         if (!use_xsave)
  943                 return (EOPNOTSUPP);
  944 
  945         len = xfpustate_size;
  946         if (len < sizeof(struct xstate_hdr))
  947                 return (EINVAL);
  948         max_len = cpu_max_ext_state_size - sizeof(struct savefpu);
  949         if (len > max_len)
  950                 return (EINVAL);
  951 
  952         ehdr = (struct xstate_hdr *)xfpustate;
  953         bv = ehdr->xstate_bv;
  954 
  955         /*
  956          * Avoid #gp.
  957          */
  958         if (bv & ~xsave_mask)
  959                 return (EINVAL);
  960 
  961         hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1);
  962 
  963         hdr->xstate_bv = bv;
  964         bcopy(xfpustate + sizeof(struct xstate_hdr),
  965             (char *)(hdr + 1), len - sizeof(struct xstate_hdr));
  966 
  967         return (0);
  968 }
  969 
  970 /*
  971  * Set the state of the FPU.
  972  */
  973 int
  974 fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate,
  975     size_t xfpustate_size)
  976 {
  977         struct pcb *pcb;
  978         int error;
  979 
  980         addr->sv_env.en_mxcsr &= cpu_mxcsr_mask;
  981         pcb = td->td_pcb;
  982         error = 0;
  983         critical_enter();
  984         if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
  985                 error = fpusetxstate(td, xfpustate, xfpustate_size);
  986                 if (error == 0) {
  987                         bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
  988                         fpurestore(get_pcb_user_save_td(td));
  989                         set_pcb_flags(pcb, PCB_FPUINITDONE |
  990                             PCB_USERFPUINITDONE);
  991                 }
  992         } else {
  993                 error = fpusetxstate(td, xfpustate, xfpustate_size);
  994                 if (error == 0) {
  995                         bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
  996                         fpuuserinited(td);
  997                 }
  998         }
  999         critical_exit();
 1000         return (error);
 1001 }
 1002 
 1003 /*
 1004  * On AuthenticAMD processors, the fxrstor instruction does not restore
 1005  * the x87's stored last instruction pointer, last data pointer, and last
 1006  * opcode values, except in the rare case in which the exception summary
 1007  * (ES) bit in the x87 status word is set to 1.
 1008  *
 1009  * In order to avoid leaking this information across processes, we clean
 1010  * these values by performing a dummy load before executing fxrstor().
 1011  */
 1012 static void
 1013 fpu_clean_state(void)
 1014 {
 1015         static float dummy_variable = 0.0;
 1016         u_short status;
 1017 
 1018         /*
 1019          * Clear the ES bit in the x87 status word if it is currently
 1020          * set, in order to avoid causing a fault in the upcoming load.
 1021          */
 1022         fnstsw(&status);
 1023         if (status & 0x80)
 1024                 fnclex();
 1025 
 1026         /*
 1027          * Load the dummy variable into the x87 stack.  This mangles
 1028          * the x87 stack, but we don't care since we're about to call
 1029          * fxrstor() anyway.
 1030          */
 1031         __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable));
 1032 }
 1033 
 1034 /*
 1035  * This really sucks.  We want the acpi version only, but it requires
 1036  * the isa_if.h file in order to get the definitions.
 1037  */
 1038 #include "opt_isa.h"
 1039 #ifdef DEV_ISA
 1040 #include <isa/isavar.h>
 1041 /*
 1042  * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
 1043  */
 1044 static struct isa_pnp_id fpupnp_ids[] = {
 1045         { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
 1046         { 0 }
 1047 };
 1048 
 1049 static int
 1050 fpupnp_probe(device_t dev)
 1051 {
 1052         int result;
 1053 
 1054         result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids);
 1055         if (result <= 0)
 1056                 device_quiet(dev);
 1057         return (result);
 1058 }
 1059 
 1060 static int
 1061 fpupnp_attach(device_t dev)
 1062 {
 1063 
 1064         return (0);
 1065 }
 1066 
 1067 static device_method_t fpupnp_methods[] = {
 1068         /* Device interface */
 1069         DEVMETHOD(device_probe,         fpupnp_probe),
 1070         DEVMETHOD(device_attach,        fpupnp_attach),
 1071         DEVMETHOD(device_detach,        bus_generic_detach),
 1072         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 1073         DEVMETHOD(device_suspend,       bus_generic_suspend),
 1074         DEVMETHOD(device_resume,        bus_generic_resume),
 1075         
 1076         { 0, 0 }
 1077 };
 1078 
 1079 static driver_t fpupnp_driver = {
 1080         "fpupnp",
 1081         fpupnp_methods,
 1082         1,                      /* no softc */
 1083 };
 1084 
 1085 static devclass_t fpupnp_devclass;
 1086 
 1087 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0);
 1088 ISA_PNP_INFO(fpupnp_ids);
 1089 #endif  /* DEV_ISA */
 1090 
 1091 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx",
 1092     "Kernel contexts for FPU state");
 1093 
 1094 #define FPU_KERN_CTX_FPUINITDONE 0x01
 1095 #define FPU_KERN_CTX_DUMMY       0x02   /* avoided save for the kern thread */
 1096 #define FPU_KERN_CTX_INUSE       0x04
 1097 
 1098 struct fpu_kern_ctx {
 1099         struct savefpu *prev;
 1100         uint32_t flags;
 1101         char hwstate1[];
 1102 };
 1103 
 1104 struct fpu_kern_ctx *
 1105 fpu_kern_alloc_ctx(u_int flags)
 1106 {
 1107         struct fpu_kern_ctx *res;
 1108         size_t sz;
 1109 
 1110         sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN +
 1111             cpu_max_ext_state_size;
 1112         res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ?
 1113             M_NOWAIT : M_WAITOK) | M_ZERO);
 1114         return (res);
 1115 }
 1116 
 1117 void
 1118 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx)
 1119 {
 1120 
 1121         KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx"));
 1122         /* XXXKIB clear the memory ? */
 1123         free(ctx, M_FPUKERN_CTX);
 1124 }
 1125 
 1126 static struct savefpu *
 1127 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx)
 1128 {
 1129         vm_offset_t p;
 1130 
 1131         p = (vm_offset_t)&ctx->hwstate1;
 1132         p = roundup2(p, XSAVE_AREA_ALIGN);
 1133         return ((struct savefpu *)p);
 1134 }
 1135 
 1136 void
 1137 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags)
 1138 {
 1139         struct pcb *pcb;
 1140 
 1141         pcb = td->td_pcb;
 1142         KASSERT((flags & FPU_KERN_NOCTX) != 0 || ctx != NULL,
 1143             ("ctx is required when !FPU_KERN_NOCTX"));
 1144         KASSERT(ctx == NULL || (ctx->flags & FPU_KERN_CTX_INUSE) == 0,
 1145             ("using inuse ctx"));
 1146         KASSERT((pcb->pcb_flags & PCB_FPUNOSAVE) == 0,
 1147             ("recursive fpu_kern_enter while in PCB_FPUNOSAVE state"));
 1148 
 1149         if ((flags & FPU_KERN_NOCTX) != 0) {
 1150                 critical_enter();
 1151                 stop_emulating();
 1152                 if (curthread == PCPU_GET(fpcurthread)) {
 1153                         fpusave(curpcb->pcb_save);
 1154                         PCPU_SET(fpcurthread, NULL);
 1155                 } else {
 1156                         KASSERT(PCPU_GET(fpcurthread) == NULL,
 1157                             ("invalid fpcurthread"));
 1158                 }
 1159 
 1160                 /*
 1161                  * This breaks XSAVEOPT tracker, but
 1162                  * PCB_FPUNOSAVE state is supposed to never need to
 1163                  * save FPU context at all.
 1164                  */
 1165                 fpurestore(fpu_initialstate);
 1166                 set_pcb_flags(pcb, PCB_KERNFPU | PCB_FPUNOSAVE |
 1167                     PCB_FPUINITDONE);
 1168                 return;
 1169         }
 1170         if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) {
 1171                 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE;
 1172                 return;
 1173         }
 1174         critical_enter();
 1175         KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save ==
 1176             get_pcb_user_save_pcb(pcb), ("mangled pcb_save"));
 1177         ctx->flags = FPU_KERN_CTX_INUSE;
 1178         if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0)
 1179                 ctx->flags |= FPU_KERN_CTX_FPUINITDONE;
 1180         fpuexit(td);
 1181         ctx->prev = pcb->pcb_save;
 1182         pcb->pcb_save = fpu_kern_ctx_savefpu(ctx);
 1183         set_pcb_flags(pcb, PCB_KERNFPU);
 1184         clear_pcb_flags(pcb, PCB_FPUINITDONE);
 1185         critical_exit();
 1186 }
 1187 
 1188 int
 1189 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx)
 1190 {
 1191         struct pcb *pcb;
 1192 
 1193         pcb = td->td_pcb;
 1194 
 1195         if ((pcb->pcb_flags & PCB_FPUNOSAVE) != 0) {
 1196                 KASSERT(ctx == NULL, ("non-null ctx after FPU_KERN_NOCTX"));
 1197                 KASSERT(PCPU_GET(fpcurthread) == NULL,
 1198                     ("non-NULL fpcurthread for PCB_FPUNOSAVE"));
 1199                 CRITICAL_ASSERT(td);
 1200 
 1201                 clear_pcb_flags(pcb,  PCB_FPUNOSAVE | PCB_FPUINITDONE);
 1202                 start_emulating();
 1203         } else {
 1204                 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0,
 1205                     ("leaving not inuse ctx"));
 1206                 ctx->flags &= ~FPU_KERN_CTX_INUSE;
 1207 
 1208                 if (is_fpu_kern_thread(0) &&
 1209                     (ctx->flags & FPU_KERN_CTX_DUMMY) != 0)
 1210                         return (0);
 1211                 KASSERT((ctx->flags & FPU_KERN_CTX_DUMMY) == 0,
 1212                     ("dummy ctx"));
 1213                 critical_enter();
 1214                 if (curthread == PCPU_GET(fpcurthread))
 1215                         fpudrop();
 1216                 pcb->pcb_save = ctx->prev;
 1217         }
 1218 
 1219         if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) {
 1220                 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) {
 1221                         set_pcb_flags(pcb, PCB_FPUINITDONE);
 1222                         if ((pcb->pcb_flags & PCB_KERNFPU_THR) == 0)
 1223                                 clear_pcb_flags(pcb, PCB_KERNFPU);
 1224                 } else if ((pcb->pcb_flags & PCB_KERNFPU_THR) == 0)
 1225                         clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU);
 1226         } else {
 1227                 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0)
 1228                         set_pcb_flags(pcb, PCB_FPUINITDONE);
 1229                 else
 1230                         clear_pcb_flags(pcb, PCB_FPUINITDONE);
 1231                 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave"));
 1232         }
 1233         critical_exit();
 1234         return (0);
 1235 }
 1236 
 1237 int
 1238 fpu_kern_thread(u_int flags)
 1239 {
 1240 
 1241         KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0,
 1242             ("Only kthread may use fpu_kern_thread"));
 1243         KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb),
 1244             ("mangled pcb_save"));
 1245         KASSERT(PCB_USER_FPU(curpcb), ("recursive call"));
 1246 
 1247         set_pcb_flags(curpcb, PCB_KERNFPU | PCB_KERNFPU_THR);
 1248         return (0);
 1249 }
 1250 
 1251 int
 1252 is_fpu_kern_thread(u_int flags)
 1253 {
 1254 
 1255         if ((curthread->td_pflags & TDP_KTHREAD) == 0)
 1256                 return (0);
 1257         return ((curpcb->pcb_flags & PCB_KERNFPU_THR) != 0);
 1258 }
 1259 
 1260 /*
 1261  * FPU save area alloc/free/init utility routines
 1262  */
 1263 struct savefpu *
 1264 fpu_save_area_alloc(void)
 1265 {
 1266 
 1267         return (uma_zalloc(fpu_save_area_zone, 0));
 1268 }
 1269 
 1270 void
 1271 fpu_save_area_free(struct savefpu *fsa)
 1272 {
 1273 
 1274         uma_zfree(fpu_save_area_zone, fsa);
 1275 }
 1276 
 1277 void
 1278 fpu_save_area_reset(struct savefpu *fsa)
 1279 {
 1280 
 1281         bcopy(fpu_initialstate, fsa, cpu_max_ext_state_size);
 1282 }

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