FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/fpu.c
1 /*-
2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by the University of
17 * California, Berkeley and its contributors.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
35 */
36
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD: releng/5.2/sys/amd64/amd64/fpu.c 123180 2003-12-06 23:19:47Z peter $");
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/bus.h>
43 #include <sys/kernel.h>
44 #include <sys/lock.h>
45 #include <sys/malloc.h>
46 #include <sys/module.h>
47 #include <sys/mutex.h>
48 #include <sys/mutex.h>
49 #include <sys/proc.h>
50 #include <sys/sysctl.h>
51 #include <machine/bus.h>
52 #include <sys/rman.h>
53 #include <sys/signalvar.h>
54 #include <sys/user.h>
55
56 #include <machine/cputypes.h>
57 #include <machine/frame.h>
58 #include <machine/intr_machdep.h>
59 #include <machine/md_var.h>
60 #include <machine/pcb.h>
61 #include <machine/psl.h>
62 #include <machine/resource.h>
63 #include <machine/specialreg.h>
64 #include <machine/segments.h>
65 #include <machine/ucontext.h>
66
67 /*
68 * Floating point support.
69 */
70
71 #if defined(__GNUC__) && !defined(lint)
72
73 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr)))
74 #define fnclex() __asm("fnclex")
75 #define fninit() __asm("fninit")
76 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
77 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr)))
78 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr)))
79 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
80 #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
81 : : "n" (CR0_TS) : "ax")
82 #define stop_emulating() __asm("clts")
83
84 #else /* not __GNUC__ */
85
86 void fldcw(caddr_t addr);
87 void fnclex(void);
88 void fninit(void);
89 void fnstcw(caddr_t addr);
90 void fnstsw(caddr_t addr);
91 void fxsave(caddr_t addr);
92 void fxrstor(caddr_t addr);
93 void start_emulating(void);
94 void stop_emulating(void);
95
96 #endif /* __GNUC__ */
97
98 #define GET_FPU_CW(thread) ((thread)->td_pcb->pcb_save.sv_env.en_cw)
99 #define GET_FPU_SW(thread) ((thread)->td_pcb->pcb_save.sv_env.en_sw)
100
101 typedef u_char bool_t;
102
103 int hw_float = 1;
104 SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
105 CTLFLAG_RD, &hw_float, 0,
106 "Floatingpoint instructions executed in hardware");
107
108 static struct savefpu fpu_cleanstate;
109 static bool_t fpu_cleanstate_ready;
110
111 /*
112 * Initialize floating point unit.
113 */
114 void
115 fpuinit()
116 {
117 register_t savecrit;
118 u_short control;
119
120 /*
121 * fpusave() initializes the fpu and sets fpcurthread = NULL
122 */
123 savecrit = intr_disable();
124 fpusave(&fpu_cleanstate); /* XXX borrow for now */
125 stop_emulating();
126 /* XXX fpusave() doesn't actually initialize the fpu in the SSE case. */
127 fninit();
128 control = __INITIAL_FPUCW__;
129 fldcw(&control);
130 start_emulating();
131 intr_restore(savecrit);
132
133 savecrit = intr_disable();
134 stop_emulating();
135 fxsave(&fpu_cleanstate);
136 start_emulating();
137 fpu_cleanstate_ready = 1;
138 intr_restore(savecrit);
139 }
140
141 /*
142 * Free coprocessor (if we have it).
143 */
144 void
145 fpuexit(struct thread *td)
146 {
147 register_t savecrit;
148
149 savecrit = intr_disable();
150 if (curthread == PCPU_GET(fpcurthread))
151 fpusave(&PCPU_GET(curpcb)->pcb_save);
152 intr_restore(savecrit);
153 }
154
155 int
156 fpuformat()
157 {
158
159 return (_MC_FPFMT_XMM);
160 }
161
162 /*
163 * The following mechanism is used to ensure that the FPE_... value
164 * that is passed as a trapcode to the signal handler of the user
165 * process does not have more than one bit set.
166 *
167 * Multiple bits may be set if the user process modifies the control
168 * word while a status word bit is already set. While this is a sign
169 * of bad coding, we have no choise than to narrow them down to one
170 * bit, since we must not send a trapcode that is not exactly one of
171 * the FPE_ macros.
172 *
173 * The mechanism has a static table with 127 entries. Each combination
174 * of the 7 FPU status word exception bits directly translates to a
175 * position in this table, where a single FPE_... value is stored.
176 * This FPE_... value stored there is considered the "most important"
177 * of the exception bits and will be sent as the signal code. The
178 * precedence of the bits is based upon Intel Document "Numerical
179 * Applications", Chapter "Special Computational Situations".
180 *
181 * The macro to choose one of these values does these steps: 1) Throw
182 * away status word bits that cannot be masked. 2) Throw away the bits
183 * currently masked in the control word, assuming the user isn't
184 * interested in them anymore. 3) Reinsert status word bit 7 (stack
185 * fault) if it is set, which cannot be masked but must be presered.
186 * 4) Use the remaining bits to point into the trapcode table.
187 *
188 * The 6 maskable bits in order of their preference, as stated in the
189 * above referenced Intel manual:
190 * 1 Invalid operation (FP_X_INV)
191 * 1a Stack underflow
192 * 1b Stack overflow
193 * 1c Operand of unsupported format
194 * 1d SNaN operand.
195 * 2 QNaN operand (not an exception, irrelavant here)
196 * 3 Any other invalid-operation not mentioned above or zero divide
197 * (FP_X_INV, FP_X_DZ)
198 * 4 Denormal operand (FP_X_DNML)
199 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
200 * 6 Inexact result (FP_X_IMP)
201 */
202 static char fpetable[128] = {
203 0,
204 FPE_FLTINV, /* 1 - INV */
205 FPE_FLTUND, /* 2 - DNML */
206 FPE_FLTINV, /* 3 - INV | DNML */
207 FPE_FLTDIV, /* 4 - DZ */
208 FPE_FLTINV, /* 5 - INV | DZ */
209 FPE_FLTDIV, /* 6 - DNML | DZ */
210 FPE_FLTINV, /* 7 - INV | DNML | DZ */
211 FPE_FLTOVF, /* 8 - OFL */
212 FPE_FLTINV, /* 9 - INV | OFL */
213 FPE_FLTUND, /* A - DNML | OFL */
214 FPE_FLTINV, /* B - INV | DNML | OFL */
215 FPE_FLTDIV, /* C - DZ | OFL */
216 FPE_FLTINV, /* D - INV | DZ | OFL */
217 FPE_FLTDIV, /* E - DNML | DZ | OFL */
218 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
219 FPE_FLTUND, /* 10 - UFL */
220 FPE_FLTINV, /* 11 - INV | UFL */
221 FPE_FLTUND, /* 12 - DNML | UFL */
222 FPE_FLTINV, /* 13 - INV | DNML | UFL */
223 FPE_FLTDIV, /* 14 - DZ | UFL */
224 FPE_FLTINV, /* 15 - INV | DZ | UFL */
225 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
226 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
227 FPE_FLTOVF, /* 18 - OFL | UFL */
228 FPE_FLTINV, /* 19 - INV | OFL | UFL */
229 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
230 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
231 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
232 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
233 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
234 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
235 FPE_FLTRES, /* 20 - IMP */
236 FPE_FLTINV, /* 21 - INV | IMP */
237 FPE_FLTUND, /* 22 - DNML | IMP */
238 FPE_FLTINV, /* 23 - INV | DNML | IMP */
239 FPE_FLTDIV, /* 24 - DZ | IMP */
240 FPE_FLTINV, /* 25 - INV | DZ | IMP */
241 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
242 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
243 FPE_FLTOVF, /* 28 - OFL | IMP */
244 FPE_FLTINV, /* 29 - INV | OFL | IMP */
245 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
246 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
247 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
248 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
249 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
250 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
251 FPE_FLTUND, /* 30 - UFL | IMP */
252 FPE_FLTINV, /* 31 - INV | UFL | IMP */
253 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
254 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
255 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
256 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
257 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
258 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
259 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
260 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
261 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
262 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
263 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
264 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
265 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
266 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
267 FPE_FLTSUB, /* 40 - STK */
268 FPE_FLTSUB, /* 41 - INV | STK */
269 FPE_FLTUND, /* 42 - DNML | STK */
270 FPE_FLTSUB, /* 43 - INV | DNML | STK */
271 FPE_FLTDIV, /* 44 - DZ | STK */
272 FPE_FLTSUB, /* 45 - INV | DZ | STK */
273 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
274 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
275 FPE_FLTOVF, /* 48 - OFL | STK */
276 FPE_FLTSUB, /* 49 - INV | OFL | STK */
277 FPE_FLTUND, /* 4A - DNML | OFL | STK */
278 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
279 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
280 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
281 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
282 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
283 FPE_FLTUND, /* 50 - UFL | STK */
284 FPE_FLTSUB, /* 51 - INV | UFL | STK */
285 FPE_FLTUND, /* 52 - DNML | UFL | STK */
286 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
287 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
288 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
289 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
290 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
291 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
292 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
293 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
294 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
295 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
296 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
297 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
298 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
299 FPE_FLTRES, /* 60 - IMP | STK */
300 FPE_FLTSUB, /* 61 - INV | IMP | STK */
301 FPE_FLTUND, /* 62 - DNML | IMP | STK */
302 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
303 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
304 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
305 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
306 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
307 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
308 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
309 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
310 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
311 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
312 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
313 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
314 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
315 FPE_FLTUND, /* 70 - UFL | IMP | STK */
316 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
317 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
318 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
319 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
320 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
321 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
322 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
323 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
324 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
325 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
326 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
327 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
328 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
329 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
330 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
331 };
332
333 /*
334 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
335 *
336 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now
337 * depend on longjmp() restoring a usable state. Restoring the state
338 * or examining it might fail if we didn't clear exceptions.
339 *
340 * The error code chosen will be one of the FPE_... macros. It will be
341 * sent as the second argument to old BSD-style signal handlers and as
342 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
343 *
344 * XXX the FP state is not preserved across signal handlers. So signal
345 * handlers cannot afford to do FP unless they preserve the state or
346 * longjmp() out. Both preserving the state and longjmp()ing may be
347 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable
348 * solution for signals other than SIGFPE.
349 */
350 int
351 fputrap()
352 {
353 register_t savecrit;
354 u_short control, status;
355
356 savecrit = intr_disable();
357
358 /*
359 * Interrupt handling (for another interrupt) may have pushed the
360 * state to memory. Fetch the relevant parts of the state from
361 * wherever they are.
362 */
363 if (PCPU_GET(fpcurthread) != curthread) {
364 control = GET_FPU_CW(curthread);
365 status = GET_FPU_SW(curthread);
366 } else {
367 fnstcw(&control);
368 fnstsw(&status);
369 }
370
371 if (PCPU_GET(fpcurthread) == curthread)
372 fnclex();
373 intr_restore(savecrit);
374 return (fpetable[status & ((~control & 0x3f) | 0x40)]);
375 }
376
377 /*
378 * Implement device not available (DNA) exception
379 *
380 * It would be better to switch FP context here (if curthread != fpcurthread)
381 * and not necessarily for every context switch, but it is too hard to
382 * access foreign pcb's.
383 */
384
385 static int err_count = 0;
386
387 int
388 fpudna()
389 {
390 struct pcb *pcb;
391 register_t s;
392 u_short control;
393
394 if (PCPU_GET(fpcurthread) == curthread) {
395 printf("fpudna: fpcurthread == curthread %d times\n",
396 ++err_count);
397 stop_emulating();
398 return (1);
399 }
400 if (PCPU_GET(fpcurthread) != NULL) {
401 printf("fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n",
402 PCPU_GET(fpcurthread),
403 PCPU_GET(fpcurthread)->td_proc->p_pid,
404 curthread, curthread->td_proc->p_pid);
405 panic("fpudna");
406 }
407 s = intr_disable();
408 stop_emulating();
409 /*
410 * Record new context early in case frstor causes a trap.
411 */
412 PCPU_SET(fpcurthread, curthread);
413 pcb = PCPU_GET(curpcb);
414
415 if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) {
416 /*
417 * This is the first time this thread has used the FPU or
418 * the PCB doesn't contain a clean FPU state. Explicitly
419 * initialize the FPU and load the default control word.
420 */
421 fninit();
422 control = __INITIAL_FPUCW__;
423 fldcw(&control);
424 pcb->pcb_flags |= PCB_FPUINITDONE;
425 } else {
426 /*
427 * The following frstor may cause a trap when the state
428 * being restored has a pending error. The error will
429 * appear to have been triggered by the current (fpu) user
430 * instruction even when that instruction is a no-wait
431 * instruction that should not trigger an error (e.g.,
432 * instructions are broken the same as frstor, so our
433 * treatment does not amplify the breakage.
434 */
435 fxrstor(&pcb->pcb_save);
436 }
437 intr_restore(s);
438
439 return (1);
440 }
441
442 /*
443 * Wrapper for fnsave instruction.
444 *
445 * fpusave() must be called with interrupts disabled, so that it clears
446 * fpcurthread atomically with saving the state. We require callers to do the
447 * disabling, since most callers need to disable interrupts anyway to call
448 * fpusave() atomically with checking fpcurthread.
449 */
450 void
451 fpusave(struct savefpu *addr)
452 {
453
454 stop_emulating();
455 fxsave(addr);
456 start_emulating();
457 PCPU_SET(fpcurthread, NULL);
458 }
459
460 /*
461 * This should be called with interrupts disabled and only when the owning
462 * FPU thread is non-null.
463 */
464 void
465 fpudrop()
466 {
467 struct thread *td;
468
469 td = PCPU_GET(fpcurthread);
470 PCPU_SET(fpcurthread, NULL);
471 td->td_pcb->pcb_flags &= ~PCB_FPUINITDONE;
472 start_emulating();
473 }
474
475 /*
476 * Get the state of the FPU without dropping ownership (if possible).
477 * It returns the FPU ownership status.
478 */
479 int
480 fpugetregs(struct thread *td, struct savefpu *addr)
481 {
482 register_t s;
483
484 if ((td->td_pcb->pcb_flags & PCB_FPUINITDONE) == 0) {
485 if (fpu_cleanstate_ready)
486 bcopy(&fpu_cleanstate, addr, sizeof(fpu_cleanstate));
487 else
488 bzero(addr, sizeof(*addr));
489 return (_MC_FPOWNED_NONE);
490 }
491 s = intr_disable();
492 if (td == PCPU_GET(fpcurthread)) {
493 fxsave(addr);
494 intr_restore(s);
495 return (_MC_FPOWNED_FPU);
496 } else {
497 intr_restore(s);
498 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr));
499 return (_MC_FPOWNED_PCB);
500 }
501 }
502
503 /*
504 * Set the state of the FPU.
505 */
506 void
507 fpusetregs(struct thread *td, struct savefpu *addr)
508 {
509 register_t s;
510
511 s = intr_disable();
512 if (td == PCPU_GET(fpcurthread)) {
513 fxrstor(addr);
514 intr_restore(s);
515 } else {
516 intr_restore(s);
517 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr));
518 }
519 curthread->td_pcb->pcb_flags |= PCB_FPUINITDONE;
520 }
521
522 /*
523 * This really sucks. We want the acpi version only, but it requires
524 * the isa_if.h file in order to get the definitions.
525 */
526 #include "opt_isa.h"
527 #ifdef DEV_ISA
528 #include <isa/isavar.h>
529 /*
530 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
531 */
532 static struct isa_pnp_id fpupnp_ids[] = {
533 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
534 { 0 }
535 };
536
537 static int
538 fpupnp_probe(device_t dev)
539 {
540 int result;
541
542 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids);
543 if (result <= 0)
544 device_quiet(dev);
545 return (result);
546 }
547
548 static int
549 fpupnp_attach(device_t dev)
550 {
551
552 return (0);
553 }
554
555 static device_method_t fpupnp_methods[] = {
556 /* Device interface */
557 DEVMETHOD(device_probe, fpupnp_probe),
558 DEVMETHOD(device_attach, fpupnp_attach),
559 DEVMETHOD(device_detach, bus_generic_detach),
560 DEVMETHOD(device_shutdown, bus_generic_shutdown),
561 DEVMETHOD(device_suspend, bus_generic_suspend),
562 DEVMETHOD(device_resume, bus_generic_resume),
563
564 { 0, 0 }
565 };
566
567 static driver_t fpupnp_driver = {
568 "fpupnp",
569 fpupnp_methods,
570 1, /* no softc */
571 };
572
573 static devclass_t fpupnp_devclass;
574
575 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0);
576 #endif /* DEV_ISA */
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