The Design and Implementation of the FreeBSD Operating System, Second Edition
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sys/amd64/amd64/fpu.c

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    1 /*-
    2  * Copyright (c) 1990 William Jolitz.
    3  * Copyright (c) 1991 The Regents of the University of California.
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  * 4. Neither the name of the University nor the names of its contributors
   15  *    may be used to endorse or promote products derived from this software
   16  *    without specific prior written permission.
   17  *
   18  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   28  * SUCH DAMAGE.
   29  *
   30  *      from: @(#)npx.c 7.2 (Berkeley) 5/12/91
   31  */
   32 
   33 #include <sys/cdefs.h>
   34 __FBSDID("$FreeBSD: releng/5.3/sys/amd64/amd64/fpu.c 157863 2006-04-19 07:03:14Z cperciva $");
   35 
   36 #include <sys/param.h>
   37 #include <sys/systm.h>
   38 #include <sys/bus.h>
   39 #include <sys/kernel.h>
   40 #include <sys/lock.h>
   41 #include <sys/malloc.h>
   42 #include <sys/module.h>
   43 #include <sys/mutex.h>
   44 #include <sys/mutex.h>
   45 #include <sys/proc.h>
   46 #include <sys/sysctl.h>
   47 #include <machine/bus.h>
   48 #include <sys/rman.h>
   49 #include <sys/signalvar.h>
   50 #include <sys/user.h>
   51 
   52 #include <machine/cputypes.h>
   53 #include <machine/frame.h>
   54 #include <machine/intr_machdep.h>
   55 #include <machine/md_var.h>
   56 #include <machine/pcb.h>
   57 #include <machine/psl.h>
   58 #include <machine/resource.h>
   59 #include <machine/specialreg.h>
   60 #include <machine/segments.h>
   61 #include <machine/ucontext.h>
   62 
   63 /*
   64  * Floating point support.
   65  */
   66 
   67 #if defined(__GNUC__) && !defined(lint)
   68 
   69 #define fldcw(addr)             __asm("fldcw %0" : : "m" (*(addr)))
   70 #define fnclex()                __asm("fnclex")
   71 #define fninit()                __asm("fninit")
   72 #define fnstcw(addr)            __asm __volatile("fnstcw %0" : "=m" (*(addr)))
   73 #define fnstsw(addr)            __asm __volatile("fnstsw %0" : "=m" (*(addr)))
   74 #define fxrstor(addr)           __asm("fxrstor %0" : : "m" (*(addr)))
   75 #define fxsave(addr)            __asm __volatile("fxsave %0" : "=m" (*(addr)))
   76 #define ldmxcsr(r)              __asm __volatile("ldmxcsr %0" : : "m" (r))
   77 #define start_emulating()       __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
   78                                       : : "n" (CR0_TS) : "ax")
   79 #define stop_emulating()        __asm("clts")
   80 
   81 #else   /* not __GNUC__ */
   82 
   83 void    fldcw(caddr_t addr);
   84 void    fnclex(void);
   85 void    fninit(void);
   86 void    fnstcw(caddr_t addr);
   87 void    fnstsw(caddr_t addr);
   88 void    fxsave(caddr_t addr);
   89 void    fxrstor(caddr_t addr);
   90 void    start_emulating(void);
   91 void    stop_emulating(void);
   92 
   93 #endif  /* __GNUC__ */
   94 
   95 #define GET_FPU_CW(thread) ((thread)->td_pcb->pcb_save.sv_env.en_cw)
   96 #define GET_FPU_SW(thread) ((thread)->td_pcb->pcb_save.sv_env.en_sw)
   97 
   98 typedef u_char bool_t;
   99 
  100 static  void    fpu_clean_state(void);
  101 
  102 int     hw_float = 1;
  103 SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
  104         CTLFLAG_RD, &hw_float, 0, 
  105         "Floatingpoint instructions executed in hardware");
  106 
  107 static  struct savefpu          fpu_cleanstate;
  108 static  bool_t                  fpu_cleanstate_ready;
  109 
  110 /*
  111  * Initialize floating point unit.
  112  */
  113 void
  114 fpuinit(void)
  115 {
  116         register_t savecrit;
  117         u_int mxcsr;
  118         u_short control;
  119 
  120         savecrit = intr_disable();
  121         PCPU_SET(fpcurthread, 0);
  122         stop_emulating();
  123         fninit();
  124         control = __INITIAL_FPUCW__;
  125         fldcw(&control);
  126         mxcsr = __INITIAL_MXCSR__;
  127         ldmxcsr(mxcsr);
  128         fxsave(&fpu_cleanstate);
  129         start_emulating();
  130         bzero(fpu_cleanstate.sv_fp, sizeof(fpu_cleanstate.sv_fp));
  131         bzero(fpu_cleanstate.sv_xmm, sizeof(fpu_cleanstate.sv_xmm));
  132         fpu_cleanstate_ready = 1;
  133         intr_restore(savecrit);
  134 }
  135 
  136 /*
  137  * Free coprocessor (if we have it).
  138  */
  139 void
  140 fpuexit(struct thread *td)
  141 {
  142         register_t savecrit;
  143 
  144         savecrit = intr_disable();
  145         if (curthread == PCPU_GET(fpcurthread)) {
  146                 stop_emulating();
  147                 fxsave(&PCPU_GET(curpcb)->pcb_save);
  148                 start_emulating();
  149                 PCPU_SET(fpcurthread, 0);
  150         }
  151         intr_restore(savecrit);
  152 }
  153 
  154 int
  155 fpuformat()
  156 {
  157 
  158         return (_MC_FPFMT_XMM);
  159 }
  160 
  161 /* 
  162  * The following mechanism is used to ensure that the FPE_... value
  163  * that is passed as a trapcode to the signal handler of the user
  164  * process does not have more than one bit set.
  165  * 
  166  * Multiple bits may be set if the user process modifies the control
  167  * word while a status word bit is already set.  While this is a sign
  168  * of bad coding, we have no choise than to narrow them down to one
  169  * bit, since we must not send a trapcode that is not exactly one of
  170  * the FPE_ macros.
  171  *
  172  * The mechanism has a static table with 127 entries.  Each combination
  173  * of the 7 FPU status word exception bits directly translates to a
  174  * position in this table, where a single FPE_... value is stored.
  175  * This FPE_... value stored there is considered the "most important"
  176  * of the exception bits and will be sent as the signal code.  The
  177  * precedence of the bits is based upon Intel Document "Numerical
  178  * Applications", Chapter "Special Computational Situations".
  179  *
  180  * The macro to choose one of these values does these steps: 1) Throw
  181  * away status word bits that cannot be masked.  2) Throw away the bits
  182  * currently masked in the control word, assuming the user isn't
  183  * interested in them anymore.  3) Reinsert status word bit 7 (stack
  184  * fault) if it is set, which cannot be masked but must be presered.
  185  * 4) Use the remaining bits to point into the trapcode table.
  186  *
  187  * The 6 maskable bits in order of their preference, as stated in the
  188  * above referenced Intel manual:
  189  * 1  Invalid operation (FP_X_INV)
  190  * 1a   Stack underflow
  191  * 1b   Stack overflow
  192  * 1c   Operand of unsupported format
  193  * 1d   SNaN operand.
  194  * 2  QNaN operand (not an exception, irrelavant here)
  195  * 3  Any other invalid-operation not mentioned above or zero divide
  196  *      (FP_X_INV, FP_X_DZ)
  197  * 4  Denormal operand (FP_X_DNML)
  198  * 5  Numeric over/underflow (FP_X_OFL, FP_X_UFL)
  199  * 6  Inexact result (FP_X_IMP) 
  200  */
  201 static char fpetable[128] = {
  202         0,
  203         FPE_FLTINV,     /*  1 - INV */
  204         FPE_FLTUND,     /*  2 - DNML */
  205         FPE_FLTINV,     /*  3 - INV | DNML */
  206         FPE_FLTDIV,     /*  4 - DZ */
  207         FPE_FLTINV,     /*  5 - INV | DZ */
  208         FPE_FLTDIV,     /*  6 - DNML | DZ */
  209         FPE_FLTINV,     /*  7 - INV | DNML | DZ */
  210         FPE_FLTOVF,     /*  8 - OFL */
  211         FPE_FLTINV,     /*  9 - INV | OFL */
  212         FPE_FLTUND,     /*  A - DNML | OFL */
  213         FPE_FLTINV,     /*  B - INV | DNML | OFL */
  214         FPE_FLTDIV,     /*  C - DZ | OFL */
  215         FPE_FLTINV,     /*  D - INV | DZ | OFL */
  216         FPE_FLTDIV,     /*  E - DNML | DZ | OFL */
  217         FPE_FLTINV,     /*  F - INV | DNML | DZ | OFL */
  218         FPE_FLTUND,     /* 10 - UFL */
  219         FPE_FLTINV,     /* 11 - INV | UFL */
  220         FPE_FLTUND,     /* 12 - DNML | UFL */
  221         FPE_FLTINV,     /* 13 - INV | DNML | UFL */
  222         FPE_FLTDIV,     /* 14 - DZ | UFL */
  223         FPE_FLTINV,     /* 15 - INV | DZ | UFL */
  224         FPE_FLTDIV,     /* 16 - DNML | DZ | UFL */
  225         FPE_FLTINV,     /* 17 - INV | DNML | DZ | UFL */
  226         FPE_FLTOVF,     /* 18 - OFL | UFL */
  227         FPE_FLTINV,     /* 19 - INV | OFL | UFL */
  228         FPE_FLTUND,     /* 1A - DNML | OFL | UFL */
  229         FPE_FLTINV,     /* 1B - INV | DNML | OFL | UFL */
  230         FPE_FLTDIV,     /* 1C - DZ | OFL | UFL */
  231         FPE_FLTINV,     /* 1D - INV | DZ | OFL | UFL */
  232         FPE_FLTDIV,     /* 1E - DNML | DZ | OFL | UFL */
  233         FPE_FLTINV,     /* 1F - INV | DNML | DZ | OFL | UFL */
  234         FPE_FLTRES,     /* 20 - IMP */
  235         FPE_FLTINV,     /* 21 - INV | IMP */
  236         FPE_FLTUND,     /* 22 - DNML | IMP */
  237         FPE_FLTINV,     /* 23 - INV | DNML | IMP */
  238         FPE_FLTDIV,     /* 24 - DZ | IMP */
  239         FPE_FLTINV,     /* 25 - INV | DZ | IMP */
  240         FPE_FLTDIV,     /* 26 - DNML | DZ | IMP */
  241         FPE_FLTINV,     /* 27 - INV | DNML | DZ | IMP */
  242         FPE_FLTOVF,     /* 28 - OFL | IMP */
  243         FPE_FLTINV,     /* 29 - INV | OFL | IMP */
  244         FPE_FLTUND,     /* 2A - DNML | OFL | IMP */
  245         FPE_FLTINV,     /* 2B - INV | DNML | OFL | IMP */
  246         FPE_FLTDIV,     /* 2C - DZ | OFL | IMP */
  247         FPE_FLTINV,     /* 2D - INV | DZ | OFL | IMP */
  248         FPE_FLTDIV,     /* 2E - DNML | DZ | OFL | IMP */
  249         FPE_FLTINV,     /* 2F - INV | DNML | DZ | OFL | IMP */
  250         FPE_FLTUND,     /* 30 - UFL | IMP */
  251         FPE_FLTINV,     /* 31 - INV | UFL | IMP */
  252         FPE_FLTUND,     /* 32 - DNML | UFL | IMP */
  253         FPE_FLTINV,     /* 33 - INV | DNML | UFL | IMP */
  254         FPE_FLTDIV,     /* 34 - DZ | UFL | IMP */
  255         FPE_FLTINV,     /* 35 - INV | DZ | UFL | IMP */
  256         FPE_FLTDIV,     /* 36 - DNML | DZ | UFL | IMP */
  257         FPE_FLTINV,     /* 37 - INV | DNML | DZ | UFL | IMP */
  258         FPE_FLTOVF,     /* 38 - OFL | UFL | IMP */
  259         FPE_FLTINV,     /* 39 - INV | OFL | UFL | IMP */
  260         FPE_FLTUND,     /* 3A - DNML | OFL | UFL | IMP */
  261         FPE_FLTINV,     /* 3B - INV | DNML | OFL | UFL | IMP */
  262         FPE_FLTDIV,     /* 3C - DZ | OFL | UFL | IMP */
  263         FPE_FLTINV,     /* 3D - INV | DZ | OFL | UFL | IMP */
  264         FPE_FLTDIV,     /* 3E - DNML | DZ | OFL | UFL | IMP */
  265         FPE_FLTINV,     /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
  266         FPE_FLTSUB,     /* 40 - STK */
  267         FPE_FLTSUB,     /* 41 - INV | STK */
  268         FPE_FLTUND,     /* 42 - DNML | STK */
  269         FPE_FLTSUB,     /* 43 - INV | DNML | STK */
  270         FPE_FLTDIV,     /* 44 - DZ | STK */
  271         FPE_FLTSUB,     /* 45 - INV | DZ | STK */
  272         FPE_FLTDIV,     /* 46 - DNML | DZ | STK */
  273         FPE_FLTSUB,     /* 47 - INV | DNML | DZ | STK */
  274         FPE_FLTOVF,     /* 48 - OFL | STK */
  275         FPE_FLTSUB,     /* 49 - INV | OFL | STK */
  276         FPE_FLTUND,     /* 4A - DNML | OFL | STK */
  277         FPE_FLTSUB,     /* 4B - INV | DNML | OFL | STK */
  278         FPE_FLTDIV,     /* 4C - DZ | OFL | STK */
  279         FPE_FLTSUB,     /* 4D - INV | DZ | OFL | STK */
  280         FPE_FLTDIV,     /* 4E - DNML | DZ | OFL | STK */
  281         FPE_FLTSUB,     /* 4F - INV | DNML | DZ | OFL | STK */
  282         FPE_FLTUND,     /* 50 - UFL | STK */
  283         FPE_FLTSUB,     /* 51 - INV | UFL | STK */
  284         FPE_FLTUND,     /* 52 - DNML | UFL | STK */
  285         FPE_FLTSUB,     /* 53 - INV | DNML | UFL | STK */
  286         FPE_FLTDIV,     /* 54 - DZ | UFL | STK */
  287         FPE_FLTSUB,     /* 55 - INV | DZ | UFL | STK */
  288         FPE_FLTDIV,     /* 56 - DNML | DZ | UFL | STK */
  289         FPE_FLTSUB,     /* 57 - INV | DNML | DZ | UFL | STK */
  290         FPE_FLTOVF,     /* 58 - OFL | UFL | STK */
  291         FPE_FLTSUB,     /* 59 - INV | OFL | UFL | STK */
  292         FPE_FLTUND,     /* 5A - DNML | OFL | UFL | STK */
  293         FPE_FLTSUB,     /* 5B - INV | DNML | OFL | UFL | STK */
  294         FPE_FLTDIV,     /* 5C - DZ | OFL | UFL | STK */
  295         FPE_FLTSUB,     /* 5D - INV | DZ | OFL | UFL | STK */
  296         FPE_FLTDIV,     /* 5E - DNML | DZ | OFL | UFL | STK */
  297         FPE_FLTSUB,     /* 5F - INV | DNML | DZ | OFL | UFL | STK */
  298         FPE_FLTRES,     /* 60 - IMP | STK */
  299         FPE_FLTSUB,     /* 61 - INV | IMP | STK */
  300         FPE_FLTUND,     /* 62 - DNML | IMP | STK */
  301         FPE_FLTSUB,     /* 63 - INV | DNML | IMP | STK */
  302         FPE_FLTDIV,     /* 64 - DZ | IMP | STK */
  303         FPE_FLTSUB,     /* 65 - INV | DZ | IMP | STK */
  304         FPE_FLTDIV,     /* 66 - DNML | DZ | IMP | STK */
  305         FPE_FLTSUB,     /* 67 - INV | DNML | DZ | IMP | STK */
  306         FPE_FLTOVF,     /* 68 - OFL | IMP | STK */
  307         FPE_FLTSUB,     /* 69 - INV | OFL | IMP | STK */
  308         FPE_FLTUND,     /* 6A - DNML | OFL | IMP | STK */
  309         FPE_FLTSUB,     /* 6B - INV | DNML | OFL | IMP | STK */
  310         FPE_FLTDIV,     /* 6C - DZ | OFL | IMP | STK */
  311         FPE_FLTSUB,     /* 6D - INV | DZ | OFL | IMP | STK */
  312         FPE_FLTDIV,     /* 6E - DNML | DZ | OFL | IMP | STK */
  313         FPE_FLTSUB,     /* 6F - INV | DNML | DZ | OFL | IMP | STK */
  314         FPE_FLTUND,     /* 70 - UFL | IMP | STK */
  315         FPE_FLTSUB,     /* 71 - INV | UFL | IMP | STK */
  316         FPE_FLTUND,     /* 72 - DNML | UFL | IMP | STK */
  317         FPE_FLTSUB,     /* 73 - INV | DNML | UFL | IMP | STK */
  318         FPE_FLTDIV,     /* 74 - DZ | UFL | IMP | STK */
  319         FPE_FLTSUB,     /* 75 - INV | DZ | UFL | IMP | STK */
  320         FPE_FLTDIV,     /* 76 - DNML | DZ | UFL | IMP | STK */
  321         FPE_FLTSUB,     /* 77 - INV | DNML | DZ | UFL | IMP | STK */
  322         FPE_FLTOVF,     /* 78 - OFL | UFL | IMP | STK */
  323         FPE_FLTSUB,     /* 79 - INV | OFL | UFL | IMP | STK */
  324         FPE_FLTUND,     /* 7A - DNML | OFL | UFL | IMP | STK */
  325         FPE_FLTSUB,     /* 7B - INV | DNML | OFL | UFL | IMP | STK */
  326         FPE_FLTDIV,     /* 7C - DZ | OFL | UFL | IMP | STK */
  327         FPE_FLTSUB,     /* 7D - INV | DZ | OFL | UFL | IMP | STK */
  328         FPE_FLTDIV,     /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
  329         FPE_FLTSUB,     /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
  330 };
  331 
  332 /*
  333  * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
  334  *
  335  * Clearing exceptions is necessary mainly to avoid IRQ13 bugs.  We now
  336  * depend on longjmp() restoring a usable state.  Restoring the state
  337  * or examining it might fail if we didn't clear exceptions.
  338  *
  339  * The error code chosen will be one of the FPE_... macros. It will be
  340  * sent as the second argument to old BSD-style signal handlers and as
  341  * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
  342  *
  343  * XXX the FP state is not preserved across signal handlers.  So signal
  344  * handlers cannot afford to do FP unless they preserve the state or
  345  * longjmp() out.  Both preserving the state and longjmp()ing may be
  346  * destroyed by IRQ13 bugs.  Clearing FP exceptions is not an acceptable
  347  * solution for signals other than SIGFPE.
  348  */
  349 int
  350 fputrap()
  351 {
  352         register_t savecrit;
  353         u_short control, status;
  354 
  355         savecrit = intr_disable();
  356 
  357         /*
  358          * Interrupt handling (for another interrupt) may have pushed the
  359          * state to memory.  Fetch the relevant parts of the state from
  360          * wherever they are.
  361          */
  362         if (PCPU_GET(fpcurthread) != curthread) {
  363                 control = GET_FPU_CW(curthread);
  364                 status = GET_FPU_SW(curthread);
  365         } else {
  366                 fnstcw(&control);
  367                 fnstsw(&status);
  368         }
  369 
  370         if (PCPU_GET(fpcurthread) == curthread)
  371                 fnclex();
  372         intr_restore(savecrit);
  373         return (fpetable[status & ((~control & 0x3f) | 0x40)]);
  374 }
  375 
  376 /*
  377  * Implement device not available (DNA) exception
  378  *
  379  * It would be better to switch FP context here (if curthread != fpcurthread)
  380  * and not necessarily for every context switch, but it is too hard to
  381  * access foreign pcb's.
  382  */
  383 
  384 static int err_count = 0;
  385 
  386 int
  387 fpudna()
  388 {
  389         struct pcb *pcb;
  390         register_t s;
  391 
  392         if (PCPU_GET(fpcurthread) == curthread) {
  393                 printf("fpudna: fpcurthread == curthread %d times\n",
  394                     ++err_count);
  395                 stop_emulating();
  396                 return (1);
  397         }
  398         if (PCPU_GET(fpcurthread) != NULL) {
  399                 printf("fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n",
  400                        PCPU_GET(fpcurthread),
  401                        PCPU_GET(fpcurthread)->td_proc->p_pid,
  402                        curthread, curthread->td_proc->p_pid);
  403                 panic("fpudna");
  404         }
  405         s = intr_disable();
  406         stop_emulating();
  407         /*
  408          * Record new context early in case frstor causes a trap.
  409          */
  410         PCPU_SET(fpcurthread, curthread);
  411         pcb = PCPU_GET(curpcb);
  412 
  413         fpu_clean_state();
  414 
  415         if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) {
  416                 /*
  417                  * This is the first time this thread has used the FPU,
  418                  * explicitly load sanitized registers.
  419                  */
  420                 fxrstor(&fpu_cleanstate);
  421                 pcb->pcb_flags |= PCB_FPUINITDONE;
  422         } else
  423                 fxrstor(&pcb->pcb_save);
  424         intr_restore(s);
  425 
  426         return (1);
  427 }
  428 
  429 /*
  430  * This should be called with interrupts disabled and only when the owning
  431  * FPU thread is non-null.
  432  */
  433 void
  434 fpudrop()
  435 {
  436         struct thread *td;
  437 
  438         td = PCPU_GET(fpcurthread);
  439         PCPU_SET(fpcurthread, NULL);
  440         td->td_pcb->pcb_flags &= ~PCB_FPUINITDONE;
  441         start_emulating();
  442 }
  443 
  444 /*
  445  * Get the state of the FPU without dropping ownership (if possible).
  446  * It returns the FPU ownership status.
  447  */
  448 int
  449 fpugetregs(struct thread *td, struct savefpu *addr)
  450 {
  451         register_t s;
  452 
  453         if ((td->td_pcb->pcb_flags & PCB_FPUINITDONE) == 0) {
  454                 if (fpu_cleanstate_ready)
  455                         bcopy(&fpu_cleanstate, addr, sizeof(fpu_cleanstate));
  456                 else
  457                         bzero(addr, sizeof(*addr));
  458                 return (_MC_FPOWNED_NONE);
  459         }
  460         s = intr_disable();
  461         if (td == PCPU_GET(fpcurthread)) {
  462                 fxsave(addr);
  463                 intr_restore(s);
  464                 return (_MC_FPOWNED_FPU);
  465         } else {
  466                 intr_restore(s);
  467                 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr));
  468                 return (_MC_FPOWNED_PCB);
  469         }
  470 }
  471 
  472 /*
  473  * Set the state of the FPU.
  474  */
  475 void
  476 fpusetregs(struct thread *td, struct savefpu *addr)
  477 {
  478         register_t s;
  479 
  480         s = intr_disable();
  481         if (td == PCPU_GET(fpcurthread)) {
  482                 fpu_clean_state();
  483                 fxrstor(addr);
  484                 intr_restore(s);
  485         } else {
  486                 intr_restore(s);
  487                 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr));
  488         }
  489         curthread->td_pcb->pcb_flags |= PCB_FPUINITDONE;
  490 }
  491 
  492 /*
  493  * On AuthenticAMD processors, the fxrstor instruction does not restore
  494  * the x87's stored last instruction pointer, last data pointer, and last
  495  * opcode values, except in the rare case in which the exception summary
  496  * (ES) bit in the x87 status word is set to 1.
  497  *
  498  * In order to avoid leaking this information across processes, we clean
  499  * these values by performing a dummy load before executing fxrstor().
  500  */
  501 static  double  dummy_variable = 0.0;
  502 static void
  503 fpu_clean_state(void)
  504 {
  505         u_short status;
  506 
  507         /*
  508          * Clear the ES bit in the x87 status word if it is currently
  509          * set, in order to avoid causing a fault in the upcoming load.
  510          */
  511         fnstsw(&status);
  512         if (status & 0x80)
  513                 fnclex();
  514 
  515         /*
  516          * Load the dummy variable into the x87 stack.  This mangles
  517          * the x87 stack, but we don't care since we're about to call
  518          * fxrstor() anyway.
  519          */
  520         __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable));
  521 }
  522 
  523 /*
  524  * This really sucks.  We want the acpi version only, but it requires
  525  * the isa_if.h file in order to get the definitions.
  526  */
  527 #include "opt_isa.h"
  528 #ifdef DEV_ISA
  529 #include <isa/isavar.h>
  530 /*
  531  * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
  532  */
  533 static struct isa_pnp_id fpupnp_ids[] = {
  534         { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
  535         { 0 }
  536 };
  537 
  538 static int
  539 fpupnp_probe(device_t dev)
  540 {
  541         int result;
  542 
  543         result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids);
  544         if (result <= 0)
  545                 device_quiet(dev);
  546         return (result);
  547 }
  548 
  549 static int
  550 fpupnp_attach(device_t dev)
  551 {
  552 
  553         return (0);
  554 }
  555 
  556 static device_method_t fpupnp_methods[] = {
  557         /* Device interface */
  558         DEVMETHOD(device_probe,         fpupnp_probe),
  559         DEVMETHOD(device_attach,        fpupnp_attach),
  560         DEVMETHOD(device_detach,        bus_generic_detach),
  561         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  562         DEVMETHOD(device_suspend,       bus_generic_suspend),
  563         DEVMETHOD(device_resume,        bus_generic_resume),
  564         
  565         { 0, 0 }
  566 };
  567 
  568 static driver_t fpupnp_driver = {
  569         "fpupnp",
  570         fpupnp_methods,
  571         1,                      /* no softc */
  572 };
  573 
  574 static devclass_t fpupnp_devclass;
  575 
  576 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0);
  577 #endif  /* DEV_ISA */

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