FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/fpu.c
1 /*-
2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 4. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: releng/6.4/sys/amd64/amd64/fpu.c 160062 2006-07-01 09:06:40Z davidxu $");
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/bus.h>
39 #include <sys/kernel.h>
40 #include <sys/lock.h>
41 #include <sys/malloc.h>
42 #include <sys/module.h>
43 #include <sys/mutex.h>
44 #include <sys/mutex.h>
45 #include <sys/proc.h>
46 #include <sys/sysctl.h>
47 #include <machine/bus.h>
48 #include <sys/rman.h>
49 #include <sys/signalvar.h>
50
51 #include <machine/cputypes.h>
52 #include <machine/frame.h>
53 #include <machine/intr_machdep.h>
54 #include <machine/md_var.h>
55 #include <machine/pcb.h>
56 #include <machine/psl.h>
57 #include <machine/resource.h>
58 #include <machine/specialreg.h>
59 #include <machine/segments.h>
60 #include <machine/ucontext.h>
61
62 /*
63 * Floating point support.
64 */
65
66 #if defined(__GNUCLIKE_ASM) && !defined(lint)
67
68 #define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr)))
69 #define fnclex() __asm("fnclex")
70 #define fninit() __asm("fninit")
71 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
72 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr)))
73 #define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr)))
74 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
75 #define ldmxcsr(r) __asm __volatile("ldmxcsr %0" : : "m" (r))
76 #define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
77 : : "n" (CR0_TS) : "ax")
78 #define stop_emulating() __asm("clts")
79
80 #else /* !(__GNUCLIKE_ASM && !lint) */
81
82 void fldcw(caddr_t addr);
83 void fnclex(void);
84 void fninit(void);
85 void fnstcw(caddr_t addr);
86 void fnstsw(caddr_t addr);
87 void fxsave(caddr_t addr);
88 void fxrstor(caddr_t addr);
89 void start_emulating(void);
90 void stop_emulating(void);
91
92 #endif /* __GNUCLIKE_ASM && !lint */
93
94 #define GET_FPU_CW(thread) ((thread)->td_pcb->pcb_save.sv_env.en_cw)
95 #define GET_FPU_SW(thread) ((thread)->td_pcb->pcb_save.sv_env.en_sw)
96
97 typedef u_char bool_t;
98
99 static void fpu_clean_state(void);
100
101 int hw_float = 1;
102 SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
103 CTLFLAG_RD, &hw_float, 0,
104 "Floatingpoint instructions executed in hardware");
105
106 static struct savefpu fpu_cleanstate;
107 static bool_t fpu_cleanstate_ready;
108
109 /*
110 * Initialize floating point unit.
111 */
112 void
113 fpuinit(void)
114 {
115 register_t savecrit;
116 u_int mxcsr;
117 u_short control;
118
119 savecrit = intr_disable();
120 PCPU_SET(fpcurthread, 0);
121 stop_emulating();
122 fninit();
123 control = __INITIAL_FPUCW__;
124 fldcw(&control);
125 mxcsr = __INITIAL_MXCSR__;
126 ldmxcsr(mxcsr);
127 fxsave(&fpu_cleanstate);
128 if (fpu_cleanstate.sv_env.en_mxcsr_mask)
129 cpu_mxcsr_mask = fpu_cleanstate.sv_env.en_mxcsr_mask;
130 else
131 cpu_mxcsr_mask = 0xFFBF;
132 start_emulating();
133 bzero(fpu_cleanstate.sv_fp, sizeof(fpu_cleanstate.sv_fp));
134 bzero(fpu_cleanstate.sv_xmm, sizeof(fpu_cleanstate.sv_xmm));
135 fpu_cleanstate_ready = 1;
136 intr_restore(savecrit);
137 }
138
139 /*
140 * Free coprocessor (if we have it).
141 */
142 void
143 fpuexit(struct thread *td)
144 {
145 register_t savecrit;
146
147 savecrit = intr_disable();
148 if (curthread == PCPU_GET(fpcurthread)) {
149 stop_emulating();
150 fxsave(&PCPU_GET(curpcb)->pcb_save);
151 start_emulating();
152 PCPU_SET(fpcurthread, 0);
153 }
154 intr_restore(savecrit);
155 }
156
157 int
158 fpuformat()
159 {
160
161 return (_MC_FPFMT_XMM);
162 }
163
164 /*
165 * The following mechanism is used to ensure that the FPE_... value
166 * that is passed as a trapcode to the signal handler of the user
167 * process does not have more than one bit set.
168 *
169 * Multiple bits may be set if the user process modifies the control
170 * word while a status word bit is already set. While this is a sign
171 * of bad coding, we have no choise than to narrow them down to one
172 * bit, since we must not send a trapcode that is not exactly one of
173 * the FPE_ macros.
174 *
175 * The mechanism has a static table with 127 entries. Each combination
176 * of the 7 FPU status word exception bits directly translates to a
177 * position in this table, where a single FPE_... value is stored.
178 * This FPE_... value stored there is considered the "most important"
179 * of the exception bits and will be sent as the signal code. The
180 * precedence of the bits is based upon Intel Document "Numerical
181 * Applications", Chapter "Special Computational Situations".
182 *
183 * The macro to choose one of these values does these steps: 1) Throw
184 * away status word bits that cannot be masked. 2) Throw away the bits
185 * currently masked in the control word, assuming the user isn't
186 * interested in them anymore. 3) Reinsert status word bit 7 (stack
187 * fault) if it is set, which cannot be masked but must be presered.
188 * 4) Use the remaining bits to point into the trapcode table.
189 *
190 * The 6 maskable bits in order of their preference, as stated in the
191 * above referenced Intel manual:
192 * 1 Invalid operation (FP_X_INV)
193 * 1a Stack underflow
194 * 1b Stack overflow
195 * 1c Operand of unsupported format
196 * 1d SNaN operand.
197 * 2 QNaN operand (not an exception, irrelavant here)
198 * 3 Any other invalid-operation not mentioned above or zero divide
199 * (FP_X_INV, FP_X_DZ)
200 * 4 Denormal operand (FP_X_DNML)
201 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
202 * 6 Inexact result (FP_X_IMP)
203 */
204 static char fpetable[128] = {
205 0,
206 FPE_FLTINV, /* 1 - INV */
207 FPE_FLTUND, /* 2 - DNML */
208 FPE_FLTINV, /* 3 - INV | DNML */
209 FPE_FLTDIV, /* 4 - DZ */
210 FPE_FLTINV, /* 5 - INV | DZ */
211 FPE_FLTDIV, /* 6 - DNML | DZ */
212 FPE_FLTINV, /* 7 - INV | DNML | DZ */
213 FPE_FLTOVF, /* 8 - OFL */
214 FPE_FLTINV, /* 9 - INV | OFL */
215 FPE_FLTUND, /* A - DNML | OFL */
216 FPE_FLTINV, /* B - INV | DNML | OFL */
217 FPE_FLTDIV, /* C - DZ | OFL */
218 FPE_FLTINV, /* D - INV | DZ | OFL */
219 FPE_FLTDIV, /* E - DNML | DZ | OFL */
220 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
221 FPE_FLTUND, /* 10 - UFL */
222 FPE_FLTINV, /* 11 - INV | UFL */
223 FPE_FLTUND, /* 12 - DNML | UFL */
224 FPE_FLTINV, /* 13 - INV | DNML | UFL */
225 FPE_FLTDIV, /* 14 - DZ | UFL */
226 FPE_FLTINV, /* 15 - INV | DZ | UFL */
227 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
228 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
229 FPE_FLTOVF, /* 18 - OFL | UFL */
230 FPE_FLTINV, /* 19 - INV | OFL | UFL */
231 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
232 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
233 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
234 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
235 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
236 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
237 FPE_FLTRES, /* 20 - IMP */
238 FPE_FLTINV, /* 21 - INV | IMP */
239 FPE_FLTUND, /* 22 - DNML | IMP */
240 FPE_FLTINV, /* 23 - INV | DNML | IMP */
241 FPE_FLTDIV, /* 24 - DZ | IMP */
242 FPE_FLTINV, /* 25 - INV | DZ | IMP */
243 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
244 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
245 FPE_FLTOVF, /* 28 - OFL | IMP */
246 FPE_FLTINV, /* 29 - INV | OFL | IMP */
247 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
248 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
249 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
250 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
251 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
252 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
253 FPE_FLTUND, /* 30 - UFL | IMP */
254 FPE_FLTINV, /* 31 - INV | UFL | IMP */
255 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
256 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
257 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
258 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
259 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
260 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
261 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
262 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
263 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
264 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
265 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
266 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
267 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
268 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
269 FPE_FLTSUB, /* 40 - STK */
270 FPE_FLTSUB, /* 41 - INV | STK */
271 FPE_FLTUND, /* 42 - DNML | STK */
272 FPE_FLTSUB, /* 43 - INV | DNML | STK */
273 FPE_FLTDIV, /* 44 - DZ | STK */
274 FPE_FLTSUB, /* 45 - INV | DZ | STK */
275 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
276 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
277 FPE_FLTOVF, /* 48 - OFL | STK */
278 FPE_FLTSUB, /* 49 - INV | OFL | STK */
279 FPE_FLTUND, /* 4A - DNML | OFL | STK */
280 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
281 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
282 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
283 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
284 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
285 FPE_FLTUND, /* 50 - UFL | STK */
286 FPE_FLTSUB, /* 51 - INV | UFL | STK */
287 FPE_FLTUND, /* 52 - DNML | UFL | STK */
288 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
289 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
290 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
291 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
292 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
293 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
294 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
295 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
296 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
297 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
298 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
299 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
300 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
301 FPE_FLTRES, /* 60 - IMP | STK */
302 FPE_FLTSUB, /* 61 - INV | IMP | STK */
303 FPE_FLTUND, /* 62 - DNML | IMP | STK */
304 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
305 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
306 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
307 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
308 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
309 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
310 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
311 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
312 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
313 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
314 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
315 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
316 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
317 FPE_FLTUND, /* 70 - UFL | IMP | STK */
318 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
319 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
320 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
321 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
322 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
323 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
324 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
325 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
326 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
327 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
328 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
329 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
330 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
331 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
332 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
333 };
334
335 /*
336 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
337 *
338 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now
339 * depend on longjmp() restoring a usable state. Restoring the state
340 * or examining it might fail if we didn't clear exceptions.
341 *
342 * The error code chosen will be one of the FPE_... macros. It will be
343 * sent as the second argument to old BSD-style signal handlers and as
344 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
345 *
346 * XXX the FP state is not preserved across signal handlers. So signal
347 * handlers cannot afford to do FP unless they preserve the state or
348 * longjmp() out. Both preserving the state and longjmp()ing may be
349 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable
350 * solution for signals other than SIGFPE.
351 */
352 int
353 fputrap()
354 {
355 register_t savecrit;
356 u_short control, status;
357
358 savecrit = intr_disable();
359
360 /*
361 * Interrupt handling (for another interrupt) may have pushed the
362 * state to memory. Fetch the relevant parts of the state from
363 * wherever they are.
364 */
365 if (PCPU_GET(fpcurthread) != curthread) {
366 control = GET_FPU_CW(curthread);
367 status = GET_FPU_SW(curthread);
368 } else {
369 fnstcw(&control);
370 fnstsw(&status);
371 }
372
373 if (PCPU_GET(fpcurthread) == curthread)
374 fnclex();
375 intr_restore(savecrit);
376 return (fpetable[status & ((~control & 0x3f) | 0x40)]);
377 }
378
379 /*
380 * Implement device not available (DNA) exception
381 *
382 * It would be better to switch FP context here (if curthread != fpcurthread)
383 * and not necessarily for every context switch, but it is too hard to
384 * access foreign pcb's.
385 */
386
387 static int err_count = 0;
388
389 int
390 fpudna()
391 {
392 struct pcb *pcb;
393 register_t s;
394
395 if (PCPU_GET(fpcurthread) == curthread) {
396 printf("fpudna: fpcurthread == curthread %d times\n",
397 ++err_count);
398 stop_emulating();
399 return (1);
400 }
401 if (PCPU_GET(fpcurthread) != NULL) {
402 printf("fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n",
403 PCPU_GET(fpcurthread),
404 PCPU_GET(fpcurthread)->td_proc->p_pid,
405 curthread, curthread->td_proc->p_pid);
406 panic("fpudna");
407 }
408 s = intr_disable();
409 stop_emulating();
410 /*
411 * Record new context early in case frstor causes a trap.
412 */
413 PCPU_SET(fpcurthread, curthread);
414 pcb = PCPU_GET(curpcb);
415
416 fpu_clean_state();
417
418 if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) {
419 /*
420 * This is the first time this thread has used the FPU,
421 * explicitly load sanitized registers.
422 */
423 fxrstor(&fpu_cleanstate);
424 pcb->pcb_flags |= PCB_FPUINITDONE;
425 } else
426 fxrstor(&pcb->pcb_save);
427 intr_restore(s);
428
429 return (1);
430 }
431
432 /*
433 * This should be called with interrupts disabled and only when the owning
434 * FPU thread is non-null.
435 */
436 void
437 fpudrop()
438 {
439 struct thread *td;
440
441 td = PCPU_GET(fpcurthread);
442 PCPU_SET(fpcurthread, NULL);
443 td->td_pcb->pcb_flags &= ~PCB_FPUINITDONE;
444 start_emulating();
445 }
446
447 /*
448 * Get the state of the FPU without dropping ownership (if possible).
449 * It returns the FPU ownership status.
450 */
451 int
452 fpugetregs(struct thread *td, struct savefpu *addr)
453 {
454 register_t s;
455
456 if ((td->td_pcb->pcb_flags & PCB_FPUINITDONE) == 0) {
457 if (fpu_cleanstate_ready)
458 bcopy(&fpu_cleanstate, addr, sizeof(fpu_cleanstate));
459 else
460 bzero(addr, sizeof(*addr));
461 return (_MC_FPOWNED_NONE);
462 }
463 s = intr_disable();
464 if (td == PCPU_GET(fpcurthread)) {
465 fxsave(addr);
466 intr_restore(s);
467 return (_MC_FPOWNED_FPU);
468 } else {
469 intr_restore(s);
470 bcopy(&td->td_pcb->pcb_save, addr, sizeof(*addr));
471 return (_MC_FPOWNED_PCB);
472 }
473 }
474
475 /*
476 * Set the state of the FPU.
477 */
478 void
479 fpusetregs(struct thread *td, struct savefpu *addr)
480 {
481 register_t s;
482
483 s = intr_disable();
484 if (td == PCPU_GET(fpcurthread)) {
485 fpu_clean_state();
486 fxrstor(addr);
487 intr_restore(s);
488 } else {
489 intr_restore(s);
490 bcopy(addr, &td->td_pcb->pcb_save, sizeof(*addr));
491 }
492 curthread->td_pcb->pcb_flags |= PCB_FPUINITDONE;
493 }
494
495 /*
496 * On AuthenticAMD processors, the fxrstor instruction does not restore
497 * the x87's stored last instruction pointer, last data pointer, and last
498 * opcode values, except in the rare case in which the exception summary
499 * (ES) bit in the x87 status word is set to 1.
500 *
501 * In order to avoid leaking this information across processes, we clean
502 * these values by performing a dummy load before executing fxrstor().
503 */
504 static double dummy_variable = 0.0;
505 static void
506 fpu_clean_state(void)
507 {
508 u_short status;
509
510 /*
511 * Clear the ES bit in the x87 status word if it is currently
512 * set, in order to avoid causing a fault in the upcoming load.
513 */
514 fnstsw(&status);
515 if (status & 0x80)
516 fnclex();
517
518 /*
519 * Load the dummy variable into the x87 stack. This mangles
520 * the x87 stack, but we don't care since we're about to call
521 * fxrstor() anyway.
522 */
523 __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable));
524 }
525
526 /*
527 * This really sucks. We want the acpi version only, but it requires
528 * the isa_if.h file in order to get the definitions.
529 */
530 #include "opt_isa.h"
531 #ifdef DEV_ISA
532 #include <isa/isavar.h>
533 /*
534 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
535 */
536 static struct isa_pnp_id fpupnp_ids[] = {
537 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
538 { 0 }
539 };
540
541 static int
542 fpupnp_probe(device_t dev)
543 {
544 int result;
545
546 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids);
547 if (result <= 0)
548 device_quiet(dev);
549 return (result);
550 }
551
552 static int
553 fpupnp_attach(device_t dev)
554 {
555
556 return (0);
557 }
558
559 static device_method_t fpupnp_methods[] = {
560 /* Device interface */
561 DEVMETHOD(device_probe, fpupnp_probe),
562 DEVMETHOD(device_attach, fpupnp_attach),
563 DEVMETHOD(device_detach, bus_generic_detach),
564 DEVMETHOD(device_shutdown, bus_generic_shutdown),
565 DEVMETHOD(device_suspend, bus_generic_suspend),
566 DEVMETHOD(device_resume, bus_generic_resume),
567
568 { 0, 0 }
569 };
570
571 static driver_t fpupnp_driver = {
572 "fpupnp",
573 fpupnp_methods,
574 1, /* no softc */
575 };
576
577 static devclass_t fpupnp_devclass;
578
579 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0);
580 #endif /* DEV_ISA */
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