FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/fpu.c
1 /*-
2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 4. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: releng/8.2/sys/amd64/amd64/fpu.c 216455 2010-12-15 15:15:42Z kib $");
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/bus.h>
39 #include <sys/kernel.h>
40 #include <sys/lock.h>
41 #include <sys/malloc.h>
42 #include <sys/module.h>
43 #include <sys/mutex.h>
44 #include <sys/mutex.h>
45 #include <sys/proc.h>
46 #include <sys/sysctl.h>
47 #include <machine/bus.h>
48 #include <sys/rman.h>
49 #include <sys/signalvar.h>
50
51 #include <machine/cputypes.h>
52 #include <machine/frame.h>
53 #include <machine/intr_machdep.h>
54 #include <machine/md_var.h>
55 #include <machine/pcb.h>
56 #include <machine/psl.h>
57 #include <machine/resource.h>
58 #include <machine/specialreg.h>
59 #include <machine/segments.h>
60 #include <machine/ucontext.h>
61
62 /*
63 * Floating point support.
64 */
65
66 #if defined(__GNUCLIKE_ASM) && !defined(lint)
67
68 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw))
69 #define fnclex() __asm __volatile("fnclex")
70 #define fninit() __asm __volatile("fninit")
71 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
72 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr)))
73 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr)))
74 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
75 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr))
76 #define start_emulating() __asm __volatile( \
77 "smsw %%ax; orb %0,%%al; lmsw %%ax" \
78 : : "n" (CR0_TS) : "ax")
79 #define stop_emulating() __asm __volatile("clts")
80
81 #else /* !(__GNUCLIKE_ASM && !lint) */
82
83 void fldcw(u_short cw);
84 void fnclex(void);
85 void fninit(void);
86 void fnstcw(caddr_t addr);
87 void fnstsw(caddr_t addr);
88 void fxsave(caddr_t addr);
89 void fxrstor(caddr_t addr);
90 void ldmxcsr(u_int csr);
91 void start_emulating(void);
92 void stop_emulating(void);
93
94 #endif /* __GNUCLIKE_ASM && !lint */
95
96 #define GET_FPU_CW(thread) ((thread)->td_pcb->pcb_save->sv_env.en_cw)
97 #define GET_FPU_SW(thread) ((thread)->td_pcb->pcb_save->sv_env.en_sw)
98
99 typedef u_char bool_t;
100
101 static void fpu_clean_state(void);
102
103 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD,
104 NULL, 1, "Floating point instructions executed in hardware");
105
106 static struct savefpu fpu_initialstate;
107
108 /*
109 * Initialize the floating point unit. On the boot CPU we generate a
110 * clean state that is used to initialize the floating point unit when
111 * it is first used by a process.
112 */
113 void
114 fpuinit(void)
115 {
116 register_t saveintr;
117 u_int mxcsr;
118 u_short control;
119
120 /*
121 * It is too early for critical_enter() to work on AP.
122 */
123 saveintr = intr_disable();
124 stop_emulating();
125 fninit();
126 control = __INITIAL_FPUCW__;
127 fldcw(control);
128 mxcsr = __INITIAL_MXCSR__;
129 ldmxcsr(mxcsr);
130 if (PCPU_GET(cpuid) == 0) {
131 fxsave(&fpu_initialstate);
132 if (fpu_initialstate.sv_env.en_mxcsr_mask)
133 cpu_mxcsr_mask = fpu_initialstate.sv_env.en_mxcsr_mask;
134 else
135 cpu_mxcsr_mask = 0xFFBF;
136 bzero(fpu_initialstate.sv_fp, sizeof(fpu_initialstate.sv_fp));
137 bzero(fpu_initialstate.sv_xmm, sizeof(fpu_initialstate.sv_xmm));
138 }
139 start_emulating();
140 intr_restore(saveintr);
141 }
142
143 /*
144 * Free coprocessor (if we have it).
145 */
146 void
147 fpuexit(struct thread *td)
148 {
149
150 critical_enter();
151 if (curthread == PCPU_GET(fpcurthread)) {
152 stop_emulating();
153 fxsave(PCPU_GET(curpcb)->pcb_save);
154 start_emulating();
155 PCPU_SET(fpcurthread, 0);
156 }
157 critical_exit();
158 }
159
160 int
161 fpuformat()
162 {
163
164 return (_MC_FPFMT_XMM);
165 }
166
167 /*
168 * The following mechanism is used to ensure that the FPE_... value
169 * that is passed as a trapcode to the signal handler of the user
170 * process does not have more than one bit set.
171 *
172 * Multiple bits may be set if the user process modifies the control
173 * word while a status word bit is already set. While this is a sign
174 * of bad coding, we have no choise than to narrow them down to one
175 * bit, since we must not send a trapcode that is not exactly one of
176 * the FPE_ macros.
177 *
178 * The mechanism has a static table with 127 entries. Each combination
179 * of the 7 FPU status word exception bits directly translates to a
180 * position in this table, where a single FPE_... value is stored.
181 * This FPE_... value stored there is considered the "most important"
182 * of the exception bits and will be sent as the signal code. The
183 * precedence of the bits is based upon Intel Document "Numerical
184 * Applications", Chapter "Special Computational Situations".
185 *
186 * The macro to choose one of these values does these steps: 1) Throw
187 * away status word bits that cannot be masked. 2) Throw away the bits
188 * currently masked in the control word, assuming the user isn't
189 * interested in them anymore. 3) Reinsert status word bit 7 (stack
190 * fault) if it is set, which cannot be masked but must be presered.
191 * 4) Use the remaining bits to point into the trapcode table.
192 *
193 * The 6 maskable bits in order of their preference, as stated in the
194 * above referenced Intel manual:
195 * 1 Invalid operation (FP_X_INV)
196 * 1a Stack underflow
197 * 1b Stack overflow
198 * 1c Operand of unsupported format
199 * 1d SNaN operand.
200 * 2 QNaN operand (not an exception, irrelavant here)
201 * 3 Any other invalid-operation not mentioned above or zero divide
202 * (FP_X_INV, FP_X_DZ)
203 * 4 Denormal operand (FP_X_DNML)
204 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
205 * 6 Inexact result (FP_X_IMP)
206 */
207 static char fpetable[128] = {
208 0,
209 FPE_FLTINV, /* 1 - INV */
210 FPE_FLTUND, /* 2 - DNML */
211 FPE_FLTINV, /* 3 - INV | DNML */
212 FPE_FLTDIV, /* 4 - DZ */
213 FPE_FLTINV, /* 5 - INV | DZ */
214 FPE_FLTDIV, /* 6 - DNML | DZ */
215 FPE_FLTINV, /* 7 - INV | DNML | DZ */
216 FPE_FLTOVF, /* 8 - OFL */
217 FPE_FLTINV, /* 9 - INV | OFL */
218 FPE_FLTUND, /* A - DNML | OFL */
219 FPE_FLTINV, /* B - INV | DNML | OFL */
220 FPE_FLTDIV, /* C - DZ | OFL */
221 FPE_FLTINV, /* D - INV | DZ | OFL */
222 FPE_FLTDIV, /* E - DNML | DZ | OFL */
223 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
224 FPE_FLTUND, /* 10 - UFL */
225 FPE_FLTINV, /* 11 - INV | UFL */
226 FPE_FLTUND, /* 12 - DNML | UFL */
227 FPE_FLTINV, /* 13 - INV | DNML | UFL */
228 FPE_FLTDIV, /* 14 - DZ | UFL */
229 FPE_FLTINV, /* 15 - INV | DZ | UFL */
230 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
231 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
232 FPE_FLTOVF, /* 18 - OFL | UFL */
233 FPE_FLTINV, /* 19 - INV | OFL | UFL */
234 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
235 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
236 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
237 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
238 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
239 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
240 FPE_FLTRES, /* 20 - IMP */
241 FPE_FLTINV, /* 21 - INV | IMP */
242 FPE_FLTUND, /* 22 - DNML | IMP */
243 FPE_FLTINV, /* 23 - INV | DNML | IMP */
244 FPE_FLTDIV, /* 24 - DZ | IMP */
245 FPE_FLTINV, /* 25 - INV | DZ | IMP */
246 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
247 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
248 FPE_FLTOVF, /* 28 - OFL | IMP */
249 FPE_FLTINV, /* 29 - INV | OFL | IMP */
250 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
251 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
252 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
253 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
254 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
255 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
256 FPE_FLTUND, /* 30 - UFL | IMP */
257 FPE_FLTINV, /* 31 - INV | UFL | IMP */
258 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
259 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
260 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
261 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
262 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
263 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
264 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
265 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
266 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
267 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
268 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
269 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
270 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
271 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
272 FPE_FLTSUB, /* 40 - STK */
273 FPE_FLTSUB, /* 41 - INV | STK */
274 FPE_FLTUND, /* 42 - DNML | STK */
275 FPE_FLTSUB, /* 43 - INV | DNML | STK */
276 FPE_FLTDIV, /* 44 - DZ | STK */
277 FPE_FLTSUB, /* 45 - INV | DZ | STK */
278 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
279 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
280 FPE_FLTOVF, /* 48 - OFL | STK */
281 FPE_FLTSUB, /* 49 - INV | OFL | STK */
282 FPE_FLTUND, /* 4A - DNML | OFL | STK */
283 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
284 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
285 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
286 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
287 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
288 FPE_FLTUND, /* 50 - UFL | STK */
289 FPE_FLTSUB, /* 51 - INV | UFL | STK */
290 FPE_FLTUND, /* 52 - DNML | UFL | STK */
291 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
292 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
293 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
294 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
295 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
296 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
297 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
298 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
299 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
300 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
301 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
302 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
303 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
304 FPE_FLTRES, /* 60 - IMP | STK */
305 FPE_FLTSUB, /* 61 - INV | IMP | STK */
306 FPE_FLTUND, /* 62 - DNML | IMP | STK */
307 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
308 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
309 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
310 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
311 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
312 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
313 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
314 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
315 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
316 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
317 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
318 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
319 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
320 FPE_FLTUND, /* 70 - UFL | IMP | STK */
321 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
322 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
323 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
324 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
325 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
326 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
327 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
328 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
329 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
330 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
331 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
332 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
333 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
334 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
335 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
336 };
337
338 /*
339 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
340 *
341 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now
342 * depend on longjmp() restoring a usable state. Restoring the state
343 * or examining it might fail if we didn't clear exceptions.
344 *
345 * The error code chosen will be one of the FPE_... macros. It will be
346 * sent as the second argument to old BSD-style signal handlers and as
347 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
348 *
349 * XXX the FP state is not preserved across signal handlers. So signal
350 * handlers cannot afford to do FP unless they preserve the state or
351 * longjmp() out. Both preserving the state and longjmp()ing may be
352 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable
353 * solution for signals other than SIGFPE.
354 */
355 int
356 fputrap()
357 {
358 u_short control, status;
359
360 critical_enter();
361
362 /*
363 * Interrupt handling (for another interrupt) may have pushed the
364 * state to memory. Fetch the relevant parts of the state from
365 * wherever they are.
366 */
367 if (PCPU_GET(fpcurthread) != curthread) {
368 control = GET_FPU_CW(curthread);
369 status = GET_FPU_SW(curthread);
370 } else {
371 fnstcw(&control);
372 fnstsw(&status);
373 }
374
375 if (PCPU_GET(fpcurthread) == curthread)
376 fnclex();
377 critical_exit();
378 return (fpetable[status & ((~control & 0x3f) | 0x40)]);
379 }
380
381 /*
382 * Implement device not available (DNA) exception
383 *
384 * It would be better to switch FP context here (if curthread != fpcurthread)
385 * and not necessarily for every context switch, but it is too hard to
386 * access foreign pcb's.
387 */
388
389 static int err_count = 0;
390
391 void
392 fpudna(void)
393 {
394 struct pcb *pcb;
395
396 critical_enter();
397 if (PCPU_GET(fpcurthread) == curthread) {
398 printf("fpudna: fpcurthread == curthread %d times\n",
399 ++err_count);
400 stop_emulating();
401 critical_exit();
402 return;
403 }
404 if (PCPU_GET(fpcurthread) != NULL) {
405 printf("fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n",
406 PCPU_GET(fpcurthread),
407 PCPU_GET(fpcurthread)->td_proc->p_pid,
408 curthread, curthread->td_proc->p_pid);
409 panic("fpudna");
410 }
411 stop_emulating();
412 /*
413 * Record new context early in case frstor causes a trap.
414 */
415 PCPU_SET(fpcurthread, curthread);
416 pcb = PCPU_GET(curpcb);
417
418 fpu_clean_state();
419
420 if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) {
421 /*
422 * This is the first time this thread has used the FPU or
423 * the PCB doesn't contain a clean FPU state. Explicitly
424 * load an initial state.
425 */
426 fxrstor(&fpu_initialstate);
427 if (pcb->pcb_initial_fpucw != __INITIAL_FPUCW__)
428 fldcw(pcb->pcb_initial_fpucw);
429 pcb->pcb_flags |= PCB_FPUINITDONE;
430 if (PCB_USER_FPU(pcb))
431 pcb->pcb_flags |= PCB_USERFPUINITDONE;
432 } else
433 fxrstor(pcb->pcb_save);
434 critical_exit();
435 }
436
437 void
438 fpudrop()
439 {
440 struct thread *td;
441
442 td = PCPU_GET(fpcurthread);
443 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread"));
444 CRITICAL_ASSERT(td);
445 PCPU_SET(fpcurthread, NULL);
446 td->td_pcb->pcb_flags &= ~PCB_FPUINITDONE;
447 start_emulating();
448 }
449
450 /*
451 * Get the user state of the FPU into pcb->pcb_user_save without
452 * dropping ownership (if possible). It returns the FPU ownership
453 * status.
454 */
455 int
456 fpugetregs(struct thread *td)
457 {
458 struct pcb *pcb;
459
460 pcb = td->td_pcb;
461 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) {
462 bcopy(&fpu_initialstate, &pcb->pcb_user_save,
463 sizeof(fpu_initialstate));
464 pcb->pcb_user_save.sv_env.en_cw = pcb->pcb_initial_fpucw;
465 fpuuserinited(td);
466 return (_MC_FPOWNED_PCB);
467 }
468 critical_enter();
469 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
470 fxsave(&pcb->pcb_user_save);
471 critical_exit();
472 return (_MC_FPOWNED_FPU);
473 } else {
474 critical_exit();
475 return (_MC_FPOWNED_PCB);
476 }
477 }
478
479 void
480 fpuuserinited(struct thread *td)
481 {
482 struct pcb *pcb;
483
484 pcb = td->td_pcb;
485 if (PCB_USER_FPU(pcb))
486 pcb->pcb_flags |= PCB_FPUINITDONE;
487 pcb->pcb_flags |= PCB_USERFPUINITDONE;
488 }
489
490 /*
491 * Set the state of the FPU.
492 */
493 void
494 fpusetregs(struct thread *td, struct savefpu *addr)
495 {
496 struct pcb *pcb;
497
498 pcb = td->td_pcb;
499 critical_enter();
500 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
501 fxrstor(addr);
502 critical_exit();
503 pcb->pcb_flags |= PCB_FPUINITDONE | PCB_USERFPUINITDONE;
504 } else {
505 critical_exit();
506 bcopy(addr, &td->td_pcb->pcb_user_save, sizeof(*addr));
507 fpuuserinited(td);
508 }
509 }
510
511 /*
512 * On AuthenticAMD processors, the fxrstor instruction does not restore
513 * the x87's stored last instruction pointer, last data pointer, and last
514 * opcode values, except in the rare case in which the exception summary
515 * (ES) bit in the x87 status word is set to 1.
516 *
517 * In order to avoid leaking this information across processes, we clean
518 * these values by performing a dummy load before executing fxrstor().
519 */
520 static void
521 fpu_clean_state(void)
522 {
523 static float dummy_variable = 0.0;
524 u_short status;
525
526 /*
527 * Clear the ES bit in the x87 status word if it is currently
528 * set, in order to avoid causing a fault in the upcoming load.
529 */
530 fnstsw(&status);
531 if (status & 0x80)
532 fnclex();
533
534 /*
535 * Load the dummy variable into the x87 stack. This mangles
536 * the x87 stack, but we don't care since we're about to call
537 * fxrstor() anyway.
538 */
539 __asm __volatile("ffree %%st(7); fld %0" : : "m" (dummy_variable));
540 }
541
542 /*
543 * This really sucks. We want the acpi version only, but it requires
544 * the isa_if.h file in order to get the definitions.
545 */
546 #include "opt_isa.h"
547 #ifdef DEV_ISA
548 #include <isa/isavar.h>
549 /*
550 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
551 */
552 static struct isa_pnp_id fpupnp_ids[] = {
553 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
554 { 0 }
555 };
556
557 static int
558 fpupnp_probe(device_t dev)
559 {
560 int result;
561
562 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids);
563 if (result <= 0)
564 device_quiet(dev);
565 return (result);
566 }
567
568 static int
569 fpupnp_attach(device_t dev)
570 {
571
572 return (0);
573 }
574
575 static device_method_t fpupnp_methods[] = {
576 /* Device interface */
577 DEVMETHOD(device_probe, fpupnp_probe),
578 DEVMETHOD(device_attach, fpupnp_attach),
579 DEVMETHOD(device_detach, bus_generic_detach),
580 DEVMETHOD(device_shutdown, bus_generic_shutdown),
581 DEVMETHOD(device_suspend, bus_generic_suspend),
582 DEVMETHOD(device_resume, bus_generic_resume),
583
584 { 0, 0 }
585 };
586
587 static driver_t fpupnp_driver = {
588 "fpupnp",
589 fpupnp_methods,
590 1, /* no softc */
591 };
592
593 static devclass_t fpupnp_devclass;
594
595 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0);
596 #endif /* DEV_ISA */
597
598 int
599 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags)
600 {
601 struct pcb *pcb;
602
603 pcb = td->td_pcb;
604 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save == &pcb->pcb_user_save,
605 ("mangled pcb_save"));
606 ctx->flags = 0;
607 if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0)
608 ctx->flags |= FPU_KERN_CTX_FPUINITDONE;
609 fpuexit(td);
610 ctx->prev = pcb->pcb_save;
611 pcb->pcb_save = &ctx->hwstate;
612 pcb->pcb_flags |= PCB_KERNFPU;
613 pcb->pcb_flags &= ~PCB_FPUINITDONE;
614 return (0);
615 }
616
617 int
618 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx)
619 {
620 struct pcb *pcb;
621
622 pcb = td->td_pcb;
623 critical_enter();
624 if (curthread == PCPU_GET(fpcurthread))
625 fpudrop();
626 critical_exit();
627 pcb->pcb_save = ctx->prev;
628 if (pcb->pcb_save == &pcb->pcb_user_save) {
629 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0)
630 pcb->pcb_flags |= PCB_FPUINITDONE;
631 else
632 pcb->pcb_flags &= ~PCB_FPUINITDONE;
633 pcb->pcb_flags &= ~PCB_KERNFPU;
634 } else {
635 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0)
636 pcb->pcb_flags |= PCB_FPUINITDONE;
637 else
638 pcb->pcb_flags &= ~PCB_FPUINITDONE;
639 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave"));
640 }
641 return (0);
642 }
643
644 int
645 fpu_kern_thread(u_int flags)
646 {
647 struct pcb *pcb;
648
649 pcb = PCPU_GET(curpcb);
650 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0,
651 ("Only kthread may use fpu_kern_thread"));
652 KASSERT(pcb->pcb_save == &pcb->pcb_user_save, ("mangled pcb_save"));
653 KASSERT(PCB_USER_FPU(pcb), ("recursive call"));
654
655 pcb->pcb_flags |= PCB_KERNFPU;
656 return (0);
657 }
658
659 int
660 is_fpu_kern_thread(u_int flags)
661 {
662
663 if ((curthread->td_pflags & TDP_KTHREAD) == 0)
664 return (0);
665 return ((PCPU_GET(curpcb)->pcb_flags & PCB_KERNFPU) != 0);
666 }
Cache object: 9212125b497071532aef18f8ec87d3a7
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