The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/identcpu.c

Version: -  FREEBSD  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-2  -  FREEBSD-11-1  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-4  -  FREEBSD-10-3  -  FREEBSD-10-2  -  FREEBSD-10-1  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-3  -  FREEBSD-9-2  -  FREEBSD-9-1  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-4  -  FREEBSD-8-3  -  FREEBSD-8-2  -  FREEBSD-8-1  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-4  -  FREEBSD-7-3  -  FREEBSD-7-2  -  FREEBSD-7-1  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-4  -  FREEBSD-6-3  -  FREEBSD-6-2  -  FREEBSD-6-1  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-5  -  FREEBSD-5-4  -  FREEBSD-5-3  -  FREEBSD-5-2  -  FREEBSD-5-1  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  linux-2.6  -  linux-2.4.22  -  MK83  -  MK84  -  PLAN9  -  DFBSD  -  NETBSD  -  NETBSD5  -  NETBSD4  -  NETBSD3  -  NETBSD20  -  OPENBSD  -  xnu-517  -  xnu-792  -  xnu-792.6.70  -  xnu-1228  -  xnu-1456.1.26  -  xnu-1699.24.8  -  xnu-2050.18.24  -  OPENSOLARIS  -  minix-3-1-1 
SearchContext: -  none  -  3  -  10 

    1 /*-
    2  * Copyright (c) 1992 Terrence R. Lambert.
    3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
    4  * Copyright (c) 1997 KATO Takenori.
    5  * Copyright (c) 2001 Tamotsu Hattori.
    6  * Copyright (c) 2001 Mitsuru IWASAKI.
    7  * All rights reserved.
    8  *
    9  * This code is derived from software contributed to Berkeley by
   10  * William Jolitz.
   11  *
   12  * Redistribution and use in source and binary forms, with or without
   13  * modification, are permitted provided that the following conditions
   14  * are met:
   15  * 1. Redistributions of source code must retain the above copyright
   16  *    notice, this list of conditions and the following disclaimer.
   17  * 2. Redistributions in binary form must reproduce the above copyright
   18  *    notice, this list of conditions and the following disclaimer in the
   19  *    documentation and/or other materials provided with the distribution.
   20  * 3. All advertising materials mentioning features or use of this software
   21  *    must display the following acknowledgement:
   22  *      This product includes software developed by the University of
   23  *      California, Berkeley and its contributors.
   24  * 4. Neither the name of the University nor the names of its contributors
   25  *    may be used to endorse or promote products derived from this software
   26  *    without specific prior written permission.
   27  *
   28  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   31  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   32  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   38  * SUCH DAMAGE.
   39  *
   40  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
   41  */
   42 
   43 #include <sys/cdefs.h>
   44 __FBSDID("$FreeBSD: releng/5.3/sys/amd64/amd64/identcpu.c 130227 2004-06-08 01:20:37Z peter $");
   45 
   46 #include "opt_cpu.h"
   47 
   48 #include <sys/param.h>
   49 #include <sys/bus.h>
   50 #include <sys/systm.h>
   51 #include <sys/kernel.h>
   52 #include <sys/sysctl.h>
   53 #include <sys/power.h>
   54 
   55 #include <machine/asmacros.h>
   56 #include <machine/clock.h>
   57 #include <machine/cputypes.h>
   58 #include <machine/frame.h>
   59 #include <machine/intr_machdep.h>
   60 #include <machine/segments.h>
   61 #include <machine/specialreg.h>
   62 #include <machine/md_var.h>
   63 
   64 #include <amd64/isa/icu.h>
   65 
   66 /* XXX - should be in header file: */
   67 void printcpuinfo(void);
   68 void identify_cpu(void);
   69 void earlysetcpuclass(void);
   70 void panicifcpuunsupported(void);
   71 
   72 static void print_AMD_info(void);
   73 static void print_AMD_assoc(int i);
   74 
   75 int     cpu_class;
   76 char machine[] = "amd64";
   77 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 
   78     machine, 0, "Machine class");
   79 
   80 static char cpu_model[128];
   81 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 
   82     cpu_model, 0, "Machine model");
   83 
   84 static int hw_clockrate;
   85 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 
   86     &hw_clockrate, 0, "CPU instruction clock rate");
   87 
   88 static char cpu_brand[48];
   89 
   90 static struct {
   91         char    *cpu_name;
   92         int     cpu_class;
   93 } amd64_cpus[] = {
   94         { "Clawhammer",         CPUCLASS_K8 },          /* CPU_CLAWHAMMER */
   95         { "Sledgehammer",       CPUCLASS_K8 },          /* CPU_SLEDGEHAMMER */
   96 };
   97 
   98 void
   99 printcpuinfo(void)
  100 {
  101         u_int regs[4], i;
  102         char *brand;
  103 
  104         cpu_class = amd64_cpus[cpu].cpu_class;
  105         printf("CPU: ");
  106         strncpy(cpu_model, amd64_cpus[cpu].cpu_name, sizeof (cpu_model));
  107 
  108         /* Check for extended CPUID information and a processor name. */
  109         if (cpu_exthigh >= 0x80000004) {
  110                 brand = cpu_brand;
  111                 for (i = 0x80000002; i < 0x80000005; i++) {
  112                         do_cpuid(i, regs);
  113                         memcpy(brand, regs, sizeof(regs));
  114                         brand += sizeof(regs);
  115                 }
  116         }
  117 
  118         if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
  119                 /* Please make up your mind folks! */
  120                 strcat(cpu_model, "EM64T");
  121         } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
  122                 /*
  123                  * Values taken from AMD Processor Recognition
  124                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
  125                  * (also describes ``Features'' encodings.
  126                  */
  127                 strcpy(cpu_model, "AMD ");
  128                 switch (cpu_id & 0xF00) {
  129                 case 0xf00:
  130                         strcat(cpu_model, "AMD64 Processor");
  131                         break;
  132                 default:
  133                         strcat(cpu_model, "Unknown");
  134                         break;
  135                 }
  136         }
  137 
  138         /*
  139          * Replace cpu_model with cpu_brand minus leading spaces if
  140          * we have one.
  141          */
  142         brand = cpu_brand;
  143         while (*brand == ' ')
  144                 ++brand;
  145         if (*brand != '\0')
  146                 strcpy(cpu_model, brand);
  147 
  148         printf("%s (", cpu_model);
  149         switch(cpu_class) {
  150         case CPUCLASS_K8:
  151                 hw_clockrate = (tsc_freq + 5000) / 1000000;
  152                 printf("%jd.%02d-MHz ",
  153                        (intmax_t)(tsc_freq + 4999) / 1000000,
  154                        (u_int)((tsc_freq + 4999) / 10000) % 100);
  155                 printf("K8");
  156                 break;
  157         default:
  158                 printf("Unknown");      /* will panic below... */
  159         }
  160         printf("-class CPU)\n");
  161         if(*cpu_vendor)
  162                 printf("  Origin = \"%s\"",cpu_vendor);
  163         if(cpu_id)
  164                 printf("  Id = 0x%x", cpu_id);
  165 
  166         if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
  167             strcmp(cpu_vendor, "AuthenticAMD") == 0) {
  168                 printf("  Stepping = %u", cpu_id & 0xf);
  169                 if (cpu_high > 0) {
  170                         /*
  171                          * Here we should probably set up flags indicating
  172                          * whether or not various features are available.
  173                          * The interesting ones are probably VME, PSE, PAE,
  174                          * and PGE.  The code already assumes without bothering
  175                          * to check that all CPUs >= Pentium have a TSC and
  176                          * MSRs.
  177                          */
  178                         printf("\n  Features=0x%b", cpu_feature,
  179                         "\020"
  180                         "\001FPU"       /* Integral FPU */
  181                         "\002VME"       /* Extended VM86 mode support */
  182                         "\003DE"        /* Debugging Extensions (CR4.DE) */
  183                         "\004PSE"       /* 4MByte page tables */
  184                         "\005TSC"       /* Timestamp counter */
  185                         "\006MSR"       /* Machine specific registers */
  186                         "\007PAE"       /* Physical address extension */
  187                         "\010MCE"       /* Machine Check support */
  188                         "\011CX8"       /* CMPEXCH8 instruction */
  189                         "\012APIC"      /* SMP local APIC */
  190                         "\013oldMTRR"   /* Previous implementation of MTRR */
  191                         "\014SEP"       /* Fast System Call */
  192                         "\015MTRR"      /* Memory Type Range Registers */
  193                         "\016PGE"       /* PG_G (global bit) support */
  194                         "\017MCA"       /* Machine Check Architecture */
  195                         "\020CMOV"      /* CMOV instruction */
  196                         "\021PAT"       /* Page attributes table */
  197                         "\022PSE36"     /* 36 bit address space support */
  198                         "\023PN"        /* Processor Serial number */
  199                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
  200                         "\025<b20>"
  201                         "\026DTS"       /* Debug Trace Store */
  202                         "\027ACPI"      /* ACPI support */
  203                         "\030MMX"       /* MMX instructions */
  204                         "\031FXSR"      /* FXSAVE/FXRSTOR */
  205                         "\032SSE"       /* Streaming SIMD Extensions */
  206                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
  207                         "\034SS"        /* Self snoop */
  208                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
  209                         "\036TM"        /* Thermal Monitor clock slowdown */
  210                         "\037IA64"      /* CPU can execute IA64 instructions */
  211                         "\040PBE"       /* Pending Break Enable */
  212                         );
  213 
  214                         if (cpu_feature2 != 0) {
  215                                 printf("\n  Features2=0x%b", cpu_feature2,
  216                                 "\020"
  217                                 "\001SSE3"      /* SSE3 */
  218                                 "\002<b1>"
  219                                 "\003RSVD2>"    /* "Reserved" bit 2 */
  220                                 "\004MON"       /* MONITOR/MWAIT Instructions */
  221                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
  222                                 "\006<b5>"      /* Machine specific registers */
  223                                 "\007<b6>"      /* Physical address extension */
  224                                 "\010EST"       /* Enhanced SpeedStep */
  225                                 "\011TM2"       /* Thermal Monitor 2 */
  226                                 "\012<b9>"
  227                                 "\013CNTX-ID"   /* L1 context ID available */
  228                                 "\014<b11>"
  229                                 "\015<b12>"
  230                                 "\016CX16"      /* CMPXCHG16B Instruction */
  231                                 "\017<b14>"
  232                                 "\020<b15>"
  233                                 "\021<b16>"
  234                                 "\022<b17>"
  235                                 "\023<b18>"
  236                                 "\024<b19>"
  237                                 "\025<b20>"
  238                                 "\026<b21>"
  239                                 "\027<b22>"
  240                                 "\030<b23>"
  241                                 "\031<b24>"
  242                                 "\032<b25>"
  243                                 "\033<b26>"
  244                                 "\034<b27>"
  245                                 "\035<b28>"
  246                                 "\036<b29>"
  247                                 "\037<b30>"
  248                                 "\040<b31>"
  249                                 );
  250                         }
  251                         if (amd_feature != 0) {
  252                                 printf("\n  AMD Features=0x%b", amd_feature,
  253                                 "\020"          /* in hex */
  254                                 "\001<s0>"      /* Same */
  255                                 "\002<s1>"      /* Same */
  256                                 "\003<s2>"      /* Same */
  257                                 "\004<s3>"      /* Same */
  258                                 "\005<s4>"      /* Same */
  259                                 "\006<s5>"      /* Same */
  260                                 "\007<s6>"      /* Same */
  261                                 "\010<s7>"      /* Same */
  262                                 "\011<s8>"      /* Same */
  263                                 "\012<s9>"      /* Same */
  264                                 "\013<b10>"     /* Undefined */
  265                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
  266                                 "\015<s12>"     /* Same */
  267                                 "\016<s13>"     /* Same */
  268                                 "\017<s14>"     /* Same */
  269                                 "\020<s15>"     /* Same */
  270                                 "\021<s16>"     /* Same */
  271                                 "\022<s17>"     /* Same */
  272                                 "\023<b18>"     /* Reserved, unknown */
  273                                 "\024MP"        /* Multiprocessor Capable */
  274                                 "\025NX"        /* Has EFER.NXE, NX */
  275                                 "\026<b21>"     /* Undefined */
  276                                 "\027MMX+"      /* AMD MMX Extensions */
  277                                 "\030<s23>"     /* Same */
  278                                 "\031<s24>"     /* Same */
  279                                 "\032<b25>"     /* Undefined */
  280                                 "\033<b26>"     /* Undefined */
  281                                 "\034<b27>"     /* Undefined */
  282                                 "\035<b28>"     /* Undefined */
  283                                 "\036LM"        /* 64 bit long mode */
  284                                 "\0373DNow+"    /* AMD 3DNow! Extensions */
  285                                 "\0403DNow"     /* AMD 3DNow! */
  286                                 );
  287                         }
  288 
  289                         /*
  290                          * If this CPU supports hyperthreading then mention
  291                          * the number of logical CPU's it contains.
  292                          */
  293                         if (cpu_feature & CPUID_HTT &&
  294                             (cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1)
  295                                 printf("\n  Hyperthreading: %d logical CPUs",
  296                                     (cpu_procinfo & CPUID_HTT_CORES) >> 16);
  297                 }
  298         }
  299         /* Avoid ugly blank lines: only print newline when we have to. */
  300         if (*cpu_vendor || cpu_id)
  301                 printf("\n");
  302 
  303         if (!bootverbose)
  304                 return;
  305 
  306         if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
  307                 print_AMD_info();
  308 }
  309 
  310 void
  311 panicifcpuunsupported(void)
  312 {
  313 
  314 #ifndef HAMMER
  315 #error "You need to specify a cpu type"
  316 #endif
  317         /*
  318          * Now that we have told the user what they have,
  319          * let them know if that machine type isn't configured.
  320          */
  321         switch (cpu_class) {
  322         case CPUCLASS_X86:
  323 #ifndef HAMMER
  324         case CPUCLASS_K8:
  325 #endif
  326                 panic("CPU class not configured");
  327         default:
  328                 break;
  329         }
  330 }
  331 
  332 
  333 /*
  334  * Final stage of CPU identification. -- Should I check TI?
  335  */
  336 void
  337 identify_cpu(void)
  338 {
  339         u_int regs[4];
  340 
  341         do_cpuid(0, regs);
  342         cpu_high = regs[0];
  343         ((u_int *)&cpu_vendor)[0] = regs[1];
  344         ((u_int *)&cpu_vendor)[1] = regs[3];
  345         ((u_int *)&cpu_vendor)[2] = regs[2];
  346         cpu_vendor[12] = '\0';
  347 
  348         do_cpuid(1, regs);
  349         cpu_id = regs[0];
  350         cpu_procinfo = regs[1];
  351         cpu_feature = regs[3];
  352         cpu_feature2 = regs[2];
  353 
  354         if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
  355             strcmp(cpu_vendor, "AuthenticAMD") == 0) {
  356                 do_cpuid(0x80000000, regs);
  357                 cpu_exthigh = regs[0];
  358         }
  359         if (cpu_exthigh >= 0x80000001) {
  360                 do_cpuid(0x80000001, regs);
  361                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
  362         }
  363 
  364         /* XXX */
  365         cpu = CPU_CLAWHAMMER;
  366 }
  367 
  368 static void
  369 print_AMD_assoc(int i)
  370 {
  371         if (i == 255)
  372                 printf(", fully associative\n");
  373         else
  374                 printf(", %d-way associative\n", i);
  375 }
  376 
  377 static void
  378 print_AMD_l2_assoc(int i)
  379 {
  380         switch (i & 0x0f) {
  381         case 0: printf(", disabled/not present\n"); break;
  382         case 1: printf(", direct mapped\n"); break;
  383         case 2: printf(", 2-way associative\n"); break;
  384         case 4: printf(", 4-way associative\n"); break;
  385         case 6: printf(", 8-way associative\n"); break;
  386         case 8: printf(", 16-way associative\n"); break;
  387         case 15: printf(", fully associative\n"); break;
  388         default: printf(", reserved configuration\n"); break;
  389         }
  390 }
  391 
  392 static void
  393 print_AMD_info(void)
  394 {
  395         u_int regs[4];
  396 
  397         if (cpu_exthigh < 0x80000005)
  398                 return;
  399 
  400         do_cpuid(0x80000005, regs);
  401         printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
  402         print_AMD_assoc(regs[0] >> 24);
  403 
  404         printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
  405         print_AMD_assoc((regs[0] >> 8) & 0xff);
  406 
  407         printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
  408         print_AMD_assoc(regs[1] >> 24);
  409 
  410         printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
  411         print_AMD_assoc((regs[1] >> 8) & 0xff);
  412 
  413         printf("L1 data cache: %d kbytes", regs[2] >> 24);
  414         printf(", %d bytes/line", regs[2] & 0xff);
  415         printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
  416         print_AMD_assoc((regs[2] >> 16) & 0xff);
  417 
  418         printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
  419         printf(", %d bytes/line", regs[3] & 0xff);
  420         printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
  421         print_AMD_assoc((regs[3] >> 16) & 0xff);
  422 
  423         if (cpu_exthigh >= 0x80000006) {
  424                 do_cpuid(0x80000006, regs);
  425                 if ((regs[0] >> 16) != 0) {
  426                         printf("L2 2MB data TLB: %d entries",
  427                             (regs[0] >> 16) & 0xfff);
  428                         print_AMD_l2_assoc(regs[0] >> 28);
  429                         printf("L2 2MB instruction TLB: %d entries",
  430                             regs[0] & 0xfff);
  431                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
  432                 } else {
  433                         printf("L2 2MB unified TLB: %d entries",
  434                             regs[0] & 0xfff);
  435                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
  436                 }
  437                 if ((regs[1] >> 16) != 0) {
  438                         printf("L2 4KB data TLB: %d entries",
  439                             (regs[1] >> 16) & 0xfff);
  440                         print_AMD_l2_assoc(regs[1] >> 28);
  441 
  442                         printf("L2 4KB instruction TLB: %d entries",
  443                             (regs[1] >> 16) & 0xfff);
  444                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
  445                 } else {
  446                         printf("L2 4KB unified TLB: %d entries",
  447                             (regs[1] >> 16) & 0xfff);
  448                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
  449                 }
  450                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
  451                 printf(", %d bytes/line", regs[2] & 0xff);
  452                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
  453                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);     
  454         }
  455 }

Cache object: efe2684955ac24dd8d480de31b8033d3


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.