The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/identcpu.c

Version: -  FREEBSD  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-2  -  FREEBSD-11-1  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-4  -  FREEBSD-10-3  -  FREEBSD-10-2  -  FREEBSD-10-1  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-3  -  FREEBSD-9-2  -  FREEBSD-9-1  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-4  -  FREEBSD-8-3  -  FREEBSD-8-2  -  FREEBSD-8-1  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-4  -  FREEBSD-7-3  -  FREEBSD-7-2  -  FREEBSD-7-1  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-4  -  FREEBSD-6-3  -  FREEBSD-6-2  -  FREEBSD-6-1  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-5  -  FREEBSD-5-4  -  FREEBSD-5-3  -  FREEBSD-5-2  -  FREEBSD-5-1  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  linux-2.6  -  linux-2.4.22  -  MK83  -  MK84  -  PLAN9  -  DFBSD  -  NETBSD  -  NETBSD5  -  NETBSD4  -  NETBSD3  -  NETBSD20  -  OPENBSD  -  xnu-517  -  xnu-792  -  xnu-792.6.70  -  xnu-1228  -  xnu-1456.1.26  -  xnu-1699.24.8  -  xnu-2050.18.24  -  OPENSOLARIS  -  minix-3-1-1 
SearchContext: -  none  -  3  -  10 

    1 /*-
    2  * Copyright (c) 1992 Terrence R. Lambert.
    3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
    4  * Copyright (c) 1997 KATO Takenori.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to Berkeley by
    8  * William Jolitz.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. All advertising materials mentioning features or use of this software
   19  *    must display the following acknowledgement:
   20  *      This product includes software developed by the University of
   21  *      California, Berkeley and its contributors.
   22  * 4. Neither the name of the University nor the names of its contributors
   23  *    may be used to endorse or promote products derived from this software
   24  *    without specific prior written permission.
   25  *
   26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   36  * SUCH DAMAGE.
   37  *
   38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
   39  */
   40 
   41 #include <sys/cdefs.h>
   42 __FBSDID("$FreeBSD: src/sys/amd64/amd64/identcpu.c,v 1.134.2.2 2005/06/05 08:44:08 schweikh Exp $");
   43 
   44 #include "opt_cpu.h"
   45 
   46 #include <sys/param.h>
   47 #include <sys/bus.h>
   48 #include <sys/systm.h>
   49 #include <sys/kernel.h>
   50 #include <sys/sysctl.h>
   51 #include <sys/power.h>
   52 
   53 #include <machine/asmacros.h>
   54 #include <machine/clock.h>
   55 #include <machine/cputypes.h>
   56 #include <machine/frame.h>
   57 #include <machine/intr_machdep.h>
   58 #include <machine/segments.h>
   59 #include <machine/specialreg.h>
   60 #include <machine/md_var.h>
   61 
   62 #include <amd64/isa/icu.h>
   63 
   64 /* XXX - should be in header file: */
   65 void printcpuinfo(void);
   66 void identify_cpu(void);
   67 void earlysetcpuclass(void);
   68 void panicifcpuunsupported(void);
   69 
   70 static void print_AMD_info(void);
   71 static void print_AMD_assoc(int i);
   72 
   73 int     cpu_class;
   74 char machine[] = "amd64";
   75 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 
   76     machine, 0, "Machine class");
   77 
   78 static char cpu_model[128];
   79 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 
   80     cpu_model, 0, "Machine model");
   81 
   82 static int hw_clockrate;
   83 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 
   84     &hw_clockrate, 0, "CPU instruction clock rate");
   85 
   86 static char cpu_brand[48];
   87 
   88 static struct {
   89         char    *cpu_name;
   90         int     cpu_class;
   91 } amd64_cpus[] = {
   92         { "Clawhammer",         CPUCLASS_K8 },          /* CPU_CLAWHAMMER */
   93         { "Sledgehammer",       CPUCLASS_K8 },          /* CPU_SLEDGEHAMMER */
   94 };
   95 
   96 void
   97 printcpuinfo(void)
   98 {
   99         u_int regs[4], i;
  100         char *brand;
  101 
  102         cpu_class = amd64_cpus[cpu].cpu_class;
  103         printf("CPU: ");
  104         strncpy(cpu_model, amd64_cpus[cpu].cpu_name, sizeof (cpu_model));
  105 
  106         /* Check for extended CPUID information and a processor name. */
  107         if (cpu_exthigh >= 0x80000004) {
  108                 brand = cpu_brand;
  109                 for (i = 0x80000002; i < 0x80000005; i++) {
  110                         do_cpuid(i, regs);
  111                         memcpy(brand, regs, sizeof(regs));
  112                         brand += sizeof(regs);
  113                 }
  114         }
  115 
  116         if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
  117                 /* Please make up your mind folks! */
  118                 strcat(cpu_model, "EM64T");
  119         } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
  120                 /*
  121                  * Values taken from AMD Processor Recognition
  122                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
  123                  * (also describes ``Features'' encodings.
  124                  */
  125                 strcpy(cpu_model, "AMD ");
  126                 switch (cpu_id & 0xF00) {
  127                 case 0xf00:
  128                         strcat(cpu_model, "AMD64 Processor");
  129                         break;
  130                 default:
  131                         strcat(cpu_model, "Unknown");
  132                         break;
  133                 }
  134         }
  135 
  136         /*
  137          * Replace cpu_model with cpu_brand minus leading spaces if
  138          * we have one.
  139          */
  140         brand = cpu_brand;
  141         while (*brand == ' ')
  142                 ++brand;
  143         if (*brand != '\0')
  144                 strcpy(cpu_model, brand);
  145 
  146         printf("%s (", cpu_model);
  147         switch(cpu_class) {
  148         case CPUCLASS_K8:
  149                 hw_clockrate = (tsc_freq + 5000) / 1000000;
  150                 printf("%jd.%02d-MHz ",
  151                        (intmax_t)(tsc_freq + 4999) / 1000000,
  152                        (u_int)((tsc_freq + 4999) / 10000) % 100);
  153                 printf("K8");
  154                 break;
  155         default:
  156                 printf("Unknown");      /* will panic below... */
  157         }
  158         printf("-class CPU)\n");
  159         if(*cpu_vendor)
  160                 printf("  Origin = \"%s\"",cpu_vendor);
  161         if(cpu_id)
  162                 printf("  Id = 0x%x", cpu_id);
  163 
  164         if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
  165             strcmp(cpu_vendor, "AuthenticAMD") == 0) {
  166                 printf("  Stepping = %u", cpu_id & 0xf);
  167                 if (cpu_high > 0) {
  168                         /*
  169                          * Here we should probably set up flags indicating
  170                          * whether or not various features are available.
  171                          * The interesting ones are probably VME, PSE, PAE,
  172                          * and PGE.  The code already assumes without bothering
  173                          * to check that all CPUs >= Pentium have a TSC and
  174                          * MSRs.
  175                          */
  176                         printf("\n  Features=0x%b", cpu_feature,
  177                         "\020"
  178                         "\001FPU"       /* Integral FPU */
  179                         "\002VME"       /* Extended VM86 mode support */
  180                         "\003DE"        /* Debugging Extensions (CR4.DE) */
  181                         "\004PSE"       /* 4MByte page tables */
  182                         "\005TSC"       /* Timestamp counter */
  183                         "\006MSR"       /* Machine specific registers */
  184                         "\007PAE"       /* Physical address extension */
  185                         "\010MCE"       /* Machine Check support */
  186                         "\011CX8"       /* CMPEXCH8 instruction */
  187                         "\012APIC"      /* SMP local APIC */
  188                         "\013oldMTRR"   /* Previous implementation of MTRR */
  189                         "\014SEP"       /* Fast System Call */
  190                         "\015MTRR"      /* Memory Type Range Registers */
  191                         "\016PGE"       /* PG_G (global bit) support */
  192                         "\017MCA"       /* Machine Check Architecture */
  193                         "\020CMOV"      /* CMOV instruction */
  194                         "\021PAT"       /* Page attributes table */
  195                         "\022PSE36"     /* 36 bit address space support */
  196                         "\023PN"        /* Processor Serial number */
  197                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
  198                         "\025<b20>"
  199                         "\026DTS"       /* Debug Trace Store */
  200                         "\027ACPI"      /* ACPI support */
  201                         "\030MMX"       /* MMX instructions */
  202                         "\031FXSR"      /* FXSAVE/FXRSTOR */
  203                         "\032SSE"       /* Streaming SIMD Extensions */
  204                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
  205                         "\034SS"        /* Self snoop */
  206                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
  207                         "\036TM"        /* Thermal Monitor clock slowdown */
  208                         "\037IA64"      /* CPU can execute IA64 instructions */
  209                         "\040PBE"       /* Pending Break Enable */
  210                         );
  211 
  212                         if (cpu_feature2 != 0) {
  213                                 printf("\n  Features2=0x%b", cpu_feature2,
  214                                 "\020"
  215                                 "\001SSE3"      /* SSE3 */
  216                                 "\002<b1>"
  217                                 "\003RSVD2"     /* "Reserved" bit 2 */
  218                                 "\004MON"       /* MONITOR/MWAIT Instructions */
  219                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
  220                                 "\006<b5>"      /* Machine specific registers */
  221                                 "\007<b6>"      /* Physical address extension */
  222                                 "\010EST"       /* Enhanced SpeedStep */
  223                                 "\011TM2"       /* Thermal Monitor 2 */
  224                                 "\012<b9>"
  225                                 "\013CNTX-ID"   /* L1 context ID available */
  226                                 "\014<b11>"
  227                                 "\015<b12>"
  228                                 "\016CX16"      /* CMPXCHG16B Instruction */
  229                                 "\017<b14>"
  230                                 "\020<b15>"
  231                                 "\021<b16>"
  232                                 "\022<b17>"
  233                                 "\023<b18>"
  234                                 "\024<b19>"
  235                                 "\025<b20>"
  236                                 "\026<b21>"
  237                                 "\027<b22>"
  238                                 "\030<b23>"
  239                                 "\031<b24>"
  240                                 "\032<b25>"
  241                                 "\033<b26>"
  242                                 "\034<b27>"
  243                                 "\035<b28>"
  244                                 "\036<b29>"
  245                                 "\037<b30>"
  246                                 "\040<b31>"
  247                                 );
  248                         }
  249                         if (amd_feature != 0) {
  250                                 printf("\n  AMD Features=0x%b", amd_feature,
  251                                 "\020"          /* in hex */
  252                                 "\001<s0>"      /* Same */
  253                                 "\002<s1>"      /* Same */
  254                                 "\003<s2>"      /* Same */
  255                                 "\004<s3>"      /* Same */
  256                                 "\005<s4>"      /* Same */
  257                                 "\006<s5>"      /* Same */
  258                                 "\007<s6>"      /* Same */
  259                                 "\010<s7>"      /* Same */
  260                                 "\011<s8>"      /* Same */
  261                                 "\012<s9>"      /* Same */
  262                                 "\013<b10>"     /* Undefined */
  263                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
  264                                 "\015<s12>"     /* Same */
  265                                 "\016<s13>"     /* Same */
  266                                 "\017<s14>"     /* Same */
  267                                 "\020<s15>"     /* Same */
  268                                 "\021<s16>"     /* Same */
  269                                 "\022<s17>"     /* Same */
  270                                 "\023<b18>"     /* Reserved, unknown */
  271                                 "\024MP"        /* Multiprocessor Capable */
  272                                 "\025NX"        /* Has EFER.NXE, NX */
  273                                 "\026<b21>"     /* Undefined */
  274                                 "\027MMX+"      /* AMD MMX Extensions */
  275                                 "\030<s23>"     /* Same */
  276                                 "\031<s24>"     /* Same */
  277                                 "\032<b25>"     /* Undefined */
  278                                 "\033<b26>"     /* Undefined */
  279                                 "\034<b27>"     /* Undefined */
  280                                 "\035<b28>"     /* Undefined */
  281                                 "\036LM"        /* 64 bit long mode */
  282                                 "\0373DNow+"    /* AMD 3DNow! Extensions */
  283                                 "\0403DNow"     /* AMD 3DNow! */
  284                                 );
  285                         }
  286 
  287                         /*
  288                          * If this CPU supports hyperthreading then mention
  289                          * the number of logical CPU's it contains.
  290                          */
  291                         if (cpu_feature & CPUID_HTT &&
  292                             (cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1)
  293                                 printf("\n  Hyperthreading: %d logical CPUs",
  294                                     (cpu_procinfo & CPUID_HTT_CORES) >> 16);
  295                 }
  296         }
  297         /* Avoid ugly blank lines: only print newline when we have to. */
  298         if (*cpu_vendor || cpu_id)
  299                 printf("\n");
  300 
  301         if (!bootverbose)
  302                 return;
  303 
  304         if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
  305                 print_AMD_info();
  306 }
  307 
  308 void
  309 panicifcpuunsupported(void)
  310 {
  311 
  312 #ifndef HAMMER
  313 #error "You need to specify a cpu type"
  314 #endif
  315         /*
  316          * Now that we have told the user what they have,
  317          * let them know if that machine type isn't configured.
  318          */
  319         switch (cpu_class) {
  320         case CPUCLASS_X86:
  321 #ifndef HAMMER
  322         case CPUCLASS_K8:
  323 #endif
  324                 panic("CPU class not configured");
  325         default:
  326                 break;
  327         }
  328 }
  329 
  330 
  331 /*
  332  * Final stage of CPU identification. -- Should I check TI?
  333  */
  334 void
  335 identify_cpu(void)
  336 {
  337         u_int regs[4];
  338 
  339         do_cpuid(0, regs);
  340         cpu_high = regs[0];
  341         ((u_int *)&cpu_vendor)[0] = regs[1];
  342         ((u_int *)&cpu_vendor)[1] = regs[3];
  343         ((u_int *)&cpu_vendor)[2] = regs[2];
  344         cpu_vendor[12] = '\0';
  345 
  346         do_cpuid(1, regs);
  347         cpu_id = regs[0];
  348         cpu_procinfo = regs[1];
  349         cpu_feature = regs[3];
  350         cpu_feature2 = regs[2];
  351 
  352         if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
  353             strcmp(cpu_vendor, "AuthenticAMD") == 0) {
  354                 do_cpuid(0x80000000, regs);
  355                 cpu_exthigh = regs[0];
  356         }
  357         if (cpu_exthigh >= 0x80000001) {
  358                 do_cpuid(0x80000001, regs);
  359                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
  360         }
  361 
  362         /* XXX */
  363         cpu = CPU_CLAWHAMMER;
  364 }
  365 
  366 static void
  367 print_AMD_assoc(int i)
  368 {
  369         if (i == 255)
  370                 printf(", fully associative\n");
  371         else
  372                 printf(", %d-way associative\n", i);
  373 }
  374 
  375 static void
  376 print_AMD_l2_assoc(int i)
  377 {
  378         switch (i & 0x0f) {
  379         case 0: printf(", disabled/not present\n"); break;
  380         case 1: printf(", direct mapped\n"); break;
  381         case 2: printf(", 2-way associative\n"); break;
  382         case 4: printf(", 4-way associative\n"); break;
  383         case 6: printf(", 8-way associative\n"); break;
  384         case 8: printf(", 16-way associative\n"); break;
  385         case 15: printf(", fully associative\n"); break;
  386         default: printf(", reserved configuration\n"); break;
  387         }
  388 }
  389 
  390 static void
  391 print_AMD_info(void)
  392 {
  393         u_int regs[4];
  394 
  395         if (cpu_exthigh < 0x80000005)
  396                 return;
  397 
  398         do_cpuid(0x80000005, regs);
  399         printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
  400         print_AMD_assoc(regs[0] >> 24);
  401 
  402         printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
  403         print_AMD_assoc((regs[0] >> 8) & 0xff);
  404 
  405         printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
  406         print_AMD_assoc(regs[1] >> 24);
  407 
  408         printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
  409         print_AMD_assoc((regs[1] >> 8) & 0xff);
  410 
  411         printf("L1 data cache: %d kbytes", regs[2] >> 24);
  412         printf(", %d bytes/line", regs[2] & 0xff);
  413         printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
  414         print_AMD_assoc((regs[2] >> 16) & 0xff);
  415 
  416         printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
  417         printf(", %d bytes/line", regs[3] & 0xff);
  418         printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
  419         print_AMD_assoc((regs[3] >> 16) & 0xff);
  420 
  421         if (cpu_exthigh >= 0x80000006) {
  422                 do_cpuid(0x80000006, regs);
  423                 if ((regs[0] >> 16) != 0) {
  424                         printf("L2 2MB data TLB: %d entries",
  425                             (regs[0] >> 16) & 0xfff);
  426                         print_AMD_l2_assoc(regs[0] >> 28);
  427                         printf("L2 2MB instruction TLB: %d entries",
  428                             regs[0] & 0xfff);
  429                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
  430                 } else {
  431                         printf("L2 2MB unified TLB: %d entries",
  432                             regs[0] & 0xfff);
  433                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
  434                 }
  435                 if ((regs[1] >> 16) != 0) {
  436                         printf("L2 4KB data TLB: %d entries",
  437                             (regs[1] >> 16) & 0xfff);
  438                         print_AMD_l2_assoc(regs[1] >> 28);
  439 
  440                         printf("L2 4KB instruction TLB: %d entries",
  441                             (regs[1] >> 16) & 0xfff);
  442                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
  443                 } else {
  444                         printf("L2 4KB unified TLB: %d entries",
  445                             (regs[1] >> 16) & 0xfff);
  446                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
  447                 }
  448                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
  449                 printf(", %d bytes/line", regs[2] & 0xff);
  450                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
  451                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);     
  452         }
  453 }

Cache object: 1dcbfd31eec1ac8af0f317e4a1d7afdc


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.