Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/identcpu.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD: releng/6.2/sys/amd64/amd64/identcpu.c 157998 2006-04-24 18:24:31Z jkim $"); 43 44 #include "opt_cpu.h" 45 46 #include <sys/param.h> 47 #include <sys/bus.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/sysctl.h> 51 #include <sys/power.h> 52 53 #include <machine/asmacros.h> 54 #include <machine/clock.h> 55 #include <machine/cputypes.h> 56 #include <machine/frame.h> 57 #include <machine/intr_machdep.h> 58 #include <machine/segments.h> 59 #include <machine/specialreg.h> 60 #include <machine/md_var.h> 61 62 #include <amd64/isa/icu.h> 63 64 /* XXX - should be in header file: */ 65 void printcpuinfo(void); 66 void identify_cpu(void); 67 void earlysetcpuclass(void); 68 void panicifcpuunsupported(void); 69 70 static void print_AMD_info(void); 71 static void print_AMD_assoc(int i); 72 73 int cpu_class; 74 char machine[] = "amd64"; 75 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 76 machine, 0, "Machine class"); 77 78 static char cpu_model[128]; 79 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 80 cpu_model, 0, "Machine model"); 81 82 static int hw_clockrate; 83 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 84 &hw_clockrate, 0, "CPU instruction clock rate"); 85 86 static char cpu_brand[48]; 87 88 static struct { 89 char *cpu_name; 90 int cpu_class; 91 } amd64_cpus[] = { 92 { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */ 93 { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */ 94 }; 95 96 void 97 printcpuinfo(void) 98 { 99 u_int regs[4], i; 100 char *brand; 101 102 cpu_class = amd64_cpus[cpu].cpu_class; 103 printf("CPU: "); 104 strncpy(cpu_model, amd64_cpus[cpu].cpu_name, sizeof (cpu_model)); 105 106 /* Check for extended CPUID information and a processor name. */ 107 if (cpu_exthigh >= 0x80000004) { 108 brand = cpu_brand; 109 for (i = 0x80000002; i < 0x80000005; i++) { 110 do_cpuid(i, regs); 111 memcpy(brand, regs, sizeof(regs)); 112 brand += sizeof(regs); 113 } 114 } 115 116 if (strcmp(cpu_vendor, "GenuineIntel") == 0) { 117 /* Please make up your mind folks! */ 118 strcat(cpu_model, "EM64T"); 119 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { 120 /* 121 * Values taken from AMD Processor Recognition 122 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 123 * (also describes ``Features'' encodings. 124 */ 125 strcpy(cpu_model, "AMD "); 126 switch (cpu_id & 0xF00) { 127 case 0xf00: 128 strcat(cpu_model, "AMD64 Processor"); 129 break; 130 default: 131 strcat(cpu_model, "Unknown"); 132 break; 133 } 134 } 135 136 /* 137 * Replace cpu_model with cpu_brand minus leading spaces if 138 * we have one. 139 */ 140 brand = cpu_brand; 141 while (*brand == ' ') 142 ++brand; 143 if (*brand != '\0') 144 strcpy(cpu_model, brand); 145 146 printf("%s (", cpu_model); 147 switch(cpu_class) { 148 case CPUCLASS_K8: 149 hw_clockrate = (tsc_freq + 5000) / 1000000; 150 printf("%jd.%02d-MHz ", 151 (intmax_t)(tsc_freq + 4999) / 1000000, 152 (u_int)((tsc_freq + 4999) / 10000) % 100); 153 printf("K8"); 154 break; 155 default: 156 printf("Unknown"); /* will panic below... */ 157 } 158 printf("-class CPU)\n"); 159 if(*cpu_vendor) 160 printf(" Origin = \"%s\"",cpu_vendor); 161 if(cpu_id) 162 printf(" Id = 0x%x", cpu_id); 163 164 if (strcmp(cpu_vendor, "GenuineIntel") == 0 || 165 strcmp(cpu_vendor, "AuthenticAMD") == 0) { 166 printf(" Stepping = %u", cpu_id & 0xf); 167 if (cpu_high > 0) { 168 u_int cmp = 1, htt = 1; 169 170 /* 171 * Here we should probably set up flags indicating 172 * whether or not various features are available. 173 * The interesting ones are probably VME, PSE, PAE, 174 * and PGE. The code already assumes without bothering 175 * to check that all CPUs >= Pentium have a TSC and 176 * MSRs. 177 */ 178 printf("\n Features=0x%b", cpu_feature, 179 "\020" 180 "\001FPU" /* Integral FPU */ 181 "\002VME" /* Extended VM86 mode support */ 182 "\003DE" /* Debugging Extensions (CR4.DE) */ 183 "\004PSE" /* 4MByte page tables */ 184 "\005TSC" /* Timestamp counter */ 185 "\006MSR" /* Machine specific registers */ 186 "\007PAE" /* Physical address extension */ 187 "\010MCE" /* Machine Check support */ 188 "\011CX8" /* CMPEXCH8 instruction */ 189 "\012APIC" /* SMP local APIC */ 190 "\013oldMTRR" /* Previous implementation of MTRR */ 191 "\014SEP" /* Fast System Call */ 192 "\015MTRR" /* Memory Type Range Registers */ 193 "\016PGE" /* PG_G (global bit) support */ 194 "\017MCA" /* Machine Check Architecture */ 195 "\020CMOV" /* CMOV instruction */ 196 "\021PAT" /* Page attributes table */ 197 "\022PSE36" /* 36 bit address space support */ 198 "\023PN" /* Processor Serial number */ 199 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 200 "\025<b20>" 201 "\026DTS" /* Debug Trace Store */ 202 "\027ACPI" /* ACPI support */ 203 "\030MMX" /* MMX instructions */ 204 "\031FXSR" /* FXSAVE/FXRSTOR */ 205 "\032SSE" /* Streaming SIMD Extensions */ 206 "\033SSE2" /* Streaming SIMD Extensions #2 */ 207 "\034SS" /* Self snoop */ 208 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 209 "\036TM" /* Thermal Monitor clock slowdown */ 210 "\037IA64" /* CPU can execute IA64 instructions */ 211 "\040PBE" /* Pending Break Enable */ 212 ); 213 214 if (cpu_feature2 != 0) { 215 printf("\n Features2=0x%b", cpu_feature2, 216 "\020" 217 "\001SSE3" /* SSE3 */ 218 "\002<b1>" 219 "\003RSVD2" /* "Reserved" bit 2 */ 220 "\004MON" /* MONITOR/MWAIT Instructions */ 221 "\005DS_CPL" /* CPL Qualified Debug Store */ 222 "\006VMX" /* Virtual Machine Extensions */ 223 "\007<b6>" 224 "\010EST" /* Enhanced SpeedStep */ 225 "\011TM2" /* Thermal Monitor 2 */ 226 "\012<b9>" 227 "\013CNTX-ID" /* L1 context ID available */ 228 "\014<b11>" 229 "\015<b12>" 230 "\016CX16" /* CMPXCHG16B Instruction */ 231 "\017<b14>" 232 "\020<b15>" 233 "\021<b16>" 234 "\022<b17>" 235 "\023<b18>" 236 "\024<b19>" 237 "\025<b20>" 238 "\026<b21>" 239 "\027<b22>" 240 "\030<b23>" 241 "\031<b24>" 242 "\032<b25>" 243 "\033<b26>" 244 "\034<b27>" 245 "\035<b28>" 246 "\036<b29>" 247 "\037<b30>" 248 "\040<b31>" 249 ); 250 } 251 252 /* 253 * AMD64 Architecture Programmer's Manual Volume 3: 254 * General-Purpose and System Instructions 255 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf 256 * 257 * IA-32 Intel Architecture Software Developer's Manual, 258 * Volume 2A: Instruction Set Reference, A-M 259 * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf 260 */ 261 if (amd_feature != 0) { 262 printf("\n AMD Features=0x%b", amd_feature, 263 "\020" /* in hex */ 264 "\001<s0>" /* Same */ 265 "\002<s1>" /* Same */ 266 "\003<s2>" /* Same */ 267 "\004<s3>" /* Same */ 268 "\005<s4>" /* Same */ 269 "\006<s5>" /* Same */ 270 "\007<s6>" /* Same */ 271 "\010<s7>" /* Same */ 272 "\011<s8>" /* Same */ 273 "\012<s9>" /* Same */ 274 "\013<b10>" /* Undefined */ 275 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 276 "\015<s12>" /* Same */ 277 "\016<s13>" /* Same */ 278 "\017<s14>" /* Same */ 279 "\020<s15>" /* Same */ 280 "\021<s16>" /* Same */ 281 "\022<s17>" /* Same */ 282 "\023<b18>" /* Reserved, unknown */ 283 "\024MP" /* Multiprocessor Capable */ 284 "\025NX" /* Has EFER.NXE, NX */ 285 "\026<b21>" /* Undefined */ 286 "\027MMX+" /* AMD MMX Extensions */ 287 "\030<s23>" /* Same */ 288 "\031<s24>" /* Same */ 289 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 290 "\033<b26>" /* Undefined */ 291 "\034RDTSCP" /* RDTSCP */ 292 "\035<b28>" /* Undefined */ 293 "\036LM" /* 64 bit long mode */ 294 "\0373DNow+" /* AMD 3DNow! Extensions */ 295 "\0403DNow" /* AMD 3DNow! */ 296 ); 297 } 298 299 if (amd_feature2 != 0) { 300 printf("\n AMD Features2=0x%b", amd_feature2, 301 "\020" 302 "\001LAHF" /* LAHF/SAHF in long mode */ 303 "\002CMP" /* CMP legacy */ 304 "\003<b2>" 305 "\004<b3>" 306 "\005CR8" /* CR8 in legacy mode */ 307 "\006<b5>" 308 "\007<b6>" 309 "\010<b7>" 310 "\011<b8>" 311 "\012<b9>" 312 "\013<b10>" 313 "\014<b11>" 314 "\015<b12>" 315 "\016<b13>" 316 "\017<b14>" 317 "\020<b15>" 318 "\021<b16>" 319 "\022<b17>" 320 "\023<b18>" 321 "\024<b19>" 322 "\025<b20>" 323 "\026<b21>" 324 "\027<b22>" 325 "\030<b23>" 326 "\031<b24>" 327 "\032<b25>" 328 "\033<b26>" 329 "\034<b27>" 330 "\035<b28>" 331 "\036<b29>" 332 "\037<b30>" 333 "\040<b31>" 334 ); 335 } 336 337 if (cpu_feature & CPUID_HTT && strcmp(cpu_vendor, 338 "AuthenticAMD") == 0) { 339 cpu_feature &= ~CPUID_HTT; 340 if (bootverbose) 341 printf("\n HTT bit cleared - FreeBSD" 342 " does not have licensing issues" 343 " requiring it.\n"); 344 } 345 346 /* 347 * If this CPU supports HTT or CMP then mention the 348 * number of physical/logical cores it contains. 349 */ 350 if (cpu_feature & CPUID_HTT) 351 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 352 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 && 353 (amd_feature2 & AMDID2_CMP)) 354 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 355 else if (strcmp(cpu_vendor, "GenuineIntel") == 0 && 356 (cpu_high >= 4)) { 357 cpuid_count(4, 0, regs); 358 cmp = ((regs[0] & 0xfc000000) >> 26) + 1; 359 } 360 if (cmp > 1) 361 printf("\n Cores per package: %d", cmp); 362 if ((htt / cmp) > 1) 363 printf("\n Logical CPUs per core: %d", 364 htt / cmp); 365 } 366 } 367 /* Avoid ugly blank lines: only print newline when we have to. */ 368 if (*cpu_vendor || cpu_id) 369 printf("\n"); 370 371 if (!bootverbose) 372 return; 373 374 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) 375 print_AMD_info(); 376 } 377 378 void 379 panicifcpuunsupported(void) 380 { 381 382 #ifndef HAMMER 383 #error "You need to specify a cpu type" 384 #endif 385 /* 386 * Now that we have told the user what they have, 387 * let them know if that machine type isn't configured. 388 */ 389 switch (cpu_class) { 390 case CPUCLASS_X86: 391 #ifndef HAMMER 392 case CPUCLASS_K8: 393 #endif 394 panic("CPU class not configured"); 395 default: 396 break; 397 } 398 } 399 400 401 /* 402 * Final stage of CPU identification. -- Should I check TI? 403 */ 404 void 405 identify_cpu(void) 406 { 407 u_int regs[4]; 408 409 do_cpuid(0, regs); 410 cpu_high = regs[0]; 411 ((u_int *)&cpu_vendor)[0] = regs[1]; 412 ((u_int *)&cpu_vendor)[1] = regs[3]; 413 ((u_int *)&cpu_vendor)[2] = regs[2]; 414 cpu_vendor[12] = '\0'; 415 416 do_cpuid(1, regs); 417 cpu_id = regs[0]; 418 cpu_procinfo = regs[1]; 419 cpu_feature = regs[3]; 420 cpu_feature2 = regs[2]; 421 422 if (strcmp(cpu_vendor, "GenuineIntel") == 0 || 423 strcmp(cpu_vendor, "AuthenticAMD") == 0) { 424 do_cpuid(0x80000000, regs); 425 cpu_exthigh = regs[0]; 426 } 427 if (cpu_exthigh >= 0x80000001) { 428 do_cpuid(0x80000001, regs); 429 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 430 amd_feature2 = regs[2]; 431 } 432 if (cpu_exthigh >= 0x80000008) { 433 do_cpuid(0x80000008, regs); 434 cpu_procinfo2 = regs[2]; 435 } 436 437 /* XXX */ 438 cpu = CPU_CLAWHAMMER; 439 } 440 441 static void 442 print_AMD_assoc(int i) 443 { 444 if (i == 255) 445 printf(", fully associative\n"); 446 else 447 printf(", %d-way associative\n", i); 448 } 449 450 static void 451 print_AMD_l2_assoc(int i) 452 { 453 switch (i & 0x0f) { 454 case 0: printf(", disabled/not present\n"); break; 455 case 1: printf(", direct mapped\n"); break; 456 case 2: printf(", 2-way associative\n"); break; 457 case 4: printf(", 4-way associative\n"); break; 458 case 6: printf(", 8-way associative\n"); break; 459 case 8: printf(", 16-way associative\n"); break; 460 case 15: printf(", fully associative\n"); break; 461 default: printf(", reserved configuration\n"); break; 462 } 463 } 464 465 static void 466 print_AMD_info(void) 467 { 468 u_int regs[4]; 469 470 if (cpu_exthigh < 0x80000005) 471 return; 472 473 do_cpuid(0x80000005, regs); 474 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 475 print_AMD_assoc(regs[0] >> 24); 476 477 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 478 print_AMD_assoc((regs[0] >> 8) & 0xff); 479 480 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 481 print_AMD_assoc(regs[1] >> 24); 482 483 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 484 print_AMD_assoc((regs[1] >> 8) & 0xff); 485 486 printf("L1 data cache: %d kbytes", regs[2] >> 24); 487 printf(", %d bytes/line", regs[2] & 0xff); 488 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 489 print_AMD_assoc((regs[2] >> 16) & 0xff); 490 491 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 492 printf(", %d bytes/line", regs[3] & 0xff); 493 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 494 print_AMD_assoc((regs[3] >> 16) & 0xff); 495 496 if (cpu_exthigh >= 0x80000006) { 497 do_cpuid(0x80000006, regs); 498 if ((regs[0] >> 16) != 0) { 499 printf("L2 2MB data TLB: %d entries", 500 (regs[0] >> 16) & 0xfff); 501 print_AMD_l2_assoc(regs[0] >> 28); 502 printf("L2 2MB instruction TLB: %d entries", 503 regs[0] & 0xfff); 504 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 505 } else { 506 printf("L2 2MB unified TLB: %d entries", 507 regs[0] & 0xfff); 508 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 509 } 510 if ((regs[1] >> 16) != 0) { 511 printf("L2 4KB data TLB: %d entries", 512 (regs[1] >> 16) & 0xfff); 513 print_AMD_l2_assoc(regs[1] >> 28); 514 515 printf("L2 4KB instruction TLB: %d entries", 516 (regs[1] >> 16) & 0xfff); 517 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 518 } else { 519 printf("L2 4KB unified TLB: %d entries", 520 (regs[1] >> 16) & 0xfff); 521 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 522 } 523 printf("L2 unified cache: %d kbytes", regs[2] >> 16); 524 printf(", %d bytes/line", regs[2] & 0xff); 525 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 526 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 527 } 528 }
Cache object: d54a6687eee37862d79eee82e87a8dd5
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]