The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/identcpu.c

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    1 /*-
    2  * Copyright (c) 1992 Terrence R. Lambert.
    3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
    4  * Copyright (c) 1997 KATO Takenori.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to Berkeley by
    8  * William Jolitz.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. All advertising materials mentioning features or use of this software
   19  *    must display the following acknowledgement:
   20  *      This product includes software developed by the University of
   21  *      California, Berkeley and its contributors.
   22  * 4. Neither the name of the University nor the names of its contributors
   23  *    may be used to endorse or promote products derived from this software
   24  *    without specific prior written permission.
   25  *
   26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   36  * SUCH DAMAGE.
   37  *
   38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
   39  */
   40 
   41 #include <sys/cdefs.h>
   42 __FBSDID("$FreeBSD$");
   43 
   44 #include "opt_cpu.h"
   45 
   46 #include <sys/param.h>
   47 #include <sys/bus.h>
   48 #include <sys/cpu.h>
   49 #include <sys/eventhandler.h>
   50 #include <sys/systm.h>
   51 #include <sys/kernel.h>
   52 #include <sys/sysctl.h>
   53 #include <sys/power.h>
   54 
   55 #include <machine/asmacros.h>
   56 #include <machine/clock.h>
   57 #include <machine/cputypes.h>
   58 #include <machine/frame.h>
   59 #include <machine/intr_machdep.h>
   60 #include <machine/segments.h>
   61 #include <machine/specialreg.h>
   62 #include <machine/md_var.h>
   63 
   64 #include <amd64/isa/icu.h>
   65 
   66 /* XXX - should be in header file: */
   67 void printcpuinfo(void);
   68 void identify_cpu(void);
   69 void earlysetcpuclass(void);
   70 void panicifcpuunsupported(void);
   71 
   72 static void print_AMD_info(void);
   73 static void print_AMD_assoc(int i);
   74 void setPQL2(int *const size, int *const ways);
   75 static void setPQL2_AMD(int *const size, int *const ways);
   76 
   77 int     cpu_class;
   78 char machine[] = "amd64";
   79 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 
   80     machine, 0, "Machine class");
   81 
   82 static char cpu_model[128];
   83 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 
   84     cpu_model, 0, "Machine model");
   85 
   86 static int hw_clockrate;
   87 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 
   88     &hw_clockrate, 0, "CPU instruction clock rate");
   89 
   90 static char cpu_brand[48];
   91 
   92 static struct {
   93         char    *cpu_name;
   94         int     cpu_class;
   95 } amd64_cpus[] = {
   96         { "Clawhammer",         CPUCLASS_K8 },          /* CPU_CLAWHAMMER */
   97         { "Sledgehammer",       CPUCLASS_K8 },          /* CPU_SLEDGEHAMMER */
   98 };
   99 
  100 extern int pq_l2size;
  101 extern int pq_l2nways;
  102 
  103 void
  104 printcpuinfo(void)
  105 {
  106         u_int regs[4], i;
  107         char *brand;
  108 
  109         cpu_class = amd64_cpus[cpu].cpu_class;
  110         printf("CPU: ");
  111         strncpy(cpu_model, amd64_cpus[cpu].cpu_name, sizeof (cpu_model));
  112 
  113         /* Check for extended CPUID information and a processor name. */
  114         if (cpu_exthigh >= 0x80000004) {
  115                 brand = cpu_brand;
  116                 for (i = 0x80000002; i < 0x80000005; i++) {
  117                         do_cpuid(i, regs);
  118                         memcpy(brand, regs, sizeof(regs));
  119                         brand += sizeof(regs);
  120                 }
  121         }
  122 
  123         if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
  124                 /* Please make up your mind folks! */
  125                 strcat(cpu_model, "EM64T");
  126         } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
  127                 /*
  128                  * Values taken from AMD Processor Recognition
  129                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
  130                  * (also describes ``Features'' encodings.
  131                  */
  132                 strcpy(cpu_model, "AMD ");
  133                 switch (cpu_id & 0xF00) {
  134                 case 0xf00:
  135                         strcat(cpu_model, "AMD64 Processor");
  136                         break;
  137                 default:
  138                         strcat(cpu_model, "Unknown");
  139                         break;
  140                 }
  141         }
  142 
  143         /*
  144          * Replace cpu_model with cpu_brand minus leading spaces if
  145          * we have one.
  146          */
  147         brand = cpu_brand;
  148         while (*brand == ' ')
  149                 ++brand;
  150         if (*brand != '\0')
  151                 strcpy(cpu_model, brand);
  152 
  153         printf("%s (", cpu_model);
  154         switch(cpu_class) {
  155         case CPUCLASS_K8:
  156                 hw_clockrate = (tsc_freq + 5000) / 1000000;
  157                 printf("%jd.%02d-MHz ",
  158                        (intmax_t)(tsc_freq + 4999) / 1000000,
  159                        (u_int)((tsc_freq + 4999) / 10000) % 100);
  160                 printf("K8");
  161                 break;
  162         default:
  163                 printf("Unknown");      /* will panic below... */
  164         }
  165         printf("-class CPU)\n");
  166         if(*cpu_vendor)
  167                 printf("  Origin = \"%s\"",cpu_vendor);
  168         if(cpu_id)
  169                 printf("  Id = 0x%x", cpu_id);
  170 
  171         if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
  172             strcmp(cpu_vendor, "AuthenticAMD") == 0) {
  173                 printf("  Stepping = %u", cpu_id & 0xf);
  174                 if (cpu_high > 0) {
  175                         u_int cmp = 1, htt = 1;
  176 
  177                         /*
  178                          * Here we should probably set up flags indicating
  179                          * whether or not various features are available.
  180                          * The interesting ones are probably VME, PSE, PAE,
  181                          * and PGE.  The code already assumes without bothering
  182                          * to check that all CPUs >= Pentium have a TSC and
  183                          * MSRs.
  184                          */
  185                         printf("\n  Features=0x%b", cpu_feature,
  186                         "\020"
  187                         "\001FPU"       /* Integral FPU */
  188                         "\002VME"       /* Extended VM86 mode support */
  189                         "\003DE"        /* Debugging Extensions (CR4.DE) */
  190                         "\004PSE"       /* 4MByte page tables */
  191                         "\005TSC"       /* Timestamp counter */
  192                         "\006MSR"       /* Machine specific registers */
  193                         "\007PAE"       /* Physical address extension */
  194                         "\010MCE"       /* Machine Check support */
  195                         "\011CX8"       /* CMPEXCH8 instruction */
  196                         "\012APIC"      /* SMP local APIC */
  197                         "\013oldMTRR"   /* Previous implementation of MTRR */
  198                         "\014SEP"       /* Fast System Call */
  199                         "\015MTRR"      /* Memory Type Range Registers */
  200                         "\016PGE"       /* PG_G (global bit) support */
  201                         "\017MCA"       /* Machine Check Architecture */
  202                         "\020CMOV"      /* CMOV instruction */
  203                         "\021PAT"       /* Page attributes table */
  204                         "\022PSE36"     /* 36 bit address space support */
  205                         "\023PN"        /* Processor Serial number */
  206                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
  207                         "\025<b20>"
  208                         "\026DTS"       /* Debug Trace Store */
  209                         "\027ACPI"      /* ACPI support */
  210                         "\030MMX"       /* MMX instructions */
  211                         "\031FXSR"      /* FXSAVE/FXRSTOR */
  212                         "\032SSE"       /* Streaming SIMD Extensions */
  213                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
  214                         "\034SS"        /* Self snoop */
  215                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
  216                         "\036TM"        /* Thermal Monitor clock slowdown */
  217                         "\037IA64"      /* CPU can execute IA64 instructions */
  218                         "\040PBE"       /* Pending Break Enable */
  219                         );
  220 
  221                         if (cpu_feature2 != 0) {
  222                                 printf("\n  Features2=0x%b", cpu_feature2,
  223                                 "\020"
  224                                 "\001SSE3"      /* SSE3 */
  225                                 "\002<b1>"
  226                                 "\003RSVD2"     /* "Reserved" bit 2 */
  227                                 "\004MON"       /* MONITOR/MWAIT Instructions */
  228                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
  229                                 "\006VMX"       /* Virtual Machine Extensions */
  230                                 "\007SMX"       /* Safer Mode Extensions */
  231                                 "\010EST"       /* Enhanced SpeedStep */
  232                                 "\011TM2"       /* Thermal Monitor 2 */
  233                                 "\012SSSE3"     /* SSSE3 */
  234                                 "\013CNXT-ID"   /* L1 context ID available */
  235                                 "\014<b11>"
  236                                 "\015<b12>"
  237                                 "\016CX16"      /* CMPXCHG16B Instruction */
  238                                 "\017xTPR"      /* Send Task Priority Messages*/
  239                                 "\020PDCM"      /* Perf/Debug Capability MSR */
  240                                 "\021<b16>"
  241                                 "\022<b17>"
  242                                 "\023DCA"       /* Direct Cache Access */
  243                                 "\024<b19>"
  244                                 "\025<b20>"
  245                                 "\026<b21>"
  246                                 "\027<b22>"
  247                                 "\030<b23>"
  248                                 "\031<b24>"
  249                                 "\032<b25>"
  250                                 "\033XSAVE"
  251                                 "\034OSXSAVE"
  252                                 "\035<b28>"
  253                                 "\036<b29>"
  254                                 "\037<b30>"
  255                                 "\040<b31>"
  256                                 );
  257                         }
  258 
  259                         /*
  260                          * AMD64 Architecture Programmer's Manual Volume 3:
  261                          * General-Purpose and System Instructions
  262                          * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
  263                          *
  264                          * IA-32 Intel Architecture Software Developer's Manual,
  265                          * Volume 2A: Instruction Set Reference, A-M
  266                          * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
  267                          */
  268                         if (amd_feature != 0) {
  269                                 printf("\n  AMD Features=0x%b", amd_feature,
  270                                 "\020"          /* in hex */
  271                                 "\001<s0>"      /* Same */
  272                                 "\002<s1>"      /* Same */
  273                                 "\003<s2>"      /* Same */
  274                                 "\004<s3>"      /* Same */
  275                                 "\005<s4>"      /* Same */
  276                                 "\006<s5>"      /* Same */
  277                                 "\007<s6>"      /* Same */
  278                                 "\010<s7>"      /* Same */
  279                                 "\011<s8>"      /* Same */
  280                                 "\012<s9>"      /* Same */
  281                                 "\013<b10>"     /* Undefined */
  282                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
  283                                 "\015<s12>"     /* Same */
  284                                 "\016<s13>"     /* Same */
  285                                 "\017<s14>"     /* Same */
  286                                 "\020<s15>"     /* Same */
  287                                 "\021<s16>"     /* Same */
  288                                 "\022<s17>"     /* Same */
  289                                 "\023<b18>"     /* Reserved, unknown */
  290                                 "\024MP"        /* Multiprocessor Capable */
  291                                 "\025NX"        /* Has EFER.NXE, NX */
  292                                 "\026<b21>"     /* Undefined */
  293                                 "\027MMX+"      /* AMD MMX Extensions */
  294                                 "\030<s23>"     /* Same */
  295                                 "\031<s24>"     /* Same */
  296                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
  297                                 "\033Page1GB"   /* 1-GB large page support */
  298                                 "\034RDTSCP"    /* RDTSCP */
  299                                 "\035<b28>"     /* Undefined */
  300                                 "\036LM"        /* 64 bit long mode */
  301                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
  302                                 "\0403DNow!"    /* AMD 3DNow! */
  303                                 );
  304                         }
  305 
  306                         if (amd_feature2 != 0) {
  307                                 printf("\n  AMD Features2=0x%b", amd_feature2,
  308                                 "\020"
  309                                 "\001LAHF"      /* LAHF/SAHF in long mode */
  310                                 "\002CMP"       /* CMP legacy */
  311                                 "\003SVM"       /* Secure Virtual Mode */
  312                                 "\004ExtAPIC"   /* Extended APIC register */
  313                                 "\005CR8"       /* CR8 in legacy mode */
  314                                 "\006<b5>"
  315                                 "\007<b6>"
  316                                 "\010<b7>"
  317                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
  318                                 "\012<b9>"
  319                                 "\013<b10>"
  320                                 "\014<b11>"
  321                                 "\015<b12>"
  322                                 "\016<b13>"
  323                                 "\017<b14>"
  324                                 "\020<b15>"
  325                                 "\021<b16>"
  326                                 "\022<b17>"
  327                                 "\023<b18>"
  328                                 "\024<b19>"
  329                                 "\025<b20>"
  330                                 "\026<b21>"
  331                                 "\027<b22>"
  332                                 "\030<b23>"
  333                                 "\031<b24>"
  334                                 "\032<b25>"
  335                                 "\033<b26>"
  336                                 "\034<b27>"
  337                                 "\035<b28>"
  338                                 "\036<b29>"
  339                                 "\037<b30>"
  340                                 "\040<b31>"
  341                                 );
  342                         }
  343 
  344                         if (cpu_feature & CPUID_HTT && strcmp(cpu_vendor,
  345                             "AuthenticAMD") == 0)
  346                                 cpu_feature &= ~CPUID_HTT;
  347 
  348                         /*
  349                          * If this CPU supports P-state invariant TSC then
  350                          * mention the capability.
  351                          */
  352                         if (!tsc_is_invariant &&
  353                             (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
  354                             ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 ||
  355                             AMD64_CPU_FAMILY(cpu_id) >= 0x10 ||
  356                             cpu_id == 0x60fb2))) {
  357                                 tsc_is_invariant = 1;
  358                                 printf("\n  TSC: P-state invariant");
  359                         }
  360 
  361                         /*
  362                          * If this CPU supports HTT or CMP then mention the
  363                          * number of physical/logical cores it contains.
  364                          */
  365                         if (cpu_feature & CPUID_HTT)
  366                                 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
  367                         if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
  368                             (amd_feature2 & AMDID2_CMP))
  369                                 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
  370                         else if (strcmp(cpu_vendor, "GenuineIntel") == 0 &&
  371                             (cpu_high >= 4)) {
  372                                 cpuid_count(4, 0, regs);
  373                                 if ((regs[0] & 0x1f) != 0)
  374                                         cmp = ((regs[0] >> 26) & 0x3f) + 1;
  375                         }
  376                         if (cmp > 1)
  377                                 printf("\n  Cores per package: %d", cmp);
  378                         if ((htt / cmp) > 1)
  379                                 printf("\n  Logical CPUs per core: %d",
  380                                     htt / cmp);
  381                 }
  382         }
  383         /* Avoid ugly blank lines: only print newline when we have to. */
  384         if (*cpu_vendor || cpu_id)
  385                 printf("\n");
  386 
  387         if (!bootverbose)
  388                 return;
  389 
  390         if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
  391                 print_AMD_info();
  392 }
  393 
  394 void
  395 panicifcpuunsupported(void)
  396 {
  397 
  398 #ifndef HAMMER
  399 #error "You need to specify a cpu type"
  400 #endif
  401         /*
  402          * Now that we have told the user what they have,
  403          * let them know if that machine type isn't configured.
  404          */
  405         switch (cpu_class) {
  406         case CPUCLASS_X86:
  407 #ifndef HAMMER
  408         case CPUCLASS_K8:
  409 #endif
  410                 panic("CPU class not configured");
  411         default:
  412                 break;
  413         }
  414 }
  415 
  416 
  417 /* Update TSC freq with the value indicated by the caller. */
  418 static void
  419 tsc_freq_changed(void *arg, const struct cf_level *level, int status)
  420 {
  421         /*
  422          * If there was an error during the transition or
  423          * TSC is P-state invariant, don't do anything.
  424          */
  425         if (status != 0 || tsc_is_invariant)
  426                 return;
  427 
  428         /* Total setting for this level gives the new frequency in MHz. */
  429         hw_clockrate = level->total_set.freq;
  430 }
  431 
  432 EVENTHANDLER_DEFINE(cpufreq_post_change, tsc_freq_changed, NULL,
  433     EVENTHANDLER_PRI_ANY);
  434 
  435 /*
  436  * Final stage of CPU identification. -- Should I check TI?
  437  */
  438 void
  439 identify_cpu(void)
  440 {
  441         u_int regs[4];
  442 
  443         do_cpuid(0, regs);
  444         cpu_high = regs[0];
  445         ((u_int *)&cpu_vendor)[0] = regs[1];
  446         ((u_int *)&cpu_vendor)[1] = regs[3];
  447         ((u_int *)&cpu_vendor)[2] = regs[2];
  448         cpu_vendor[12] = '\0';
  449 
  450         do_cpuid(1, regs);
  451         cpu_id = regs[0];
  452         cpu_procinfo = regs[1];
  453         cpu_feature = regs[3];
  454         cpu_feature2 = regs[2];
  455 
  456         if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
  457             strcmp(cpu_vendor, "AuthenticAMD") == 0) {
  458                 do_cpuid(0x80000000, regs);
  459                 cpu_exthigh = regs[0];
  460         }
  461         if (cpu_exthigh >= 0x80000001) {
  462                 do_cpuid(0x80000001, regs);
  463                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
  464                 amd_feature2 = regs[2];
  465         }
  466         if (cpu_exthigh >= 0x80000007) {
  467                 do_cpuid(0x80000007, regs);
  468                 amd_pminfo = regs[3];
  469         }
  470         if (cpu_exthigh >= 0x80000008) {
  471                 do_cpuid(0x80000008, regs);
  472                 cpu_procinfo2 = regs[2];
  473         }
  474 
  475         /* XXX */
  476         cpu = CPU_CLAWHAMMER;
  477 }
  478 
  479 static void
  480 print_AMD_assoc(int i)
  481 {
  482         if (i == 255)
  483                 printf(", fully associative\n");
  484         else
  485                 printf(", %d-way associative\n", i);
  486 }
  487 
  488 static void
  489 print_AMD_l2_assoc(int i)
  490 {
  491         switch (i & 0x0f) {
  492         case 0: printf(", disabled/not present\n"); break;
  493         case 1: printf(", direct mapped\n"); break;
  494         case 2: printf(", 2-way associative\n"); break;
  495         case 4: printf(", 4-way associative\n"); break;
  496         case 6: printf(", 8-way associative\n"); break;
  497         case 8: printf(", 16-way associative\n"); break;
  498         case 15: printf(", fully associative\n"); break;
  499         default: printf(", reserved configuration\n"); break;
  500         }
  501 }
  502 
  503 static void
  504 print_AMD_info(void)
  505 {
  506         u_int regs[4];
  507 
  508         if (cpu_exthigh < 0x80000005)
  509                 return;
  510 
  511         do_cpuid(0x80000005, regs);
  512         printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
  513         print_AMD_assoc(regs[0] >> 24);
  514 
  515         printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
  516         print_AMD_assoc((regs[0] >> 8) & 0xff);
  517 
  518         printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
  519         print_AMD_assoc(regs[1] >> 24);
  520 
  521         printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
  522         print_AMD_assoc((regs[1] >> 8) & 0xff);
  523 
  524         printf("L1 data cache: %d kbytes", regs[2] >> 24);
  525         printf(", %d bytes/line", regs[2] & 0xff);
  526         printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
  527         print_AMD_assoc((regs[2] >> 16) & 0xff);
  528 
  529         printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
  530         printf(", %d bytes/line", regs[3] & 0xff);
  531         printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
  532         print_AMD_assoc((regs[3] >> 16) & 0xff);
  533 
  534         if (cpu_exthigh >= 0x80000006) {
  535                 do_cpuid(0x80000006, regs);
  536                 if ((regs[0] >> 16) != 0) {
  537                         printf("L2 2MB data TLB: %d entries",
  538                             (regs[0] >> 16) & 0xfff);
  539                         print_AMD_l2_assoc(regs[0] >> 28);
  540                         printf("L2 2MB instruction TLB: %d entries",
  541                             regs[0] & 0xfff);
  542                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
  543                 } else {
  544                         printf("L2 2MB unified TLB: %d entries",
  545                             regs[0] & 0xfff);
  546                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
  547                 }
  548                 if ((regs[1] >> 16) != 0) {
  549                         printf("L2 4KB data TLB: %d entries",
  550                             (regs[1] >> 16) & 0xfff);
  551                         print_AMD_l2_assoc(regs[1] >> 28);
  552 
  553                         printf("L2 4KB instruction TLB: %d entries",
  554                             (regs[1] >> 16) & 0xfff);
  555                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
  556                 } else {
  557                         printf("L2 4KB unified TLB: %d entries",
  558                             (regs[1] >> 16) & 0xfff);
  559                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
  560                 }
  561                 printf("L2 unified cache: %d kbytes", regs[2] >> 16);
  562                 printf(", %d bytes/line", regs[2] & 0xff);
  563                 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
  564                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);     
  565         }
  566 }
  567 
  568 static void             
  569 setPQL2_AMD(int *const size, int *const ways)
  570 {
  571         if (cpu_exthigh >= 0x80000006) {
  572                 u_int regs[4];
  573 
  574                 do_cpuid(0x80000006, regs);
  575                 *size = regs[2] >> 16;
  576                 *ways = (regs[2] >> 12) & 0x0f;
  577                 switch (*ways) {
  578                 case 0:                         /* disabled/not present */
  579                 case 15:                        /* fully associative */
  580                 default: *ways = 1; break;      /* reserved configuration */
  581                 case 4: *ways = 4; break;
  582                 case 6: *ways = 8; break;
  583                 case 8: *ways = 16; break;
  584                 }
  585         }
  586 }
  587 
  588 void
  589 setPQL2(int *const size, int *const ways)
  590 {
  591         if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
  592                 setPQL2_AMD(size, ways);
  593 }

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