Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/identcpu.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD: releng/7.3/sys/amd64/amd64/identcpu.c 200742 2009-12-20 01:00:41Z avg $"); 43 44 #include "opt_cpu.h" 45 46 #include <sys/param.h> 47 #include <sys/bus.h> 48 #include <sys/cpu.h> 49 #include <sys/eventhandler.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/sysctl.h> 53 #include <sys/power.h> 54 55 #include <machine/asmacros.h> 56 #include <machine/clock.h> 57 #include <machine/cputypes.h> 58 #include <machine/frame.h> 59 #include <machine/intr_machdep.h> 60 #include <machine/segments.h> 61 #include <machine/specialreg.h> 62 #include <machine/md_var.h> 63 64 #include <amd64/isa/icu.h> 65 66 /* XXX - should be in header file: */ 67 void printcpuinfo(void); 68 void identify_cpu(void); 69 void earlysetcpuclass(void); 70 void panicifcpuunsupported(void); 71 72 static u_int find_cpu_vendor_id(void); 73 static void print_AMD_info(void); 74 static void print_AMD_assoc(int i); 75 static void print_via_padlock_info(void); 76 77 int cpu_class; 78 char machine[] = "amd64"; 79 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 80 machine, 0, "Machine class"); 81 82 static char cpu_model[128]; 83 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 84 cpu_model, 0, "Machine model"); 85 86 static int hw_clockrate; 87 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 88 &hw_clockrate, 0, "CPU instruction clock rate"); 89 90 static char cpu_brand[48]; 91 92 static struct { 93 char *cpu_name; 94 int cpu_class; 95 } amd64_cpus[] = { 96 { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */ 97 { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */ 98 }; 99 100 static struct { 101 char *vendor; 102 u_int vendor_id; 103 } cpu_vendors[] = { 104 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 105 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 106 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 107 }; 108 109 void 110 printcpuinfo(void) 111 { 112 u_int regs[4], i; 113 char *brand; 114 115 cpu_class = amd64_cpus[cpu].cpu_class; 116 printf("CPU: "); 117 strncpy(cpu_model, amd64_cpus[cpu].cpu_name, sizeof (cpu_model)); 118 119 /* Check for extended CPUID information and a processor name. */ 120 if (cpu_exthigh >= 0x80000004) { 121 brand = cpu_brand; 122 for (i = 0x80000002; i < 0x80000005; i++) { 123 do_cpuid(i, regs); 124 memcpy(brand, regs, sizeof(regs)); 125 brand += sizeof(regs); 126 } 127 } 128 129 switch (cpu_vendor_id) { 130 case CPU_VENDOR_INTEL: 131 /* Please make up your mind folks! */ 132 strcat(cpu_model, "EM64T"); 133 break; 134 case CPU_VENDOR_AMD: 135 /* 136 * Values taken from AMD Processor Recognition 137 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 138 * (also describes ``Features'' encodings. 139 */ 140 strcpy(cpu_model, "AMD "); 141 if ((cpu_id & 0xf00) == 0xf00) 142 strcat(cpu_model, "AMD64 Processor"); 143 else 144 strcat(cpu_model, "Unknown"); 145 break; 146 case CPU_VENDOR_CENTAUR: 147 strcpy(cpu_model, "VIA "); 148 if ((cpu_id & 0xff0) == 0x6f0) 149 strcat(cpu_model, "Nano Processor"); 150 else 151 strcat(cpu_model, "Unknown"); 152 break; 153 default: 154 strcat(cpu_model, "Unknown"); 155 break; 156 } 157 158 /* 159 * Replace cpu_model with cpu_brand minus leading spaces if 160 * we have one. 161 */ 162 brand = cpu_brand; 163 while (*brand == ' ') 164 ++brand; 165 if (*brand != '\0') 166 strcpy(cpu_model, brand); 167 168 printf("%s (", cpu_model); 169 switch(cpu_class) { 170 case CPUCLASS_K8: 171 hw_clockrate = (tsc_freq + 5000) / 1000000; 172 printf("%jd.%02d-MHz ", 173 (intmax_t)(tsc_freq + 4999) / 1000000, 174 (u_int)((tsc_freq + 4999) / 10000) % 100); 175 printf("K8"); 176 break; 177 default: 178 printf("Unknown"); /* will panic below... */ 179 } 180 printf("-class CPU)\n"); 181 if (*cpu_vendor) 182 printf(" Origin = \"%s\"", cpu_vendor); 183 if (cpu_id) 184 printf(" Id = 0x%x", cpu_id); 185 186 if (cpu_vendor_id == CPU_VENDOR_INTEL || 187 cpu_vendor_id == CPU_VENDOR_AMD || 188 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 189 printf(" Stepping = %u", cpu_id & 0xf); 190 if (cpu_high > 0) { 191 u_int cmp = 1, htt = 1; 192 193 /* 194 * Here we should probably set up flags indicating 195 * whether or not various features are available. 196 * The interesting ones are probably VME, PSE, PAE, 197 * and PGE. The code already assumes without bothering 198 * to check that all CPUs >= Pentium have a TSC and 199 * MSRs. 200 */ 201 printf("\n Features=0x%b", cpu_feature, 202 "\020" 203 "\001FPU" /* Integral FPU */ 204 "\002VME" /* Extended VM86 mode support */ 205 "\003DE" /* Debugging Extensions (CR4.DE) */ 206 "\004PSE" /* 4MByte page tables */ 207 "\005TSC" /* Timestamp counter */ 208 "\006MSR" /* Machine specific registers */ 209 "\007PAE" /* Physical address extension */ 210 "\010MCE" /* Machine Check support */ 211 "\011CX8" /* CMPEXCH8 instruction */ 212 "\012APIC" /* SMP local APIC */ 213 "\013oldMTRR" /* Previous implementation of MTRR */ 214 "\014SEP" /* Fast System Call */ 215 "\015MTRR" /* Memory Type Range Registers */ 216 "\016PGE" /* PG_G (global bit) support */ 217 "\017MCA" /* Machine Check Architecture */ 218 "\020CMOV" /* CMOV instruction */ 219 "\021PAT" /* Page attributes table */ 220 "\022PSE36" /* 36 bit address space support */ 221 "\023PN" /* Processor Serial number */ 222 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 223 "\025<b20>" 224 "\026DTS" /* Debug Trace Store */ 225 "\027ACPI" /* ACPI support */ 226 "\030MMX" /* MMX instructions */ 227 "\031FXSR" /* FXSAVE/FXRSTOR */ 228 "\032SSE" /* Streaming SIMD Extensions */ 229 "\033SSE2" /* Streaming SIMD Extensions #2 */ 230 "\034SS" /* Self snoop */ 231 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 232 "\036TM" /* Thermal Monitor clock slowdown */ 233 "\037IA64" /* CPU can execute IA64 instructions */ 234 "\040PBE" /* Pending Break Enable */ 235 ); 236 237 if (cpu_feature2 != 0) { 238 printf("\n Features2=0x%b", cpu_feature2, 239 "\020" 240 "\001SSE3" /* SSE3 */ 241 "\002<b1>" 242 "\003DTES64" /* 64-bit Debug Trace */ 243 "\004MON" /* MONITOR/MWAIT Instructions */ 244 "\005DS_CPL" /* CPL Qualified Debug Store */ 245 "\006VMX" /* Virtual Machine Extensions */ 246 "\007SMX" /* Safer Mode Extensions */ 247 "\010EST" /* Enhanced SpeedStep */ 248 "\011TM2" /* Thermal Monitor 2 */ 249 "\012SSSE3" /* SSSE3 */ 250 "\013CNXT-ID" /* L1 context ID available */ 251 "\014<b11>" 252 "\015<b12>" 253 "\016CX16" /* CMPXCHG16B Instruction */ 254 "\017xTPR" /* Send Task Priority Messages*/ 255 "\020PDCM" /* Perf/Debug Capability MSR */ 256 "\021<b16>" 257 "\022<b17>" 258 "\023DCA" /* Direct Cache Access */ 259 "\024SSE4.1" 260 "\025SSE4.2" 261 "\026x2APIC" /* xAPIC Extensions */ 262 "\027MOVBE" 263 "\030POPCNT" 264 "\031<b24>" 265 "\032<b25>" 266 "\033XSAVE" 267 "\034OSXSAVE" 268 "\035<b28>" 269 "\036<b29>" 270 "\037<b30>" 271 "\040<b31>" 272 ); 273 } 274 275 /* 276 * AMD64 Architecture Programmer's Manual Volume 3: 277 * General-Purpose and System Instructions 278 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf 279 * 280 * IA-32 Intel Architecture Software Developer's Manual, 281 * Volume 2A: Instruction Set Reference, A-M 282 * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf 283 */ 284 if (amd_feature != 0) { 285 printf("\n AMD Features=0x%b", amd_feature, 286 "\020" /* in hex */ 287 "\001<s0>" /* Same */ 288 "\002<s1>" /* Same */ 289 "\003<s2>" /* Same */ 290 "\004<s3>" /* Same */ 291 "\005<s4>" /* Same */ 292 "\006<s5>" /* Same */ 293 "\007<s6>" /* Same */ 294 "\010<s7>" /* Same */ 295 "\011<s8>" /* Same */ 296 "\012<s9>" /* Same */ 297 "\013<b10>" /* Undefined */ 298 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 299 "\015<s12>" /* Same */ 300 "\016<s13>" /* Same */ 301 "\017<s14>" /* Same */ 302 "\020<s15>" /* Same */ 303 "\021<s16>" /* Same */ 304 "\022<s17>" /* Same */ 305 "\023<b18>" /* Reserved, unknown */ 306 "\024MP" /* Multiprocessor Capable */ 307 "\025NX" /* Has EFER.NXE, NX */ 308 "\026<b21>" /* Undefined */ 309 "\027MMX+" /* AMD MMX Extensions */ 310 "\030<s23>" /* Same */ 311 "\031<s24>" /* Same */ 312 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 313 "\033Page1GB" /* 1-GB large page support */ 314 "\034RDTSCP" /* RDTSCP */ 315 "\035<b28>" /* Undefined */ 316 "\036LM" /* 64 bit long mode */ 317 "\0373DNow!+" /* AMD 3DNow! Extensions */ 318 "\0403DNow!" /* AMD 3DNow! */ 319 ); 320 } 321 322 if (amd_feature2 != 0) { 323 printf("\n AMD Features2=0x%b", amd_feature2, 324 "\020" 325 "\001LAHF" /* LAHF/SAHF in long mode */ 326 "\002CMP" /* CMP legacy */ 327 "\003SVM" /* Secure Virtual Mode */ 328 "\004ExtAPIC" /* Extended APIC register */ 329 "\005CR8" /* CR8 in legacy mode */ 330 "\006ABM" /* LZCNT instruction */ 331 "\007SSE4A" /* SSE4A */ 332 "\010MAS" /* Misaligned SSE mode */ 333 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 334 "\012OSVW" /* OS visible workaround */ 335 "\013IBS" /* Instruction based sampling */ 336 "\014SSE5" /* SSE5 */ 337 "\015SKINIT" /* SKINIT/STGI */ 338 "\016WDT" /* Watchdog timer */ 339 "\017<b14>" 340 "\020<b15>" 341 "\021<b16>" 342 "\022<b17>" 343 "\023<b18>" 344 "\024<b19>" 345 "\025<b20>" 346 "\026<b21>" 347 "\027<b22>" 348 "\030<b23>" 349 "\031<b24>" 350 "\032<b25>" 351 "\033<b26>" 352 "\034<b27>" 353 "\035<b28>" 354 "\036<b29>" 355 "\037<b30>" 356 "\040<b31>" 357 ); 358 } 359 360 if (cpu_vendor_id == CPU_VENDOR_CENTAUR) 361 print_via_padlock_info(); 362 363 if ((cpu_feature & CPUID_HTT) && 364 cpu_vendor_id == CPU_VENDOR_AMD) 365 cpu_feature &= ~CPUID_HTT; 366 367 /* 368 * If this CPU supports P-state invariant TSC then 369 * mention the capability. 370 */ 371 switch (cpu_vendor_id) { 372 case CPU_VENDOR_AMD: 373 if ((amd_pminfo & AMDPM_TSC_INVARIANT) || 374 CPUID_TO_FAMILY(cpu_id) >= 0x10 || 375 cpu_id == 0x60fb2) 376 tsc_is_invariant = 1; 377 break; 378 case CPU_VENDOR_INTEL: 379 if ((amd_pminfo & AMDPM_TSC_INVARIANT) || 380 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 381 CPUID_TO_MODEL(cpu_id) >= 0xe) || 382 (CPUID_TO_FAMILY(cpu_id) == 0xf && 383 CPUID_TO_MODEL(cpu_id) >= 0x3)) 384 tsc_is_invariant = 1; 385 break; 386 case CPU_VENDOR_CENTAUR: 387 if (CPUID_TO_FAMILY(cpu_id) == 0x6 && 388 CPUID_TO_MODEL(cpu_id) >= 0xf && 389 (rdmsr(0x1203) & 0x100000000ULL) == 0) 390 tsc_is_invariant = 1; 391 break; 392 } 393 if (tsc_is_invariant) 394 printf("\n TSC: P-state invariant"); 395 396 /* 397 * If this CPU supports HTT or CMP then mention the 398 * number of physical/logical cores it contains. 399 */ 400 if (cpu_feature & CPUID_HTT) 401 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 402 if (cpu_vendor_id == CPU_VENDOR_AMD && 403 (amd_feature2 & AMDID2_CMP)) 404 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 405 else if (cpu_vendor_id == CPU_VENDOR_INTEL && 406 (cpu_high >= 4)) { 407 cpuid_count(4, 0, regs); 408 if ((regs[0] & 0x1f) != 0) 409 cmp = ((regs[0] >> 26) & 0x3f) + 1; 410 } 411 if (cmp > 1) 412 printf("\n Cores per package: %d", cmp); 413 if ((htt / cmp) > 1) 414 printf("\n Logical CPUs per core: %d", 415 htt / cmp); 416 } 417 } 418 /* Avoid ugly blank lines: only print newline when we have to. */ 419 if (*cpu_vendor || cpu_id) 420 printf("\n"); 421 422 if (!bootverbose) 423 return; 424 425 if (cpu_vendor_id == CPU_VENDOR_AMD) 426 print_AMD_info(); 427 } 428 429 void 430 panicifcpuunsupported(void) 431 { 432 433 #ifndef HAMMER 434 #error "You need to specify a cpu type" 435 #endif 436 /* 437 * Now that we have told the user what they have, 438 * let them know if that machine type isn't configured. 439 */ 440 switch (cpu_class) { 441 case CPUCLASS_X86: 442 #ifndef HAMMER 443 case CPUCLASS_K8: 444 #endif 445 panic("CPU class not configured"); 446 default: 447 break; 448 } 449 } 450 451 452 /* Update TSC freq with the value indicated by the caller. */ 453 static void 454 tsc_freq_changed(void *arg, const struct cf_level *level, int status) 455 { 456 /* 457 * If there was an error during the transition or 458 * TSC is P-state invariant, don't do anything. 459 */ 460 if (status != 0 || tsc_is_invariant) 461 return; 462 463 /* Total setting for this level gives the new frequency in MHz. */ 464 hw_clockrate = level->total_set.freq; 465 } 466 467 EVENTHANDLER_DEFINE(cpufreq_post_change, tsc_freq_changed, NULL, 468 EVENTHANDLER_PRI_ANY); 469 470 /* 471 * Final stage of CPU identification. 472 */ 473 void 474 identify_cpu(void) 475 { 476 u_int regs[4]; 477 478 do_cpuid(0, regs); 479 cpu_high = regs[0]; 480 ((u_int *)&cpu_vendor)[0] = regs[1]; 481 ((u_int *)&cpu_vendor)[1] = regs[3]; 482 ((u_int *)&cpu_vendor)[2] = regs[2]; 483 cpu_vendor[12] = '\0'; 484 cpu_vendor_id = find_cpu_vendor_id(); 485 486 do_cpuid(1, regs); 487 cpu_id = regs[0]; 488 cpu_procinfo = regs[1]; 489 cpu_feature = regs[3]; 490 cpu_feature2 = regs[2]; 491 492 /* 493 * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID 494 * function number again if it is set from BIOS. It is necessary 495 * for probing correct CPU topology later. 496 * XXX This is only done on the BSP package. 497 */ 498 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4) { 499 uint64_t msr; 500 msr = rdmsr(MSR_IA32_MISC_ENABLE); 501 if ((msr & 0x400000ULL) != 0) { 502 wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL); 503 do_cpuid(0, regs); 504 cpu_high = regs[0]; 505 } 506 } 507 508 if (cpu_vendor_id == CPU_VENDOR_INTEL || 509 cpu_vendor_id == CPU_VENDOR_AMD || 510 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 511 do_cpuid(0x80000000, regs); 512 cpu_exthigh = regs[0]; 513 } 514 if (cpu_exthigh >= 0x80000001) { 515 do_cpuid(0x80000001, regs); 516 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 517 amd_feature2 = regs[2]; 518 } 519 if (cpu_exthigh >= 0x80000007) { 520 do_cpuid(0x80000007, regs); 521 amd_pminfo = regs[3]; 522 } 523 if (cpu_exthigh >= 0x80000008) { 524 do_cpuid(0x80000008, regs); 525 cpu_procinfo2 = regs[2]; 526 } 527 528 /* XXX */ 529 cpu = CPU_CLAWHAMMER; 530 } 531 532 static u_int 533 find_cpu_vendor_id(void) 534 { 535 int i; 536 537 for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++) 538 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 539 return (cpu_vendors[i].vendor_id); 540 return (0); 541 } 542 543 static void 544 print_AMD_assoc(int i) 545 { 546 if (i == 255) 547 printf(", fully associative\n"); 548 else 549 printf(", %d-way associative\n", i); 550 } 551 552 static void 553 print_AMD_l2_assoc(int i) 554 { 555 switch (i & 0x0f) { 556 case 0: printf(", disabled/not present\n"); break; 557 case 1: printf(", direct mapped\n"); break; 558 case 2: printf(", 2-way associative\n"); break; 559 case 4: printf(", 4-way associative\n"); break; 560 case 6: printf(", 8-way associative\n"); break; 561 case 8: printf(", 16-way associative\n"); break; 562 case 15: printf(", fully associative\n"); break; 563 default: printf(", reserved configuration\n"); break; 564 } 565 } 566 567 static void 568 print_AMD_info(void) 569 { 570 u_int regs[4]; 571 572 if (cpu_exthigh < 0x80000005) 573 return; 574 575 do_cpuid(0x80000005, regs); 576 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 577 print_AMD_assoc(regs[0] >> 24); 578 579 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 580 print_AMD_assoc((regs[0] >> 8) & 0xff); 581 582 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 583 print_AMD_assoc(regs[1] >> 24); 584 585 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 586 print_AMD_assoc((regs[1] >> 8) & 0xff); 587 588 printf("L1 data cache: %d kbytes", regs[2] >> 24); 589 printf(", %d bytes/line", regs[2] & 0xff); 590 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 591 print_AMD_assoc((regs[2] >> 16) & 0xff); 592 593 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 594 printf(", %d bytes/line", regs[3] & 0xff); 595 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 596 print_AMD_assoc((regs[3] >> 16) & 0xff); 597 598 if (cpu_exthigh >= 0x80000006) { 599 do_cpuid(0x80000006, regs); 600 if ((regs[0] >> 16) != 0) { 601 printf("L2 2MB data TLB: %d entries", 602 (regs[0] >> 16) & 0xfff); 603 print_AMD_l2_assoc(regs[0] >> 28); 604 printf("L2 2MB instruction TLB: %d entries", 605 regs[0] & 0xfff); 606 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 607 } else { 608 printf("L2 2MB unified TLB: %d entries", 609 regs[0] & 0xfff); 610 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 611 } 612 if ((regs[1] >> 16) != 0) { 613 printf("L2 4KB data TLB: %d entries", 614 (regs[1] >> 16) & 0xfff); 615 print_AMD_l2_assoc(regs[1] >> 28); 616 617 printf("L2 4KB instruction TLB: %d entries", 618 (regs[1] >> 16) & 0xfff); 619 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 620 } else { 621 printf("L2 4KB unified TLB: %d entries", 622 (regs[1] >> 16) & 0xfff); 623 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 624 } 625 printf("L2 unified cache: %d kbytes", regs[2] >> 16); 626 printf(", %d bytes/line", regs[2] & 0xff); 627 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 628 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 629 } 630 631 /* 632 * Opteron Rev E shows a bug as in very rare occasions a read memory 633 * barrier is not performed as expected if it is followed by a 634 * non-atomic read-modify-write instruction. 635 * As long as that bug pops up very rarely (intensive machine usage 636 * on other operating systems generally generates one unexplainable 637 * crash any 2 months) and as long as a model specific fix would be 638 * impratical at this stage, print out a warning string if the broken 639 * model and family are identified. 640 */ 641 if (CPUID_TO_FAMILY(cpu_id) == 0xf && 642 CPUID_TO_MODEL(cpu_id) >= 0x20 && CPUID_TO_MODEL(cpu_id) <= 0x3f) 643 printf("WARNING: This architecture revision has known SMP " 644 "hardware bugs which may cause random instability\n"); 645 } 646 647 static void 648 print_via_padlock_info(void) 649 { 650 u_int regs[4]; 651 652 /* Check for supported models. */ 653 switch (cpu_id & 0xff0) { 654 case 0x690: 655 if ((cpu_id & 0xf) < 3) 656 return; 657 case 0x6a0: 658 case 0x6d0: 659 case 0x6f0: 660 break; 661 default: 662 return; 663 } 664 665 do_cpuid(0xc0000000, regs); 666 if (regs[0] >= 0xc0000001) 667 do_cpuid(0xc0000001, regs); 668 else 669 return; 670 671 printf("\n VIA Padlock Features=0x%b", regs[3], 672 "\020" 673 "\003RNG" /* RNG */ 674 "\007AES" /* ACE */ 675 "\011AES-CTR" /* ACE2 */ 676 "\013SHA1,SHA256" /* PHE */ 677 "\015RSA" /* PMM */ 678 ); 679 }
Cache object: ad6628a9288b4b0fb37ec91b98978db8
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]