Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/amd64/amd64/identcpu.c
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1 /*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD: releng/8.1/sys/amd64/amd64/identcpu.c 207955 2010-05-12 09:34:10Z kib $"); 43 44 #include "opt_cpu.h" 45 46 #include <sys/param.h> 47 #include <sys/bus.h> 48 #include <sys/cpu.h> 49 #include <sys/eventhandler.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/sysctl.h> 53 #include <sys/power.h> 54 55 #include <machine/asmacros.h> 56 #include <machine/clock.h> 57 #include <machine/cputypes.h> 58 #include <machine/frame.h> 59 #include <machine/intr_machdep.h> 60 #include <machine/segments.h> 61 #include <machine/specialreg.h> 62 #include <machine/md_var.h> 63 64 #include <amd64/isa/icu.h> 65 66 /* XXX - should be in header file: */ 67 void printcpuinfo(void); 68 void identify_cpu(void); 69 void earlysetcpuclass(void); 70 void panicifcpuunsupported(void); 71 72 static u_int find_cpu_vendor_id(void); 73 static void print_AMD_info(void); 74 static void print_AMD_assoc(int i); 75 static void print_via_padlock_info(void); 76 77 int cpu_class; 78 char machine[] = "amd64"; 79 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 80 machine, 0, "Machine class"); 81 82 static char cpu_model[128]; 83 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 84 cpu_model, 0, "Machine model"); 85 86 static int hw_clockrate; 87 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 88 &hw_clockrate, 0, "CPU instruction clock rate"); 89 90 static char cpu_brand[48]; 91 92 static struct { 93 char *cpu_name; 94 int cpu_class; 95 } amd64_cpus[] = { 96 { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */ 97 { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */ 98 }; 99 100 static struct { 101 char *vendor; 102 u_int vendor_id; 103 } cpu_vendors[] = { 104 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 105 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 106 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 107 }; 108 109 110 void 111 printcpuinfo(void) 112 { 113 u_int regs[4], i; 114 char *brand; 115 116 cpu_class = amd64_cpus[cpu].cpu_class; 117 printf("CPU: "); 118 strncpy(cpu_model, amd64_cpus[cpu].cpu_name, sizeof (cpu_model)); 119 120 /* Check for extended CPUID information and a processor name. */ 121 if (cpu_exthigh >= 0x80000004) { 122 brand = cpu_brand; 123 for (i = 0x80000002; i < 0x80000005; i++) { 124 do_cpuid(i, regs); 125 memcpy(brand, regs, sizeof(regs)); 126 brand += sizeof(regs); 127 } 128 } 129 130 switch (cpu_vendor_id) { 131 case CPU_VENDOR_INTEL: 132 /* Please make up your mind folks! */ 133 strcat(cpu_model, "EM64T"); 134 break; 135 case CPU_VENDOR_AMD: 136 /* 137 * Values taken from AMD Processor Recognition 138 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 139 * (also describes ``Features'' encodings. 140 */ 141 strcpy(cpu_model, "AMD "); 142 if ((cpu_id & 0xf00) == 0xf00) 143 strcat(cpu_model, "AMD64 Processor"); 144 else 145 strcat(cpu_model, "Unknown"); 146 break; 147 case CPU_VENDOR_CENTAUR: 148 strcpy(cpu_model, "VIA "); 149 if ((cpu_id & 0xff0) == 0x6f0) 150 strcat(cpu_model, "Nano Processor"); 151 else 152 strcat(cpu_model, "Unknown"); 153 break; 154 default: 155 strcat(cpu_model, "Unknown"); 156 break; 157 } 158 159 /* 160 * Replace cpu_model with cpu_brand minus leading spaces if 161 * we have one. 162 */ 163 brand = cpu_brand; 164 while (*brand == ' ') 165 ++brand; 166 if (*brand != '\0') 167 strcpy(cpu_model, brand); 168 169 printf("%s (", cpu_model); 170 switch(cpu_class) { 171 case CPUCLASS_K8: 172 hw_clockrate = (tsc_freq + 5000) / 1000000; 173 printf("%jd.%02d-MHz ", 174 (intmax_t)(tsc_freq + 4999) / 1000000, 175 (u_int)((tsc_freq + 4999) / 10000) % 100); 176 printf("K8"); 177 break; 178 default: 179 printf("Unknown"); /* will panic below... */ 180 } 181 printf("-class CPU)\n"); 182 if (*cpu_vendor) 183 printf(" Origin = \"%s\"", cpu_vendor); 184 if (cpu_id) 185 printf(" Id = 0x%x", cpu_id); 186 187 if (cpu_vendor_id == CPU_VENDOR_INTEL || 188 cpu_vendor_id == CPU_VENDOR_AMD || 189 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 190 printf(" Family = %x", CPUID_TO_FAMILY(cpu_id)); 191 printf(" Model = %x", CPUID_TO_MODEL(cpu_id)); 192 printf(" Stepping = %u", cpu_id & CPUID_STEPPING); 193 if (cpu_high > 0) { 194 195 /* 196 * Here we should probably set up flags indicating 197 * whether or not various features are available. 198 * The interesting ones are probably VME, PSE, PAE, 199 * and PGE. The code already assumes without bothering 200 * to check that all CPUs >= Pentium have a TSC and 201 * MSRs. 202 */ 203 printf("\n Features=0x%b", cpu_feature, 204 "\020" 205 "\001FPU" /* Integral FPU */ 206 "\002VME" /* Extended VM86 mode support */ 207 "\003DE" /* Debugging Extensions (CR4.DE) */ 208 "\004PSE" /* 4MByte page tables */ 209 "\005TSC" /* Timestamp counter */ 210 "\006MSR" /* Machine specific registers */ 211 "\007PAE" /* Physical address extension */ 212 "\010MCE" /* Machine Check support */ 213 "\011CX8" /* CMPEXCH8 instruction */ 214 "\012APIC" /* SMP local APIC */ 215 "\013oldMTRR" /* Previous implementation of MTRR */ 216 "\014SEP" /* Fast System Call */ 217 "\015MTRR" /* Memory Type Range Registers */ 218 "\016PGE" /* PG_G (global bit) support */ 219 "\017MCA" /* Machine Check Architecture */ 220 "\020CMOV" /* CMOV instruction */ 221 "\021PAT" /* Page attributes table */ 222 "\022PSE36" /* 36 bit address space support */ 223 "\023PN" /* Processor Serial number */ 224 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 225 "\025<b20>" 226 "\026DTS" /* Debug Trace Store */ 227 "\027ACPI" /* ACPI support */ 228 "\030MMX" /* MMX instructions */ 229 "\031FXSR" /* FXSAVE/FXRSTOR */ 230 "\032SSE" /* Streaming SIMD Extensions */ 231 "\033SSE2" /* Streaming SIMD Extensions #2 */ 232 "\034SS" /* Self snoop */ 233 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 234 "\036TM" /* Thermal Monitor clock slowdown */ 235 "\037IA64" /* CPU can execute IA64 instructions */ 236 "\040PBE" /* Pending Break Enable */ 237 ); 238 239 if (cpu_feature2 != 0) { 240 printf("\n Features2=0x%b", cpu_feature2, 241 "\020" 242 "\001SSE3" /* SSE3 */ 243 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ 244 "\003DTES64" /* 64-bit Debug Trace */ 245 "\004MON" /* MONITOR/MWAIT Instructions */ 246 "\005DS_CPL" /* CPL Qualified Debug Store */ 247 "\006VMX" /* Virtual Machine Extensions */ 248 "\007SMX" /* Safer Mode Extensions */ 249 "\010EST" /* Enhanced SpeedStep */ 250 "\011TM2" /* Thermal Monitor 2 */ 251 "\012SSSE3" /* SSSE3 */ 252 "\013CNXT-ID" /* L1 context ID available */ 253 "\014<b11>" 254 "\015<b12>" 255 "\016CX16" /* CMPXCHG16B Instruction */ 256 "\017xTPR" /* Send Task Priority Messages*/ 257 "\020PDCM" /* Perf/Debug Capability MSR */ 258 "\021<b16>" 259 "\022<b17>" 260 "\023DCA" /* Direct Cache Access */ 261 "\024SSE4.1" 262 "\025SSE4.2" 263 "\026x2APIC" /* xAPIC Extensions */ 264 "\027MOVBE" 265 "\030POPCNT" 266 "\031<b24>" 267 "\032AESNI" /* AES Crypto*/ 268 "\033XSAVE" 269 "\034OSXSAVE" 270 "\035<b28>" 271 "\036<b29>" 272 "\037<b30>" 273 "\040<b31>" 274 ); 275 } 276 277 /* 278 * AMD64 Architecture Programmer's Manual Volume 3: 279 * General-Purpose and System Instructions 280 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf 281 * 282 * IA-32 Intel Architecture Software Developer's Manual, 283 * Volume 2A: Instruction Set Reference, A-M 284 * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf 285 */ 286 if (amd_feature != 0) { 287 printf("\n AMD Features=0x%b", amd_feature, 288 "\020" /* in hex */ 289 "\001<s0>" /* Same */ 290 "\002<s1>" /* Same */ 291 "\003<s2>" /* Same */ 292 "\004<s3>" /* Same */ 293 "\005<s4>" /* Same */ 294 "\006<s5>" /* Same */ 295 "\007<s6>" /* Same */ 296 "\010<s7>" /* Same */ 297 "\011<s8>" /* Same */ 298 "\012<s9>" /* Same */ 299 "\013<b10>" /* Undefined */ 300 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 301 "\015<s12>" /* Same */ 302 "\016<s13>" /* Same */ 303 "\017<s14>" /* Same */ 304 "\020<s15>" /* Same */ 305 "\021<s16>" /* Same */ 306 "\022<s17>" /* Same */ 307 "\023<b18>" /* Reserved, unknown */ 308 "\024MP" /* Multiprocessor Capable */ 309 "\025NX" /* Has EFER.NXE, NX */ 310 "\026<b21>" /* Undefined */ 311 "\027MMX+" /* AMD MMX Extensions */ 312 "\030<s23>" /* Same */ 313 "\031<s24>" /* Same */ 314 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 315 "\033Page1GB" /* 1-GB large page support */ 316 "\034RDTSCP" /* RDTSCP */ 317 "\035<b28>" /* Undefined */ 318 "\036LM" /* 64 bit long mode */ 319 "\0373DNow!+" /* AMD 3DNow! Extensions */ 320 "\0403DNow!" /* AMD 3DNow! */ 321 ); 322 } 323 324 if (amd_feature2 != 0) { 325 printf("\n AMD Features2=0x%b", amd_feature2, 326 "\020" 327 "\001LAHF" /* LAHF/SAHF in long mode */ 328 "\002CMP" /* CMP legacy */ 329 "\003SVM" /* Secure Virtual Mode */ 330 "\004ExtAPIC" /* Extended APIC register */ 331 "\005CR8" /* CR8 in legacy mode */ 332 "\006ABM" /* LZCNT instruction */ 333 "\007SSE4A" /* SSE4A */ 334 "\010MAS" /* Misaligned SSE mode */ 335 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 336 "\012OSVW" /* OS visible workaround */ 337 "\013IBS" /* Instruction based sampling */ 338 "\014SSE5" /* SSE5 */ 339 "\015SKINIT" /* SKINIT/STGI */ 340 "\016WDT" /* Watchdog timer */ 341 "\017<b14>" 342 "\020<b15>" 343 "\021<b16>" 344 "\022<b17>" 345 "\023<b18>" 346 "\024<b19>" 347 "\025<b20>" 348 "\026<b21>" 349 "\027<b22>" 350 "\030<b23>" 351 "\031<b24>" 352 "\032<b25>" 353 "\033<b26>" 354 "\034<b27>" 355 "\035<b28>" 356 "\036<b29>" 357 "\037<b30>" 358 "\040<b31>" 359 ); 360 } 361 362 if (cpu_vendor_id == CPU_VENDOR_CENTAUR) 363 print_via_padlock_info(); 364 365 if ((cpu_feature & CPUID_HTT) && 366 cpu_vendor_id == CPU_VENDOR_AMD) 367 cpu_feature &= ~CPUID_HTT; 368 369 /* 370 * If this CPU supports P-state invariant TSC then 371 * mention the capability. 372 */ 373 switch (cpu_vendor_id) { 374 case CPU_VENDOR_AMD: 375 if ((amd_pminfo & AMDPM_TSC_INVARIANT) || 376 CPUID_TO_FAMILY(cpu_id) >= 0x10 || 377 cpu_id == 0x60fb2) 378 tsc_is_invariant = 1; 379 break; 380 case CPU_VENDOR_INTEL: 381 if ((amd_pminfo & AMDPM_TSC_INVARIANT) || 382 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 383 CPUID_TO_MODEL(cpu_id) >= 0xe) || 384 (CPUID_TO_FAMILY(cpu_id) == 0xf && 385 CPUID_TO_MODEL(cpu_id) >= 0x3)) 386 tsc_is_invariant = 1; 387 break; 388 case CPU_VENDOR_CENTAUR: 389 if (CPUID_TO_FAMILY(cpu_id) == 0x6 && 390 CPUID_TO_MODEL(cpu_id) >= 0xf && 391 (rdmsr(0x1203) & 0x100000000ULL) == 0) 392 tsc_is_invariant = 1; 393 break; 394 } 395 if (tsc_is_invariant) 396 printf("\n TSC: P-state invariant"); 397 398 } 399 } 400 /* Avoid ugly blank lines: only print newline when we have to. */ 401 if (*cpu_vendor || cpu_id) 402 printf("\n"); 403 404 if (!bootverbose) 405 return; 406 407 if (cpu_vendor_id == CPU_VENDOR_AMD) 408 print_AMD_info(); 409 } 410 411 void 412 panicifcpuunsupported(void) 413 { 414 415 #ifndef HAMMER 416 #error "You need to specify a cpu type" 417 #endif 418 /* 419 * Now that we have told the user what they have, 420 * let them know if that machine type isn't configured. 421 */ 422 switch (cpu_class) { 423 case CPUCLASS_X86: 424 #ifndef HAMMER 425 case CPUCLASS_K8: 426 #endif 427 panic("CPU class not configured"); 428 default: 429 break; 430 } 431 } 432 433 434 /* Update TSC freq with the value indicated by the caller. */ 435 static void 436 tsc_freq_changed(void *arg, const struct cf_level *level, int status) 437 { 438 /* 439 * If there was an error during the transition or 440 * TSC is P-state invariant, don't do anything. 441 */ 442 if (status != 0 || tsc_is_invariant) 443 return; 444 445 /* Total setting for this level gives the new frequency in MHz. */ 446 hw_clockrate = level->total_set.freq; 447 } 448 449 EVENTHANDLER_DEFINE(cpufreq_post_change, tsc_freq_changed, NULL, 450 EVENTHANDLER_PRI_ANY); 451 452 /* 453 * Final stage of CPU identification. 454 */ 455 void 456 identify_cpu(void) 457 { 458 u_int regs[4]; 459 460 do_cpuid(0, regs); 461 cpu_high = regs[0]; 462 ((u_int *)&cpu_vendor)[0] = regs[1]; 463 ((u_int *)&cpu_vendor)[1] = regs[3]; 464 ((u_int *)&cpu_vendor)[2] = regs[2]; 465 cpu_vendor[12] = '\0'; 466 cpu_vendor_id = find_cpu_vendor_id(); 467 468 do_cpuid(1, regs); 469 cpu_id = regs[0]; 470 cpu_procinfo = regs[1]; 471 cpu_feature = regs[3]; 472 cpu_feature2 = regs[2]; 473 474 /* 475 * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID 476 * function number again if it is set from BIOS. It is necessary 477 * for probing correct CPU topology later. 478 * XXX This is only done on the BSP package. 479 */ 480 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4) { 481 uint64_t msr; 482 msr = rdmsr(MSR_IA32_MISC_ENABLE); 483 if ((msr & 0x400000ULL) != 0) { 484 wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL); 485 do_cpuid(0, regs); 486 cpu_high = regs[0]; 487 } 488 } 489 490 if (cpu_vendor_id == CPU_VENDOR_INTEL || 491 cpu_vendor_id == CPU_VENDOR_AMD || 492 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 493 do_cpuid(0x80000000, regs); 494 cpu_exthigh = regs[0]; 495 } 496 if (cpu_exthigh >= 0x80000001) { 497 do_cpuid(0x80000001, regs); 498 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 499 amd_feature2 = regs[2]; 500 } 501 if (cpu_exthigh >= 0x80000007) { 502 do_cpuid(0x80000007, regs); 503 amd_pminfo = regs[3]; 504 } 505 if (cpu_exthigh >= 0x80000008) { 506 do_cpuid(0x80000008, regs); 507 cpu_procinfo2 = regs[2]; 508 } 509 510 /* XXX */ 511 cpu = CPU_CLAWHAMMER; 512 } 513 514 static u_int 515 find_cpu_vendor_id(void) 516 { 517 int i; 518 519 for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++) 520 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 521 return (cpu_vendors[i].vendor_id); 522 return (0); 523 } 524 525 static void 526 print_AMD_assoc(int i) 527 { 528 if (i == 255) 529 printf(", fully associative\n"); 530 else 531 printf(", %d-way associative\n", i); 532 } 533 534 static void 535 print_AMD_l2_assoc(int i) 536 { 537 switch (i & 0x0f) { 538 case 0: printf(", disabled/not present\n"); break; 539 case 1: printf(", direct mapped\n"); break; 540 case 2: printf(", 2-way associative\n"); break; 541 case 4: printf(", 4-way associative\n"); break; 542 case 6: printf(", 8-way associative\n"); break; 543 case 8: printf(", 16-way associative\n"); break; 544 case 15: printf(", fully associative\n"); break; 545 default: printf(", reserved configuration\n"); break; 546 } 547 } 548 549 static void 550 print_AMD_info(void) 551 { 552 u_int regs[4]; 553 554 if (cpu_exthigh < 0x80000005) 555 return; 556 557 do_cpuid(0x80000005, regs); 558 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 559 print_AMD_assoc(regs[0] >> 24); 560 561 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 562 print_AMD_assoc((regs[0] >> 8) & 0xff); 563 564 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 565 print_AMD_assoc(regs[1] >> 24); 566 567 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 568 print_AMD_assoc((regs[1] >> 8) & 0xff); 569 570 printf("L1 data cache: %d kbytes", regs[2] >> 24); 571 printf(", %d bytes/line", regs[2] & 0xff); 572 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 573 print_AMD_assoc((regs[2] >> 16) & 0xff); 574 575 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 576 printf(", %d bytes/line", regs[3] & 0xff); 577 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 578 print_AMD_assoc((regs[3] >> 16) & 0xff); 579 580 if (cpu_exthigh >= 0x80000006) { 581 do_cpuid(0x80000006, regs); 582 if ((regs[0] >> 16) != 0) { 583 printf("L2 2MB data TLB: %d entries", 584 (regs[0] >> 16) & 0xfff); 585 print_AMD_l2_assoc(regs[0] >> 28); 586 printf("L2 2MB instruction TLB: %d entries", 587 regs[0] & 0xfff); 588 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 589 } else { 590 printf("L2 2MB unified TLB: %d entries", 591 regs[0] & 0xfff); 592 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 593 } 594 if ((regs[1] >> 16) != 0) { 595 printf("L2 4KB data TLB: %d entries", 596 (regs[1] >> 16) & 0xfff); 597 print_AMD_l2_assoc(regs[1] >> 28); 598 599 printf("L2 4KB instruction TLB: %d entries", 600 (regs[1] >> 16) & 0xfff); 601 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 602 } else { 603 printf("L2 4KB unified TLB: %d entries", 604 (regs[1] >> 16) & 0xfff); 605 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 606 } 607 printf("L2 unified cache: %d kbytes", regs[2] >> 16); 608 printf(", %d bytes/line", regs[2] & 0xff); 609 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 610 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 611 } 612 613 /* 614 * Opteron Rev E shows a bug as in very rare occasions a read memory 615 * barrier is not performed as expected if it is followed by a 616 * non-atomic read-modify-write instruction. 617 * As long as that bug pops up very rarely (intensive machine usage 618 * on other operating systems generally generates one unexplainable 619 * crash any 2 months) and as long as a model specific fix would be 620 * impratical at this stage, print out a warning string if the broken 621 * model and family are identified. 622 */ 623 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && 624 CPUID_TO_MODEL(cpu_id) <= 0x3f) 625 printf("WARNING: This architecture revision has known SMP " 626 "hardware bugs which may cause random instability\n"); 627 } 628 629 static void 630 print_via_padlock_info(void) 631 { 632 u_int regs[4]; 633 634 /* Check for supported models. */ 635 switch (cpu_id & 0xff0) { 636 case 0x690: 637 if ((cpu_id & 0xf) < 3) 638 return; 639 case 0x6a0: 640 case 0x6d0: 641 case 0x6f0: 642 break; 643 default: 644 return; 645 } 646 647 do_cpuid(0xc0000000, regs); 648 if (regs[0] >= 0xc0000001) 649 do_cpuid(0xc0000001, regs); 650 else 651 return; 652 653 printf("\n VIA Padlock Features=0x%b", regs[3], 654 "\020" 655 "\003RNG" /* RNG */ 656 "\007AES" /* ACE */ 657 "\011AES-CTR" /* ACE2 */ 658 "\013SHA1,SHA256" /* PHE */ 659 "\015RSA" /* PMM */ 660 ); 661 }
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