Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/amd64/amd64/identcpu.c
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1 /*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD: releng/8.2/sys/amd64/amd64/identcpu.c 213715 2010-10-12 09:10:24Z kib $"); 43 44 #include "opt_cpu.h" 45 46 #include <sys/param.h> 47 #include <sys/bus.h> 48 #include <sys/cpu.h> 49 #include <sys/eventhandler.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/sysctl.h> 53 #include <sys/power.h> 54 55 #include <machine/asmacros.h> 56 #include <machine/clock.h> 57 #include <machine/cputypes.h> 58 #include <machine/frame.h> 59 #include <machine/intr_machdep.h> 60 #include <machine/segments.h> 61 #include <machine/specialreg.h> 62 #include <machine/md_var.h> 63 64 #include <amd64/isa/icu.h> 65 66 /* XXX - should be in header file: */ 67 void printcpuinfo(void); 68 void identify_cpu(void); 69 void earlysetcpuclass(void); 70 void panicifcpuunsupported(void); 71 72 static u_int find_cpu_vendor_id(void); 73 static void print_AMD_info(void); 74 static void print_AMD_assoc(int i); 75 static void print_via_padlock_info(void); 76 77 int cpu_class; 78 char machine[] = "amd64"; 79 80 #ifdef SCTL_MASK32 81 extern int adaptive_machine_arch; 82 #endif 83 84 static int 85 sysctl_hw_machine(SYSCTL_HANDLER_ARGS) 86 { 87 #ifdef SCTL_MASK32 88 static const char machine32[] = "i386"; 89 #endif 90 int error; 91 92 #ifdef SCTL_MASK32 93 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) 94 error = SYSCTL_OUT(req, machine32, sizeof(machine32)); 95 else 96 #endif 97 error = SYSCTL_OUT(req, machine, sizeof(machine)); 98 return (error); 99 100 } 101 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD, 102 NULL, 0, sysctl_hw_machine, "A", "Machine class"); 103 104 static char cpu_model[128]; 105 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 106 cpu_model, 0, "Machine model"); 107 108 static int hw_clockrate; 109 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 110 &hw_clockrate, 0, "CPU instruction clock rate"); 111 112 static char cpu_brand[48]; 113 114 static struct { 115 char *cpu_name; 116 int cpu_class; 117 } amd64_cpus[] = { 118 { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */ 119 { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */ 120 }; 121 122 static struct { 123 char *vendor; 124 u_int vendor_id; 125 } cpu_vendors[] = { 126 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 127 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 128 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 129 }; 130 131 132 void 133 printcpuinfo(void) 134 { 135 u_int regs[4], i; 136 char *brand; 137 138 cpu_class = amd64_cpus[cpu].cpu_class; 139 printf("CPU: "); 140 strncpy(cpu_model, amd64_cpus[cpu].cpu_name, sizeof (cpu_model)); 141 142 /* Check for extended CPUID information and a processor name. */ 143 if (cpu_exthigh >= 0x80000004) { 144 brand = cpu_brand; 145 for (i = 0x80000002; i < 0x80000005; i++) { 146 do_cpuid(i, regs); 147 memcpy(brand, regs, sizeof(regs)); 148 brand += sizeof(regs); 149 } 150 } 151 152 switch (cpu_vendor_id) { 153 case CPU_VENDOR_INTEL: 154 /* Please make up your mind folks! */ 155 strcat(cpu_model, "EM64T"); 156 break; 157 case CPU_VENDOR_AMD: 158 /* 159 * Values taken from AMD Processor Recognition 160 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 161 * (also describes ``Features'' encodings. 162 */ 163 strcpy(cpu_model, "AMD "); 164 if ((cpu_id & 0xf00) == 0xf00) 165 strcat(cpu_model, "AMD64 Processor"); 166 else 167 strcat(cpu_model, "Unknown"); 168 break; 169 case CPU_VENDOR_CENTAUR: 170 strcpy(cpu_model, "VIA "); 171 if ((cpu_id & 0xff0) == 0x6f0) 172 strcat(cpu_model, "Nano Processor"); 173 else 174 strcat(cpu_model, "Unknown"); 175 break; 176 default: 177 strcat(cpu_model, "Unknown"); 178 break; 179 } 180 181 /* 182 * Replace cpu_model with cpu_brand minus leading spaces if 183 * we have one. 184 */ 185 brand = cpu_brand; 186 while (*brand == ' ') 187 ++brand; 188 if (*brand != '\0') 189 strcpy(cpu_model, brand); 190 191 printf("%s (", cpu_model); 192 switch(cpu_class) { 193 case CPUCLASS_K8: 194 hw_clockrate = (tsc_freq + 5000) / 1000000; 195 printf("%jd.%02d-MHz ", 196 (intmax_t)(tsc_freq + 4999) / 1000000, 197 (u_int)((tsc_freq + 4999) / 10000) % 100); 198 printf("K8"); 199 break; 200 default: 201 printf("Unknown"); /* will panic below... */ 202 } 203 printf("-class CPU)\n"); 204 if (*cpu_vendor) 205 printf(" Origin = \"%s\"", cpu_vendor); 206 if (cpu_id) 207 printf(" Id = 0x%x", cpu_id); 208 209 if (cpu_vendor_id == CPU_VENDOR_INTEL || 210 cpu_vendor_id == CPU_VENDOR_AMD || 211 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 212 printf(" Family = %x", CPUID_TO_FAMILY(cpu_id)); 213 printf(" Model = %x", CPUID_TO_MODEL(cpu_id)); 214 printf(" Stepping = %u", cpu_id & CPUID_STEPPING); 215 if (cpu_high > 0) { 216 217 /* 218 * Here we should probably set up flags indicating 219 * whether or not various features are available. 220 * The interesting ones are probably VME, PSE, PAE, 221 * and PGE. The code already assumes without bothering 222 * to check that all CPUs >= Pentium have a TSC and 223 * MSRs. 224 */ 225 printf("\n Features=0x%b", cpu_feature, 226 "\020" 227 "\001FPU" /* Integral FPU */ 228 "\002VME" /* Extended VM86 mode support */ 229 "\003DE" /* Debugging Extensions (CR4.DE) */ 230 "\004PSE" /* 4MByte page tables */ 231 "\005TSC" /* Timestamp counter */ 232 "\006MSR" /* Machine specific registers */ 233 "\007PAE" /* Physical address extension */ 234 "\010MCE" /* Machine Check support */ 235 "\011CX8" /* CMPEXCH8 instruction */ 236 "\012APIC" /* SMP local APIC */ 237 "\013oldMTRR" /* Previous implementation of MTRR */ 238 "\014SEP" /* Fast System Call */ 239 "\015MTRR" /* Memory Type Range Registers */ 240 "\016PGE" /* PG_G (global bit) support */ 241 "\017MCA" /* Machine Check Architecture */ 242 "\020CMOV" /* CMOV instruction */ 243 "\021PAT" /* Page attributes table */ 244 "\022PSE36" /* 36 bit address space support */ 245 "\023PN" /* Processor Serial number */ 246 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 247 "\025<b20>" 248 "\026DTS" /* Debug Trace Store */ 249 "\027ACPI" /* ACPI support */ 250 "\030MMX" /* MMX instructions */ 251 "\031FXSR" /* FXSAVE/FXRSTOR */ 252 "\032SSE" /* Streaming SIMD Extensions */ 253 "\033SSE2" /* Streaming SIMD Extensions #2 */ 254 "\034SS" /* Self snoop */ 255 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 256 "\036TM" /* Thermal Monitor clock slowdown */ 257 "\037IA64" /* CPU can execute IA64 instructions */ 258 "\040PBE" /* Pending Break Enable */ 259 ); 260 261 if (cpu_feature2 != 0) { 262 printf("\n Features2=0x%b", cpu_feature2, 263 "\020" 264 "\001SSE3" /* SSE3 */ 265 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ 266 "\003DTES64" /* 64-bit Debug Trace */ 267 "\004MON" /* MONITOR/MWAIT Instructions */ 268 "\005DS_CPL" /* CPL Qualified Debug Store */ 269 "\006VMX" /* Virtual Machine Extensions */ 270 "\007SMX" /* Safer Mode Extensions */ 271 "\010EST" /* Enhanced SpeedStep */ 272 "\011TM2" /* Thermal Monitor 2 */ 273 "\012SSSE3" /* SSSE3 */ 274 "\013CNXT-ID" /* L1 context ID available */ 275 "\014<b11>" 276 "\015<b12>" 277 "\016CX16" /* CMPXCHG16B Instruction */ 278 "\017xTPR" /* Send Task Priority Messages*/ 279 "\020PDCM" /* Perf/Debug Capability MSR */ 280 "\021<b16>" 281 "\022PCID" /* Process-context Identifiers */ 282 "\023DCA" /* Direct Cache Access */ 283 "\024SSE4.1" 284 "\025SSE4.2" 285 "\026x2APIC" /* xAPIC Extensions */ 286 "\027MOVBE" 287 "\030POPCNT" 288 "\031<b24>" 289 "\032AESNI" /* AES Crypto*/ 290 "\033XSAVE" 291 "\034OSXSAVE" 292 "\035<b28>" 293 "\036<b29>" 294 "\037<b30>" 295 "\040<b31>" 296 ); 297 } 298 299 /* 300 * AMD64 Architecture Programmer's Manual Volume 3: 301 * General-Purpose and System Instructions 302 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf 303 * 304 * IA-32 Intel Architecture Software Developer's Manual, 305 * Volume 2A: Instruction Set Reference, A-M 306 * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf 307 */ 308 if (amd_feature != 0) { 309 printf("\n AMD Features=0x%b", amd_feature, 310 "\020" /* in hex */ 311 "\001<s0>" /* Same */ 312 "\002<s1>" /* Same */ 313 "\003<s2>" /* Same */ 314 "\004<s3>" /* Same */ 315 "\005<s4>" /* Same */ 316 "\006<s5>" /* Same */ 317 "\007<s6>" /* Same */ 318 "\010<s7>" /* Same */ 319 "\011<s8>" /* Same */ 320 "\012<s9>" /* Same */ 321 "\013<b10>" /* Undefined */ 322 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 323 "\015<s12>" /* Same */ 324 "\016<s13>" /* Same */ 325 "\017<s14>" /* Same */ 326 "\020<s15>" /* Same */ 327 "\021<s16>" /* Same */ 328 "\022<s17>" /* Same */ 329 "\023<b18>" /* Reserved, unknown */ 330 "\024MP" /* Multiprocessor Capable */ 331 "\025NX" /* Has EFER.NXE, NX */ 332 "\026<b21>" /* Undefined */ 333 "\027MMX+" /* AMD MMX Extensions */ 334 "\030<s23>" /* Same */ 335 "\031<s24>" /* Same */ 336 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 337 "\033Page1GB" /* 1-GB large page support */ 338 "\034RDTSCP" /* RDTSCP */ 339 "\035<b28>" /* Undefined */ 340 "\036LM" /* 64 bit long mode */ 341 "\0373DNow!+" /* AMD 3DNow! Extensions */ 342 "\0403DNow!" /* AMD 3DNow! */ 343 ); 344 } 345 346 if (amd_feature2 != 0) { 347 printf("\n AMD Features2=0x%b", amd_feature2, 348 "\020" 349 "\001LAHF" /* LAHF/SAHF in long mode */ 350 "\002CMP" /* CMP legacy */ 351 "\003SVM" /* Secure Virtual Mode */ 352 "\004ExtAPIC" /* Extended APIC register */ 353 "\005CR8" /* CR8 in legacy mode */ 354 "\006ABM" /* LZCNT instruction */ 355 "\007SSE4A" /* SSE4A */ 356 "\010MAS" /* Misaligned SSE mode */ 357 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 358 "\012OSVW" /* OS visible workaround */ 359 "\013IBS" /* Instruction based sampling */ 360 "\014SSE5" /* SSE5 */ 361 "\015SKINIT" /* SKINIT/STGI */ 362 "\016WDT" /* Watchdog timer */ 363 "\017<b14>" 364 "\020<b15>" 365 "\021<b16>" 366 "\022<b17>" 367 "\023<b18>" 368 "\024<b19>" 369 "\025<b20>" 370 "\026<b21>" 371 "\027<b22>" 372 "\030<b23>" 373 "\031<b24>" 374 "\032<b25>" 375 "\033<b26>" 376 "\034<b27>" 377 "\035<b28>" 378 "\036<b29>" 379 "\037<b30>" 380 "\040<b31>" 381 ); 382 } 383 384 if (cpu_vendor_id == CPU_VENDOR_CENTAUR) 385 print_via_padlock_info(); 386 387 if ((cpu_feature & CPUID_HTT) && 388 cpu_vendor_id == CPU_VENDOR_AMD) 389 cpu_feature &= ~CPUID_HTT; 390 391 /* 392 * If this CPU supports P-state invariant TSC then 393 * mention the capability. 394 */ 395 switch (cpu_vendor_id) { 396 case CPU_VENDOR_AMD: 397 if ((amd_pminfo & AMDPM_TSC_INVARIANT) || 398 CPUID_TO_FAMILY(cpu_id) >= 0x10 || 399 cpu_id == 0x60fb2) 400 tsc_is_invariant = 1; 401 break; 402 case CPU_VENDOR_INTEL: 403 if ((amd_pminfo & AMDPM_TSC_INVARIANT) || 404 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 405 CPUID_TO_MODEL(cpu_id) >= 0xe) || 406 (CPUID_TO_FAMILY(cpu_id) == 0xf && 407 CPUID_TO_MODEL(cpu_id) >= 0x3)) 408 tsc_is_invariant = 1; 409 break; 410 case CPU_VENDOR_CENTAUR: 411 if (CPUID_TO_FAMILY(cpu_id) == 0x6 && 412 CPUID_TO_MODEL(cpu_id) >= 0xf && 413 (rdmsr(0x1203) & 0x100000000ULL) == 0) 414 tsc_is_invariant = 1; 415 break; 416 } 417 if (tsc_is_invariant) 418 printf("\n TSC: P-state invariant"); 419 420 } 421 } 422 /* Avoid ugly blank lines: only print newline when we have to. */ 423 if (*cpu_vendor || cpu_id) 424 printf("\n"); 425 426 if (!bootverbose) 427 return; 428 429 if (cpu_vendor_id == CPU_VENDOR_AMD) 430 print_AMD_info(); 431 } 432 433 void 434 panicifcpuunsupported(void) 435 { 436 437 #ifndef HAMMER 438 #error "You need to specify a cpu type" 439 #endif 440 /* 441 * Now that we have told the user what they have, 442 * let them know if that machine type isn't configured. 443 */ 444 switch (cpu_class) { 445 case CPUCLASS_X86: 446 #ifndef HAMMER 447 case CPUCLASS_K8: 448 #endif 449 panic("CPU class not configured"); 450 default: 451 break; 452 } 453 } 454 455 456 /* Update TSC freq with the value indicated by the caller. */ 457 static void 458 tsc_freq_changed(void *arg, const struct cf_level *level, int status) 459 { 460 /* 461 * If there was an error during the transition or 462 * TSC is P-state invariant, don't do anything. 463 */ 464 if (status != 0 || tsc_is_invariant) 465 return; 466 467 /* Total setting for this level gives the new frequency in MHz. */ 468 hw_clockrate = level->total_set.freq; 469 } 470 471 EVENTHANDLER_DEFINE(cpufreq_post_change, tsc_freq_changed, NULL, 472 EVENTHANDLER_PRI_ANY); 473 474 /* 475 * Final stage of CPU identification. 476 */ 477 void 478 identify_cpu(void) 479 { 480 u_int regs[4]; 481 482 do_cpuid(0, regs); 483 cpu_high = regs[0]; 484 ((u_int *)&cpu_vendor)[0] = regs[1]; 485 ((u_int *)&cpu_vendor)[1] = regs[3]; 486 ((u_int *)&cpu_vendor)[2] = regs[2]; 487 cpu_vendor[12] = '\0'; 488 cpu_vendor_id = find_cpu_vendor_id(); 489 490 do_cpuid(1, regs); 491 cpu_id = regs[0]; 492 cpu_procinfo = regs[1]; 493 cpu_feature = regs[3]; 494 cpu_feature2 = regs[2]; 495 496 /* 497 * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID 498 * function number again if it is set from BIOS. It is necessary 499 * for probing correct CPU topology later. 500 * XXX This is only done on the BSP package. 501 */ 502 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4) { 503 uint64_t msr; 504 msr = rdmsr(MSR_IA32_MISC_ENABLE); 505 if ((msr & 0x400000ULL) != 0) { 506 wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL); 507 do_cpuid(0, regs); 508 cpu_high = regs[0]; 509 } 510 } 511 512 if (cpu_vendor_id == CPU_VENDOR_INTEL || 513 cpu_vendor_id == CPU_VENDOR_AMD || 514 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 515 do_cpuid(0x80000000, regs); 516 cpu_exthigh = regs[0]; 517 } 518 if (cpu_exthigh >= 0x80000001) { 519 do_cpuid(0x80000001, regs); 520 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 521 amd_feature2 = regs[2]; 522 } 523 if (cpu_exthigh >= 0x80000007) { 524 do_cpuid(0x80000007, regs); 525 amd_pminfo = regs[3]; 526 } 527 if (cpu_exthigh >= 0x80000008) { 528 do_cpuid(0x80000008, regs); 529 cpu_procinfo2 = regs[2]; 530 } 531 532 /* XXX */ 533 cpu = CPU_CLAWHAMMER; 534 } 535 536 static u_int 537 find_cpu_vendor_id(void) 538 { 539 int i; 540 541 for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++) 542 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 543 return (cpu_vendors[i].vendor_id); 544 return (0); 545 } 546 547 static void 548 print_AMD_assoc(int i) 549 { 550 if (i == 255) 551 printf(", fully associative\n"); 552 else 553 printf(", %d-way associative\n", i); 554 } 555 556 static void 557 print_AMD_l2_assoc(int i) 558 { 559 switch (i & 0x0f) { 560 case 0: printf(", disabled/not present\n"); break; 561 case 1: printf(", direct mapped\n"); break; 562 case 2: printf(", 2-way associative\n"); break; 563 case 4: printf(", 4-way associative\n"); break; 564 case 6: printf(", 8-way associative\n"); break; 565 case 8: printf(", 16-way associative\n"); break; 566 case 15: printf(", fully associative\n"); break; 567 default: printf(", reserved configuration\n"); break; 568 } 569 } 570 571 static void 572 print_AMD_info(void) 573 { 574 u_int regs[4]; 575 576 if (cpu_exthigh < 0x80000005) 577 return; 578 579 do_cpuid(0x80000005, regs); 580 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 581 print_AMD_assoc(regs[0] >> 24); 582 583 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 584 print_AMD_assoc((regs[0] >> 8) & 0xff); 585 586 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 587 print_AMD_assoc(regs[1] >> 24); 588 589 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 590 print_AMD_assoc((regs[1] >> 8) & 0xff); 591 592 printf("L1 data cache: %d kbytes", regs[2] >> 24); 593 printf(", %d bytes/line", regs[2] & 0xff); 594 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 595 print_AMD_assoc((regs[2] >> 16) & 0xff); 596 597 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 598 printf(", %d bytes/line", regs[3] & 0xff); 599 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 600 print_AMD_assoc((regs[3] >> 16) & 0xff); 601 602 if (cpu_exthigh >= 0x80000006) { 603 do_cpuid(0x80000006, regs); 604 if ((regs[0] >> 16) != 0) { 605 printf("L2 2MB data TLB: %d entries", 606 (regs[0] >> 16) & 0xfff); 607 print_AMD_l2_assoc(regs[0] >> 28); 608 printf("L2 2MB instruction TLB: %d entries", 609 regs[0] & 0xfff); 610 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 611 } else { 612 printf("L2 2MB unified TLB: %d entries", 613 regs[0] & 0xfff); 614 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 615 } 616 if ((regs[1] >> 16) != 0) { 617 printf("L2 4KB data TLB: %d entries", 618 (regs[1] >> 16) & 0xfff); 619 print_AMD_l2_assoc(regs[1] >> 28); 620 621 printf("L2 4KB instruction TLB: %d entries", 622 (regs[1] >> 16) & 0xfff); 623 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 624 } else { 625 printf("L2 4KB unified TLB: %d entries", 626 (regs[1] >> 16) & 0xfff); 627 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 628 } 629 printf("L2 unified cache: %d kbytes", regs[2] >> 16); 630 printf(", %d bytes/line", regs[2] & 0xff); 631 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 632 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 633 } 634 635 /* 636 * Opteron Rev E shows a bug as in very rare occasions a read memory 637 * barrier is not performed as expected if it is followed by a 638 * non-atomic read-modify-write instruction. 639 * As long as that bug pops up very rarely (intensive machine usage 640 * on other operating systems generally generates one unexplainable 641 * crash any 2 months) and as long as a model specific fix would be 642 * impratical at this stage, print out a warning string if the broken 643 * model and family are identified. 644 */ 645 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && 646 CPUID_TO_MODEL(cpu_id) <= 0x3f) 647 printf("WARNING: This architecture revision has known SMP " 648 "hardware bugs which may cause random instability\n"); 649 } 650 651 static void 652 print_via_padlock_info(void) 653 { 654 u_int regs[4]; 655 656 /* Check for supported models. */ 657 switch (cpu_id & 0xff0) { 658 case 0x690: 659 if ((cpu_id & 0xf) < 3) 660 return; 661 case 0x6a0: 662 case 0x6d0: 663 case 0x6f0: 664 break; 665 default: 666 return; 667 } 668 669 do_cpuid(0xc0000000, regs); 670 if (regs[0] >= 0xc0000001) 671 do_cpuid(0xc0000001, regs); 672 else 673 return; 674 675 printf("\n VIA Padlock Features=0x%b", regs[3], 676 "\020" 677 "\003RNG" /* RNG */ 678 "\007AES" /* ACE */ 679 "\011AES-CTR" /* ACE2 */ 680 "\013SHA1,SHA256" /* PHE */ 681 "\015RSA" /* PMM */ 682 ); 683 }
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