Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/identcpu.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD: releng/8.3/sys/amd64/amd64/identcpu.c 222153 2011-05-20 22:38:02Z jkim $"); 43 44 #include "opt_cpu.h" 45 46 #include <sys/param.h> 47 #include <sys/bus.h> 48 #include <sys/cpu.h> 49 #include <sys/eventhandler.h> 50 #include <sys/systm.h> 51 #include <sys/kernel.h> 52 #include <sys/sysctl.h> 53 #include <sys/power.h> 54 55 #include <machine/asmacros.h> 56 #include <machine/clock.h> 57 #include <machine/cputypes.h> 58 #include <machine/frame.h> 59 #include <machine/intr_machdep.h> 60 #include <machine/segments.h> 61 #include <machine/specialreg.h> 62 #include <machine/md_var.h> 63 64 #include <amd64/isa/icu.h> 65 66 /* XXX - should be in header file: */ 67 void printcpuinfo(void); 68 void identify_cpu(void); 69 void earlysetcpuclass(void); 70 void panicifcpuunsupported(void); 71 72 static u_int find_cpu_vendor_id(void); 73 static void print_AMD_info(void); 74 static void print_AMD_assoc(int i); 75 static void print_via_padlock_info(void); 76 77 int cpu_class; 78 char machine[] = "amd64"; 79 80 #ifdef SCTL_MASK32 81 extern int adaptive_machine_arch; 82 #endif 83 84 static int 85 sysctl_hw_machine(SYSCTL_HANDLER_ARGS) 86 { 87 #ifdef SCTL_MASK32 88 static const char machine32[] = "i386"; 89 #endif 90 int error; 91 92 #ifdef SCTL_MASK32 93 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) 94 error = SYSCTL_OUT(req, machine32, sizeof(machine32)); 95 else 96 #endif 97 error = SYSCTL_OUT(req, machine, sizeof(machine)); 98 return (error); 99 100 } 101 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD, 102 NULL, 0, sysctl_hw_machine, "A", "Machine class"); 103 104 static char cpu_model[128]; 105 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 106 cpu_model, 0, "Machine model"); 107 108 static int hw_clockrate; 109 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 110 &hw_clockrate, 0, "CPU instruction clock rate"); 111 112 static char cpu_brand[48]; 113 114 static struct { 115 char *cpu_name; 116 int cpu_class; 117 } amd64_cpus[] = { 118 { "Clawhammer", CPUCLASS_K8 }, /* CPU_CLAWHAMMER */ 119 { "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */ 120 }; 121 122 static struct { 123 char *vendor; 124 u_int vendor_id; 125 } cpu_vendors[] = { 126 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 127 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 128 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 129 }; 130 131 132 void 133 printcpuinfo(void) 134 { 135 u_int regs[4], i; 136 char *brand; 137 138 cpu_class = amd64_cpus[cpu].cpu_class; 139 printf("CPU: "); 140 strncpy(cpu_model, amd64_cpus[cpu].cpu_name, sizeof (cpu_model)); 141 142 /* Check for extended CPUID information and a processor name. */ 143 if (cpu_exthigh >= 0x80000004) { 144 brand = cpu_brand; 145 for (i = 0x80000002; i < 0x80000005; i++) { 146 do_cpuid(i, regs); 147 memcpy(brand, regs, sizeof(regs)); 148 brand += sizeof(regs); 149 } 150 } 151 152 switch (cpu_vendor_id) { 153 case CPU_VENDOR_INTEL: 154 /* Please make up your mind folks! */ 155 strcat(cpu_model, "EM64T"); 156 break; 157 case CPU_VENDOR_AMD: 158 /* 159 * Values taken from AMD Processor Recognition 160 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 161 * (also describes ``Features'' encodings. 162 */ 163 strcpy(cpu_model, "AMD "); 164 if ((cpu_id & 0xf00) == 0xf00) 165 strcat(cpu_model, "AMD64 Processor"); 166 else 167 strcat(cpu_model, "Unknown"); 168 break; 169 case CPU_VENDOR_CENTAUR: 170 strcpy(cpu_model, "VIA "); 171 if ((cpu_id & 0xff0) == 0x6f0) 172 strcat(cpu_model, "Nano Processor"); 173 else 174 strcat(cpu_model, "Unknown"); 175 break; 176 default: 177 strcat(cpu_model, "Unknown"); 178 break; 179 } 180 181 /* 182 * Replace cpu_model with cpu_brand minus leading spaces if 183 * we have one. 184 */ 185 brand = cpu_brand; 186 while (*brand == ' ') 187 ++brand; 188 if (*brand != '\0') 189 strcpy(cpu_model, brand); 190 191 printf("%s (", cpu_model); 192 switch(cpu_class) { 193 case CPUCLASS_K8: 194 hw_clockrate = (tsc_freq + 5000) / 1000000; 195 printf("%jd.%02d-MHz ", 196 (intmax_t)(tsc_freq + 4999) / 1000000, 197 (u_int)((tsc_freq + 4999) / 10000) % 100); 198 printf("K8"); 199 break; 200 default: 201 printf("Unknown"); /* will panic below... */ 202 } 203 printf("-class CPU)\n"); 204 if (*cpu_vendor) 205 printf(" Origin = \"%s\"", cpu_vendor); 206 if (cpu_id) 207 printf(" Id = 0x%x", cpu_id); 208 209 if (cpu_vendor_id == CPU_VENDOR_INTEL || 210 cpu_vendor_id == CPU_VENDOR_AMD || 211 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 212 printf(" Family = %x", CPUID_TO_FAMILY(cpu_id)); 213 printf(" Model = %x", CPUID_TO_MODEL(cpu_id)); 214 printf(" Stepping = %u", cpu_id & CPUID_STEPPING); 215 216 /* 217 * AMD CPUID Specification 218 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf 219 * 220 * Intel Processor Identification and CPUID Instruction 221 * http://www.intel.com/assets/pdf/appnote/241618.pdf 222 */ 223 if (cpu_high > 0) { 224 225 /* 226 * Here we should probably set up flags indicating 227 * whether or not various features are available. 228 * The interesting ones are probably VME, PSE, PAE, 229 * and PGE. The code already assumes without bothering 230 * to check that all CPUs >= Pentium have a TSC and 231 * MSRs. 232 */ 233 printf("\n Features=0x%b", cpu_feature, 234 "\020" 235 "\001FPU" /* Integral FPU */ 236 "\002VME" /* Extended VM86 mode support */ 237 "\003DE" /* Debugging Extensions (CR4.DE) */ 238 "\004PSE" /* 4MByte page tables */ 239 "\005TSC" /* Timestamp counter */ 240 "\006MSR" /* Machine specific registers */ 241 "\007PAE" /* Physical address extension */ 242 "\010MCE" /* Machine Check support */ 243 "\011CX8" /* CMPEXCH8 instruction */ 244 "\012APIC" /* SMP local APIC */ 245 "\013oldMTRR" /* Previous implementation of MTRR */ 246 "\014SEP" /* Fast System Call */ 247 "\015MTRR" /* Memory Type Range Registers */ 248 "\016PGE" /* PG_G (global bit) support */ 249 "\017MCA" /* Machine Check Architecture */ 250 "\020CMOV" /* CMOV instruction */ 251 "\021PAT" /* Page attributes table */ 252 "\022PSE36" /* 36 bit address space support */ 253 "\023PN" /* Processor Serial number */ 254 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 255 "\025<b20>" 256 "\026DTS" /* Debug Trace Store */ 257 "\027ACPI" /* ACPI support */ 258 "\030MMX" /* MMX instructions */ 259 "\031FXSR" /* FXSAVE/FXRSTOR */ 260 "\032SSE" /* Streaming SIMD Extensions */ 261 "\033SSE2" /* Streaming SIMD Extensions #2 */ 262 "\034SS" /* Self snoop */ 263 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 264 "\036TM" /* Thermal Monitor clock slowdown */ 265 "\037IA64" /* CPU can execute IA64 instructions */ 266 "\040PBE" /* Pending Break Enable */ 267 ); 268 269 if (cpu_feature2 != 0) { 270 printf("\n Features2=0x%b", cpu_feature2, 271 "\020" 272 "\001SSE3" /* SSE3 */ 273 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ 274 "\003DTES64" /* 64-bit Debug Trace */ 275 "\004MON" /* MONITOR/MWAIT Instructions */ 276 "\005DS_CPL" /* CPL Qualified Debug Store */ 277 "\006VMX" /* Virtual Machine Extensions */ 278 "\007SMX" /* Safer Mode Extensions */ 279 "\010EST" /* Enhanced SpeedStep */ 280 "\011TM2" /* Thermal Monitor 2 */ 281 "\012SSSE3" /* SSSE3 */ 282 "\013CNXT-ID" /* L1 context ID available */ 283 "\014<b11>" 284 "\015FMA" /* Fused Multiply Add */ 285 "\016CX16" /* CMPXCHG16B Instruction */ 286 "\017xTPR" /* Send Task Priority Messages*/ 287 "\020PDCM" /* Perf/Debug Capability MSR */ 288 "\021<b16>" 289 "\022PCID" /* Process-context Identifiers*/ 290 "\023DCA" /* Direct Cache Access */ 291 "\024SSE4.1" /* SSE 4.1 */ 292 "\025SSE4.2" /* SSE 4.2 */ 293 "\026x2APIC" /* xAPIC Extensions */ 294 "\027MOVBE" /* MOVBE Instruction */ 295 "\030POPCNT" /* POPCNT Instruction */ 296 "\031TSCDLT" /* TSC-Deadline Timer */ 297 "\032AESNI" /* AES Crypto */ 298 "\033XSAVE" /* XSAVE/XRSTOR States */ 299 "\034OSXSAVE" /* OS-Enabled State Management*/ 300 "\035AVX" /* Advanced Vector Extensions */ 301 "\036F16C" /* Half-precision conversions */ 302 "\037<b30>" 303 "\040HV" /* Hypervisor */ 304 ); 305 } 306 307 if (amd_feature != 0) { 308 printf("\n AMD Features=0x%b", amd_feature, 309 "\020" /* in hex */ 310 "\001<s0>" /* Same */ 311 "\002<s1>" /* Same */ 312 "\003<s2>" /* Same */ 313 "\004<s3>" /* Same */ 314 "\005<s4>" /* Same */ 315 "\006<s5>" /* Same */ 316 "\007<s6>" /* Same */ 317 "\010<s7>" /* Same */ 318 "\011<s8>" /* Same */ 319 "\012<s9>" /* Same */ 320 "\013<b10>" /* Undefined */ 321 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 322 "\015<s12>" /* Same */ 323 "\016<s13>" /* Same */ 324 "\017<s14>" /* Same */ 325 "\020<s15>" /* Same */ 326 "\021<s16>" /* Same */ 327 "\022<s17>" /* Same */ 328 "\023<b18>" /* Reserved, unknown */ 329 "\024MP" /* Multiprocessor Capable */ 330 "\025NX" /* Has EFER.NXE, NX */ 331 "\026<b21>" /* Undefined */ 332 "\027MMX+" /* AMD MMX Extensions */ 333 "\030<s23>" /* Same */ 334 "\031<s24>" /* Same */ 335 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 336 "\033Page1GB" /* 1-GB large page support */ 337 "\034RDTSCP" /* RDTSCP */ 338 "\035<b28>" /* Undefined */ 339 "\036LM" /* 64 bit long mode */ 340 "\0373DNow!+" /* AMD 3DNow! Extensions */ 341 "\0403DNow!" /* AMD 3DNow! */ 342 ); 343 } 344 345 if (amd_feature2 != 0) { 346 printf("\n AMD Features2=0x%b", amd_feature2, 347 "\020" 348 "\001LAHF" /* LAHF/SAHF in long mode */ 349 "\002CMP" /* CMP legacy */ 350 "\003SVM" /* Secure Virtual Mode */ 351 "\004ExtAPIC" /* Extended APIC register */ 352 "\005CR8" /* CR8 in legacy mode */ 353 "\006ABM" /* LZCNT instruction */ 354 "\007SSE4A" /* SSE4A */ 355 "\010MAS" /* Misaligned SSE mode */ 356 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 357 "\012OSVW" /* OS visible workaround */ 358 "\013IBS" /* Instruction based sampling */ 359 "\014XOP" /* XOP extended instructions */ 360 "\015SKINIT" /* SKINIT/STGI */ 361 "\016WDT" /* Watchdog timer */ 362 "\017<b14>" 363 "\020LWP" /* Lightweight Profiling */ 364 "\021FMA4" /* 4-operand FMA instructions */ 365 "\022<b17>" 366 "\023<b18>" 367 "\024NodeId" /* NodeId MSR support */ 368 "\025<b20>" 369 "\026TBM" /* Trailing Bit Manipulation */ 370 "\027Topology" /* Topology Extensions */ 371 "\030<b23>" 372 "\031<b24>" 373 "\032<b25>" 374 "\033<b26>" 375 "\034<b27>" 376 "\035<b28>" 377 "\036<b29>" 378 "\037<b30>" 379 "\040<b31>" 380 ); 381 } 382 383 if (cpu_vendor_id == CPU_VENDOR_CENTAUR) 384 print_via_padlock_info(); 385 386 if ((cpu_feature & CPUID_HTT) && 387 cpu_vendor_id == CPU_VENDOR_AMD) 388 cpu_feature &= ~CPUID_HTT; 389 390 /* 391 * If this CPU supports P-state invariant TSC then 392 * mention the capability. 393 */ 394 switch (cpu_vendor_id) { 395 case CPU_VENDOR_AMD: 396 if ((amd_pminfo & AMDPM_TSC_INVARIANT) || 397 CPUID_TO_FAMILY(cpu_id) >= 0x10 || 398 cpu_id == 0x60fb2) 399 tsc_is_invariant = 1; 400 break; 401 case CPU_VENDOR_INTEL: 402 if ((amd_pminfo & AMDPM_TSC_INVARIANT) || 403 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 404 CPUID_TO_MODEL(cpu_id) >= 0xe) || 405 (CPUID_TO_FAMILY(cpu_id) == 0xf && 406 CPUID_TO_MODEL(cpu_id) >= 0x3)) 407 tsc_is_invariant = 1; 408 break; 409 case CPU_VENDOR_CENTAUR: 410 if (CPUID_TO_FAMILY(cpu_id) == 0x6 && 411 CPUID_TO_MODEL(cpu_id) >= 0xf && 412 (rdmsr(0x1203) & 0x100000000ULL) == 0) 413 tsc_is_invariant = 1; 414 break; 415 } 416 if (tsc_is_invariant) 417 printf("\n TSC: P-state invariant"); 418 419 } 420 } 421 /* Avoid ugly blank lines: only print newline when we have to. */ 422 if (*cpu_vendor || cpu_id) 423 printf("\n"); 424 425 if (!bootverbose) 426 return; 427 428 if (cpu_vendor_id == CPU_VENDOR_AMD) 429 print_AMD_info(); 430 } 431 432 void 433 panicifcpuunsupported(void) 434 { 435 436 #ifndef HAMMER 437 #error "You need to specify a cpu type" 438 #endif 439 /* 440 * Now that we have told the user what they have, 441 * let them know if that machine type isn't configured. 442 */ 443 switch (cpu_class) { 444 case CPUCLASS_X86: 445 #ifndef HAMMER 446 case CPUCLASS_K8: 447 #endif 448 panic("CPU class not configured"); 449 default: 450 break; 451 } 452 } 453 454 455 /* Update TSC freq with the value indicated by the caller. */ 456 static void 457 tsc_freq_changed(void *arg, const struct cf_level *level, int status) 458 { 459 /* 460 * If there was an error during the transition or 461 * TSC is P-state invariant, don't do anything. 462 */ 463 if (status != 0 || tsc_is_invariant) 464 return; 465 466 /* Total setting for this level gives the new frequency in MHz. */ 467 hw_clockrate = level->total_set.freq; 468 } 469 470 EVENTHANDLER_DEFINE(cpufreq_post_change, tsc_freq_changed, NULL, 471 EVENTHANDLER_PRI_ANY); 472 473 /* 474 * Final stage of CPU identification. 475 */ 476 void 477 identify_cpu(void) 478 { 479 u_int regs[4]; 480 481 do_cpuid(0, regs); 482 cpu_high = regs[0]; 483 ((u_int *)&cpu_vendor)[0] = regs[1]; 484 ((u_int *)&cpu_vendor)[1] = regs[3]; 485 ((u_int *)&cpu_vendor)[2] = regs[2]; 486 cpu_vendor[12] = '\0'; 487 cpu_vendor_id = find_cpu_vendor_id(); 488 489 do_cpuid(1, regs); 490 cpu_id = regs[0]; 491 cpu_procinfo = regs[1]; 492 cpu_feature = regs[3]; 493 cpu_feature2 = regs[2]; 494 495 /* 496 * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID 497 * function number again if it is set from BIOS. It is necessary 498 * for probing correct CPU topology later. 499 * XXX This is only done on the BSP package. 500 */ 501 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4) { 502 uint64_t msr; 503 msr = rdmsr(MSR_IA32_MISC_ENABLE); 504 if ((msr & 0x400000ULL) != 0) { 505 wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL); 506 do_cpuid(0, regs); 507 cpu_high = regs[0]; 508 } 509 } 510 511 if (cpu_vendor_id == CPU_VENDOR_INTEL || 512 cpu_vendor_id == CPU_VENDOR_AMD || 513 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 514 do_cpuid(0x80000000, regs); 515 cpu_exthigh = regs[0]; 516 } 517 if (cpu_exthigh >= 0x80000001) { 518 do_cpuid(0x80000001, regs); 519 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 520 amd_feature2 = regs[2]; 521 } 522 if (cpu_exthigh >= 0x80000007) { 523 do_cpuid(0x80000007, regs); 524 amd_pminfo = regs[3]; 525 } 526 if (cpu_exthigh >= 0x80000008) { 527 do_cpuid(0x80000008, regs); 528 cpu_procinfo2 = regs[2]; 529 } 530 531 /* XXX */ 532 cpu = CPU_CLAWHAMMER; 533 } 534 535 static u_int 536 find_cpu_vendor_id(void) 537 { 538 int i; 539 540 for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++) 541 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 542 return (cpu_vendors[i].vendor_id); 543 return (0); 544 } 545 546 static void 547 print_AMD_assoc(int i) 548 { 549 if (i == 255) 550 printf(", fully associative\n"); 551 else 552 printf(", %d-way associative\n", i); 553 } 554 555 static void 556 print_AMD_l2_assoc(int i) 557 { 558 switch (i & 0x0f) { 559 case 0: printf(", disabled/not present\n"); break; 560 case 1: printf(", direct mapped\n"); break; 561 case 2: printf(", 2-way associative\n"); break; 562 case 4: printf(", 4-way associative\n"); break; 563 case 6: printf(", 8-way associative\n"); break; 564 case 8: printf(", 16-way associative\n"); break; 565 case 15: printf(", fully associative\n"); break; 566 default: printf(", reserved configuration\n"); break; 567 } 568 } 569 570 static void 571 print_AMD_info(void) 572 { 573 u_int regs[4]; 574 575 if (cpu_exthigh < 0x80000005) 576 return; 577 578 do_cpuid(0x80000005, regs); 579 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 580 print_AMD_assoc(regs[0] >> 24); 581 582 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 583 print_AMD_assoc((regs[0] >> 8) & 0xff); 584 585 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 586 print_AMD_assoc(regs[1] >> 24); 587 588 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 589 print_AMD_assoc((regs[1] >> 8) & 0xff); 590 591 printf("L1 data cache: %d kbytes", regs[2] >> 24); 592 printf(", %d bytes/line", regs[2] & 0xff); 593 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 594 print_AMD_assoc((regs[2] >> 16) & 0xff); 595 596 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 597 printf(", %d bytes/line", regs[3] & 0xff); 598 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 599 print_AMD_assoc((regs[3] >> 16) & 0xff); 600 601 if (cpu_exthigh >= 0x80000006) { 602 do_cpuid(0x80000006, regs); 603 if ((regs[0] >> 16) != 0) { 604 printf("L2 2MB data TLB: %d entries", 605 (regs[0] >> 16) & 0xfff); 606 print_AMD_l2_assoc(regs[0] >> 28); 607 printf("L2 2MB instruction TLB: %d entries", 608 regs[0] & 0xfff); 609 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 610 } else { 611 printf("L2 2MB unified TLB: %d entries", 612 regs[0] & 0xfff); 613 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 614 } 615 if ((regs[1] >> 16) != 0) { 616 printf("L2 4KB data TLB: %d entries", 617 (regs[1] >> 16) & 0xfff); 618 print_AMD_l2_assoc(regs[1] >> 28); 619 620 printf("L2 4KB instruction TLB: %d entries", 621 (regs[1] >> 16) & 0xfff); 622 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 623 } else { 624 printf("L2 4KB unified TLB: %d entries", 625 (regs[1] >> 16) & 0xfff); 626 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 627 } 628 printf("L2 unified cache: %d kbytes", regs[2] >> 16); 629 printf(", %d bytes/line", regs[2] & 0xff); 630 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 631 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 632 } 633 634 /* 635 * Opteron Rev E shows a bug as in very rare occasions a read memory 636 * barrier is not performed as expected if it is followed by a 637 * non-atomic read-modify-write instruction. 638 * As long as that bug pops up very rarely (intensive machine usage 639 * on other operating systems generally generates one unexplainable 640 * crash any 2 months) and as long as a model specific fix would be 641 * impratical at this stage, print out a warning string if the broken 642 * model and family are identified. 643 */ 644 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && 645 CPUID_TO_MODEL(cpu_id) <= 0x3f) 646 printf("WARNING: This architecture revision has known SMP " 647 "hardware bugs which may cause random instability\n"); 648 } 649 650 static void 651 print_via_padlock_info(void) 652 { 653 u_int regs[4]; 654 655 /* Check for supported models. */ 656 switch (cpu_id & 0xff0) { 657 case 0x690: 658 if ((cpu_id & 0xf) < 3) 659 return; 660 case 0x6a0: 661 case 0x6d0: 662 case 0x6f0: 663 break; 664 default: 665 return; 666 } 667 668 do_cpuid(0xc0000000, regs); 669 if (regs[0] >= 0xc0000001) 670 do_cpuid(0xc0000001, regs); 671 else 672 return; 673 674 printf("\n VIA Padlock Features=0x%b", regs[3], 675 "\020" 676 "\003RNG" /* RNG */ 677 "\007AES" /* ACE */ 678 "\011AES-CTR" /* ACE2 */ 679 "\013SHA1,SHA256" /* PHE */ 680 "\015RSA" /* PMM */ 681 ); 682 }
Cache object: 9a8106b62a1b1df4a884bff1e4ac9ac1
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]