1 /*-
2 * Copyright (c) KATO Takenori, 1997, 1998.
3 *
4 * All rights reserved. Unpublished rights reserved under the copyright
5 * laws of Japan.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer as
13 * the first lines of this file unmodified.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD: releng/10.2/sys/amd64/amd64/initcpu.c 284338 2015-06-13 07:31:50Z kib $");
32
33 #include "opt_cpu.h"
34
35 #include <sys/param.h>
36 #include <sys/kernel.h>
37 #include <sys/pcpu.h>
38 #include <sys/systm.h>
39 #include <sys/sysctl.h>
40
41 #include <machine/cputypes.h>
42 #include <machine/md_var.h>
43 #include <machine/specialreg.h>
44
45 #include <vm/vm.h>
46 #include <vm/pmap.h>
47
48 static int hw_instruction_sse;
49 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
50 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
51 /*
52 * -1: automatic (default)
53 * 0: keep enable CLFLUSH
54 * 1: force disable CLFLUSH
55 */
56 static int hw_clflush_disable = -1;
57
58 int cpu; /* Are we 386, 386sx, 486, etc? */
59 u_int cpu_feature; /* Feature flags */
60 u_int cpu_feature2; /* Feature flags */
61 u_int amd_feature; /* AMD feature flags */
62 u_int amd_feature2; /* AMD feature flags */
63 u_int amd_pminfo; /* AMD advanced power management info */
64 u_int via_feature_rng; /* VIA RNG features */
65 u_int via_feature_xcrypt; /* VIA ACE features */
66 u_int cpu_high; /* Highest arg to CPUID */
67 u_int cpu_exthigh; /* Highest arg to extended CPUID */
68 u_int cpu_id; /* Stepping ID */
69 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
70 u_int cpu_procinfo2; /* Multicore info */
71 char cpu_vendor[20]; /* CPU Origin code */
72 u_int cpu_vendor_id; /* CPU vendor ID */
73 u_int cpu_fxsr; /* SSE enabled */
74 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
75 u_int cpu_clflush_line_size = 32;
76 u_int cpu_stdext_feature;
77 u_int cpu_stdext_feature2;
78 u_int cpu_max_ext_state_size;
79 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
80 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
81 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */
82 u_int cpu_maxphyaddr; /* Max phys addr width in bits */
83
84 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
85 &via_feature_rng, 0, "VIA RNG feature available in CPU");
86 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
87 &via_feature_xcrypt, 0, "VIA xcrypt feature available in CPU");
88
89 static void
90 init_amd(void)
91 {
92
93 /*
94 * Work around Erratum 721 for Family 10h and 12h processors.
95 * These processors may incorrectly update the stack pointer
96 * after a long series of push and/or near-call instructions,
97 * or a long series of pop and/or near-return instructions.
98 *
99 * http://support.amd.com/us/Processor_TechDocs/41322_10h_Rev_Gd.pdf
100 * http://support.amd.com/us/Processor_TechDocs/44739_12h_Rev_Gd.pdf
101 *
102 * Hypervisors do not provide access to the errata MSR,
103 * causing #GP exception on attempt to apply the errata. The
104 * MSR write shall be done on host and persist globally
105 * anyway, so do not try to do it when under virtualization.
106 */
107 switch (CPUID_TO_FAMILY(cpu_id)) {
108 case 0x10:
109 case 0x12:
110 if ((cpu_feature2 & CPUID2_HV) == 0)
111 wrmsr(0xc0011029, rdmsr(0xc0011029) | 1);
112 break;
113 }
114 }
115
116 /*
117 * Initialize special VIA features
118 */
119 static void
120 init_via(void)
121 {
122 u_int regs[4], val;
123
124 /*
125 * Check extended CPUID for PadLock features.
126 *
127 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf
128 */
129 do_cpuid(0xc0000000, regs);
130 if (regs[0] >= 0xc0000001) {
131 do_cpuid(0xc0000001, regs);
132 val = regs[3];
133 } else
134 return;
135
136 /* Enable RNG if present. */
137 if ((val & VIA_CPUID_HAS_RNG) != 0) {
138 via_feature_rng = VIA_HAS_RNG;
139 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);
140 }
141
142 /* Enable PadLock if present. */
143 if ((val & VIA_CPUID_HAS_ACE) != 0)
144 via_feature_xcrypt |= VIA_HAS_AES;
145 if ((val & VIA_CPUID_HAS_ACE2) != 0)
146 via_feature_xcrypt |= VIA_HAS_AESCTR;
147 if ((val & VIA_CPUID_HAS_PHE) != 0)
148 via_feature_xcrypt |= VIA_HAS_SHA;
149 if ((val & VIA_CPUID_HAS_PMM) != 0)
150 via_feature_xcrypt |= VIA_HAS_MM;
151 if (via_feature_xcrypt != 0)
152 wrmsr(0x1107, rdmsr(0x1107) | (1 << 28));
153 }
154
155 /*
156 * Initialize CPU control registers
157 */
158 void
159 initializecpu(void)
160 {
161 uint64_t msr;
162 uint32_t cr4;
163
164 cr4 = rcr4();
165 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
166 cr4 |= CR4_FXSR | CR4_XMM;
167 cpu_fxsr = hw_instruction_sse = 1;
168 }
169 if (cpu_stdext_feature & CPUID_STDEXT_FSGSBASE)
170 cr4 |= CR4_FSGSBASE;
171
172 /*
173 * Postpone enabling the SMEP on the boot CPU until the page
174 * tables are switched from the boot loader identity mapping
175 * to the kernel tables. The boot loader enables the U bit in
176 * its tables.
177 */
178 if (!IS_BSP() && (cpu_stdext_feature & CPUID_STDEXT_SMEP))
179 cr4 |= CR4_SMEP;
180 load_cr4(cr4);
181 if ((amd_feature & AMDID_NX) != 0) {
182 msr = rdmsr(MSR_EFER) | EFER_NXE;
183 wrmsr(MSR_EFER, msr);
184 pg_nx = PG_NX;
185 }
186 switch (cpu_vendor_id) {
187 case CPU_VENDOR_AMD:
188 init_amd();
189 break;
190 case CPU_VENDOR_CENTAUR:
191 init_via();
192 break;
193 }
194 }
195
196 void
197 initializecpucache(void)
198 {
199
200 /*
201 * CPUID with %eax = 1, %ebx returns
202 * Bits 15-8: CLFLUSH line size
203 * (Value * 8 = cache line size in bytes)
204 */
205 if ((cpu_feature & CPUID_CLFSH) != 0)
206 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8;
207 /*
208 * XXXKIB: (temporary) hack to work around traps generated
209 * when CLFLUSHing APIC register window under virtualization
210 * environments. These environments tend to disable the
211 * CPUID_SS feature even though the native CPU supports it.
212 */
213 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
214 if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1)
215 cpu_feature &= ~CPUID_CLFSH;
216 /*
217 * Allow to disable CLFLUSH feature manually by
218 * hw.clflush_disable tunable.
219 */
220 if (hw_clflush_disable == 1)
221 cpu_feature &= ~CPUID_CLFSH;
222 }
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