initcpu.c

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    1 /*-
    2  * Copyright (c) KATO Takenori, 1997, 1998.
    3  * 
    4  * All rights reserved.  Unpublished rights reserved under the copyright
    5  * laws of Japan.
    6  * 
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer as
   13  *    the first lines of this file unmodified.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 
   18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   28  */
   29 
   30 #include <sys/cdefs.h>
   31 __FBSDID("$FreeBSD$");
   32 
   33 #include "opt_cpu.h"
   34 
   35 #include <sys/param.h>
   36 #include <sys/kernel.h>
   37 #include <sys/pcpu.h>
   38 #include <sys/systm.h>
   39 #include <sys/sysctl.h>
   40 
   41 #include <machine/cputypes.h>
   42 #include <machine/md_var.h>
   43 #include <machine/specialreg.h>
   44 
   45 #include <vm/vm.h>
   46 #include <vm/pmap.h>
   47 
   48 static int      hw_instruction_sse;
   49 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
   50     &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
   51 /*
   52  * -1: automatic (default)
   53  *  0: keep enable CLFLUSH
   54  *  1: force disable CLFLUSH
   55  */
   56 static int      hw_clflush_disable = -1;
   57 
   58 int     cpu;                    /* Are we 386, 386sx, 486, etc? */
   59 u_int   cpu_feature;            /* Feature flags */
   60 u_int   cpu_feature2;           /* Feature flags */
   61 u_int   amd_feature;            /* AMD feature flags */
   62 u_int   amd_feature2;           /* AMD feature flags */
   63 u_int   amd_pminfo;             /* AMD advanced power management info */
   64 u_int   via_feature_rng;        /* VIA RNG features */
   65 u_int   via_feature_xcrypt;     /* VIA ACE features */
   66 u_int   cpu_high;               /* Highest arg to CPUID */
   67 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
   68 u_int   cpu_id;                 /* Stepping ID */
   69 u_int   cpu_procinfo;           /* HyperThreading Info / Brand Index / CLFUSH */
   70 u_int   cpu_procinfo2;          /* Multicore info */
   71 char    cpu_vendor[20];         /* CPU Origin code */
   72 u_int   cpu_vendor_id;          /* CPU vendor ID */
   73 u_int   cpu_fxsr;               /* SSE enabled */
   74 u_int   cpu_mxcsr_mask;         /* Valid bits in mxcsr */
   75 u_int   cpu_clflush_line_size = 32;
   76 u_int   cpu_stdext_feature;
   77 u_int   cpu_stdext_feature2;
   78 u_int   cpu_max_ext_state_size;
   79 u_int   cpu_mon_mwait_flags;    /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
   80 u_int   cpu_mon_min_size;       /* MONITOR minimum range size, bytes */
   81 u_int   cpu_mon_max_size;       /* MONITOR minimum range size, bytes */
   82 u_int   cpu_maxphyaddr;         /* Max phys addr width in bits */
   83 
   84 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
   85         &via_feature_rng, 0, "VIA RNG feature available in CPU");
   86 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
   87         &via_feature_xcrypt, 0, "VIA xcrypt feature available in CPU");
   88 
   89 static void
   90 init_amd(void)
   91 {
   92         uint64_t msr;
   93 
   94         /*
   95          * Work around Erratum 721 for Family 10h and 12h processors.
   96          * These processors may incorrectly update the stack pointer
   97          * after a long series of push and/or near-call instructions,
   98          * or a long series of pop and/or near-return instructions.
   99          *
  100          * http://support.amd.com/us/Processor_TechDocs/41322_10h_Rev_Gd.pdf
  101          * http://support.amd.com/us/Processor_TechDocs/44739_12h_Rev_Gd.pdf
  102          *
  103          * Hypervisors do not provide access to the errata MSR,
  104          * causing #GP exception on attempt to apply the errata.  The
  105          * MSR write shall be done on host and persist globally
  106          * anyway, so do not try to do it when under virtualization.
  107          */
  108         switch (CPUID_TO_FAMILY(cpu_id)) {
  109         case 0x10:
  110         case 0x12:
  111                 if ((cpu_feature2 & CPUID2_HV) == 0)
  112                         wrmsr(0xc0011029, rdmsr(0xc0011029) | 1);
  113                 break;
  114         }
  115 
  116         /*
  117          * BIOS may fail to set InitApicIdCpuIdLo to 1 as it should per BKDG.
  118          * So, do it here or otherwise some tools could be confused by
  119          * Initial Local APIC ID reported with CPUID Function 1 in EBX.
  120          */
  121         if (CPUID_TO_FAMILY(cpu_id) == 0x10) {
  122                 if ((cpu_feature2 & CPUID2_HV) == 0) {
  123                         msr = rdmsr(MSR_NB_CFG1);
  124                         msr |= (uint64_t)1 << 54;
  125                         wrmsr(MSR_NB_CFG1, msr);
  126                 }
  127         }
  128 
  129         /*
  130          * BIOS may configure Family 10h processors to convert WC+ cache type
  131          * to CD.  That can hurt performance of guest VMs using nested paging.
  132          * The relevant MSR bit is not documented in the BKDG,
  133          * the fix is borrowed from Linux.
  134          */
  135         if (CPUID_TO_FAMILY(cpu_id) == 0x10) {
  136                 if ((cpu_feature2 & CPUID2_HV) == 0) {
  137                         msr = rdmsr(0xc001102a);
  138                         msr &= ~((uint64_t)1 << 24);
  139                         wrmsr(0xc001102a, msr);
  140                 }
  141         }
  142 
  143         /*
  144          * Work around Erratum 793: Specific Combination of Writes to Write
  145          * Combined Memory Types and Locked Instructions May Cause Core Hang.
  146          * See Revision Guide for AMD Family 16h Models 00h-0Fh Processors,
  147          * revision 3.04 or later, publication 51810.
  148          */
  149         if (CPUID_TO_FAMILY(cpu_id) == 0x16 && CPUID_TO_MODEL(cpu_id) <= 0xf) {
  150                 if ((cpu_feature2 & CPUID2_HV) == 0) {
  151                         msr = rdmsr(0xc0011020);
  152                         msr |= (uint64_t)1 << 15;
  153                         wrmsr(0xc0011020, msr);
  154                 }
  155         }
  156 }
  157 
  158 /*
  159  * Initialize special VIA features
  160  */
  161 static void
  162 init_via(void)
  163 {
  164         u_int regs[4], val;
  165 
  166         /*
  167          * Check extended CPUID for PadLock features.
  168          *
  169          * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf
  170          */
  171         do_cpuid(0xc0000000, regs);
  172         if (regs[0] >= 0xc0000001) {
  173                 do_cpuid(0xc0000001, regs);
  174                 val = regs[3];
  175         } else
  176                 return;
  177 
  178         /* Enable RNG if present. */
  179         if ((val & VIA_CPUID_HAS_RNG) != 0) {
  180                 via_feature_rng = VIA_HAS_RNG;
  181                 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);
  182         }
  183 
  184         /* Enable PadLock if present. */
  185         if ((val & VIA_CPUID_HAS_ACE) != 0)
  186                 via_feature_xcrypt |= VIA_HAS_AES;
  187         if ((val & VIA_CPUID_HAS_ACE2) != 0)
  188                 via_feature_xcrypt |= VIA_HAS_AESCTR;
  189         if ((val & VIA_CPUID_HAS_PHE) != 0)
  190                 via_feature_xcrypt |= VIA_HAS_SHA;
  191         if ((val & VIA_CPUID_HAS_PMM) != 0)
  192                 via_feature_xcrypt |= VIA_HAS_MM;
  193         if (via_feature_xcrypt != 0)
  194                 wrmsr(0x1107, rdmsr(0x1107) | (1 << 28));
  195 }
  196 
  197 /*
  198  * Initialize CPU control registers
  199  */
  200 void
  201 initializecpu(void)
  202 {
  203         uint64_t msr;
  204         uint32_t cr4;
  205 
  206         cr4 = rcr4();
  207         if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
  208                 cr4 |= CR4_FXSR | CR4_XMM;
  209                 cpu_fxsr = hw_instruction_sse = 1;
  210         }
  211         if (cpu_stdext_feature & CPUID_STDEXT_FSGSBASE)
  212                 cr4 |= CR4_FSGSBASE;
  213 
  214         /*
  215          * Postpone enabling the SMEP on the boot CPU until the page
  216          * tables are switched from the boot loader identity mapping
  217          * to the kernel tables.  The boot loader enables the U bit in
  218          * its tables.
  219          */
  220         if (!IS_BSP() && (cpu_stdext_feature & CPUID_STDEXT_SMEP))
  221                 cr4 |= CR4_SMEP;
  222         load_cr4(cr4);
  223         if ((amd_feature & AMDID_NX) != 0) {
  224                 msr = rdmsr(MSR_EFER) | EFER_NXE;
  225                 wrmsr(MSR_EFER, msr);
  226                 pg_nx = PG_NX;
  227         }
  228         switch (cpu_vendor_id) {
  229         case CPU_VENDOR_AMD:
  230                 init_amd();
  231                 break;
  232         case CPU_VENDOR_CENTAUR:
  233                 init_via();
  234                 break;
  235         }
  236 }
  237 
  238 void
  239 initializecpucache(void)
  240 {
  241 
  242         /*
  243          * CPUID with %eax = 1, %ebx returns
  244          * Bits 15-8: CLFLUSH line size
  245          *      (Value * 8 = cache line size in bytes)
  246          */
  247         if ((cpu_feature & CPUID_CLFSH) != 0)
  248                 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8;
  249         /*
  250          * XXXKIB: (temporary) hack to work around traps generated
  251          * when CLFLUSHing APIC register window under virtualization
  252          * environments.  These environments tend to disable the
  253          * CPUID_SS feature even though the native CPU supports it.
  254          */
  255         TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
  256         if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1) {
  257                 cpu_feature &= ~CPUID_CLFSH;
  258                 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT;
  259         }
  260 
  261         /*
  262          * The kernel's use of CLFLUSH{,OPT} can be disabled manually
  263          * by setting the hw.clflush_disable tunable.
  264          */
  265         if (hw_clflush_disable == 1) {
  266                 cpu_feature &= ~CPUID_CLFSH;
  267                 cpu_stdext_feature &= ~CPUID_STDEXT_CLFLUSHOPT;
  268         }
  269 }
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FreeBSD/Linux Kernel Cross Reference sys/amd64/amd64/initcpu.c

FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/initcpu.c
