Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/initcpu.c
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1 /*- 2 * Copyright (c) KATO Takenori, 1997, 1998. 3 * 4 * All rights reserved. Unpublished rights reserved under the copyright 5 * laws of Japan. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer as 13 * the first lines of this file unmodified. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD: releng/7.3/sys/amd64/amd64/initcpu.c 203047 2010-01-26 20:58:09Z jhb $"); 32 33 #include "opt_cpu.h" 34 35 #include <sys/param.h> 36 #include <sys/kernel.h> 37 #include <sys/systm.h> 38 #include <sys/sysctl.h> 39 40 #include <machine/cputypes.h> 41 #include <machine/md_var.h> 42 #include <machine/specialreg.h> 43 44 #include <vm/vm.h> 45 #include <vm/pmap.h> 46 47 static int hw_instruction_sse; 48 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 49 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 50 /* 51 * -1: automatic (default) 52 * 0: keep enable CLFLUSH 53 * 1: force disable CLFLUSH 54 */ 55 static int hw_clflush_disable = -1; 56 57 int cpu; /* Are we 386, 386sx, 486, etc? */ 58 u_int cpu_feature; /* Feature flags */ 59 u_int cpu_feature2; /* Feature flags */ 60 u_int amd_feature; /* AMD feature flags */ 61 u_int amd_feature2; /* AMD feature flags */ 62 u_int amd_pminfo; /* AMD advanced power management info */ 63 u_int via_feature_rng; /* VIA RNG features */ 64 u_int via_feature_xcrypt; /* VIA ACE features */ 65 u_int cpu_high; /* Highest arg to CPUID */ 66 u_int cpu_exthigh; /* Highest arg to extended CPUID */ 67 u_int cpu_id; /* Stepping ID */ 68 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ 69 u_int cpu_procinfo2; /* Multicore info */ 70 char cpu_vendor[20]; /* CPU Origin code */ 71 u_int cpu_vendor_id; /* CPU vendor ID */ 72 u_int cpu_fxsr; /* SSE enabled */ 73 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ 74 u_int cpu_clflush_line_size = 32; 75 76 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 77 &via_feature_rng, 0, "VIA C3/C7 RNG feature available in CPU"); 78 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 79 &via_feature_xcrypt, 0, "VIA C3/C7 xcrypt feature available in CPU"); 80 81 /* 82 * Initialize special VIA C3/C7 features 83 */ 84 static void 85 init_via(void) 86 { 87 u_int regs[4], val; 88 u_int64_t msreg; 89 90 do_cpuid(0xc0000000, regs); 91 val = regs[0]; 92 if (val >= 0xc0000001) { 93 do_cpuid(0xc0000001, regs); 94 val = regs[3]; 95 } else 96 val = 0; 97 98 /* Enable RNG if present and disabled */ 99 if (val & VIA_CPUID_HAS_RNG) { 100 if (!(val & VIA_CPUID_DO_RNG)) { 101 msreg = rdmsr(0x110B); 102 msreg |= 0x40; 103 wrmsr(0x110B, msreg); 104 } 105 via_feature_rng = VIA_HAS_RNG; 106 } 107 /* Enable AES engine if present and disabled */ 108 if (val & VIA_CPUID_HAS_ACE) { 109 if (!(val & VIA_CPUID_DO_ACE)) { 110 msreg = rdmsr(0x1107); 111 msreg |= (0x01 << 28); 112 wrmsr(0x1107, msreg); 113 } 114 via_feature_xcrypt |= VIA_HAS_AES; 115 } 116 /* Enable ACE2 engine if present and disabled */ 117 if (val & VIA_CPUID_HAS_ACE2) { 118 if (!(val & VIA_CPUID_DO_ACE2)) { 119 msreg = rdmsr(0x1107); 120 msreg |= (0x01 << 28); 121 wrmsr(0x1107, msreg); 122 } 123 via_feature_xcrypt |= VIA_HAS_AESCTR; 124 } 125 /* Enable SHA engine if present and disabled */ 126 if (val & VIA_CPUID_HAS_PHE) { 127 if (!(val & VIA_CPUID_DO_PHE)) { 128 msreg = rdmsr(0x1107); 129 msreg |= (0x01 << 28/**/); 130 wrmsr(0x1107, msreg); 131 } 132 via_feature_xcrypt |= VIA_HAS_SHA; 133 } 134 /* Enable MM engine if present and disabled */ 135 if (val & VIA_CPUID_HAS_PMM) { 136 if (!(val & VIA_CPUID_DO_PMM)) { 137 msreg = rdmsr(0x1107); 138 msreg |= (0x01 << 28/**/); 139 wrmsr(0x1107, msreg); 140 } 141 via_feature_xcrypt |= VIA_HAS_MM; 142 } 143 } 144 145 /* 146 * Initialize CPU control registers 147 */ 148 void 149 initializecpu(void) 150 { 151 uint64_t msr; 152 153 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { 154 load_cr4(rcr4() | CR4_FXSR | CR4_XMM); 155 cpu_fxsr = hw_instruction_sse = 1; 156 } 157 if ((amd_feature & AMDID_NX) != 0) { 158 msr = rdmsr(MSR_EFER) | EFER_NXE; 159 wrmsr(MSR_EFER, msr); 160 pg_nx = PG_NX; 161 } 162 if (cpu_vendor_id == CPU_VENDOR_CENTAUR && 163 CPUID_TO_FAMILY(cpu_id) == 0x6 && 164 CPUID_TO_MODEL(cpu_id) >= 0xf) 165 init_via(); 166 } 167 168 void 169 initializecpucache() 170 { 171 172 /* 173 * CPUID with %eax = 1, %ebx returns 174 * Bits 15-8: CLFLUSH line size 175 * (Value * 8 = cache line size in bytes) 176 */ 177 if ((cpu_feature & CPUID_CLFSH) != 0) 178 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8; 179 /* 180 * XXXKIB: (temporary) hack to work around traps generated when 181 * CLFLUSHing APIC registers window. 182 */ 183 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable); 184 if (cpu_vendor_id == CPU_VENDOR_INTEL && !(cpu_feature & CPUID_SS) && 185 hw_clflush_disable == -1) 186 cpu_feature &= ~CPUID_CLFSH; 187 /* 188 * Allow to disable CLFLUSH feature manually by 189 * hw.clflush_disable tunable. This may help Xen guest on some AMD 190 * CPUs. 191 */ 192 if (hw_clflush_disable == 1) 193 cpu_feature &= ~CPUID_CLFSH; 194 }
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