Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/initcpu.c
Version:
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1 /*- 2 * Copyright (c) KATO Takenori, 1997, 1998. 3 * 4 * All rights reserved. Unpublished rights reserved under the copyright 5 * laws of Japan. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer as 13 * the first lines of this file unmodified. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include "opt_cpu.h" 34 35 #include <sys/param.h> 36 #include <sys/kernel.h> 37 #include <sys/systm.h> 38 #include <sys/sysctl.h> 39 40 #include <machine/cputypes.h> 41 #include <machine/md_var.h> 42 #include <machine/specialreg.h> 43 44 #include <vm/vm.h> 45 #include <vm/pmap.h> 46 47 static int hw_instruction_sse; 48 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 49 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 50 /* 51 * -1: automatic (default) 52 * 0: keep enable CLFLUSH 53 * 1: force disable CLFLUSH 54 */ 55 static int hw_clflush_disable = -1; 56 57 int cpu; /* Are we 386, 386sx, 486, etc? */ 58 u_int cpu_feature; /* Feature flags */ 59 u_int cpu_feature2; /* Feature flags */ 60 u_int amd_feature; /* AMD feature flags */ 61 u_int amd_feature2; /* AMD feature flags */ 62 u_int amd_pminfo; /* AMD advanced power management info */ 63 u_int via_feature_rng; /* VIA RNG features */ 64 u_int via_feature_xcrypt; /* VIA ACE features */ 65 u_int cpu_high; /* Highest arg to CPUID */ 66 u_int cpu_exthigh; /* Highest arg to extended CPUID */ 67 u_int cpu_id; /* Stepping ID */ 68 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ 69 u_int cpu_procinfo2; /* Multicore info */ 70 char cpu_vendor[20]; /* CPU Origin code */ 71 u_int cpu_vendor_id; /* CPU vendor ID */ 72 u_int cpu_fxsr; /* SSE enabled */ 73 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ 74 u_int cpu_clflush_line_size = 32; 75 76 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 77 &via_feature_rng, 0, "VIA C3/C7 RNG feature available in CPU"); 78 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 79 &via_feature_xcrypt, 0, "VIA C3/C7 xcrypt feature available in CPU"); 80 81 static void 82 init_amd(void) 83 { 84 85 /* 86 * Work around Erratum 721 for Family 10h and 12h processors. 87 * These processors may incorrectly update the stack pointer 88 * after a long series of push and/or near-call instructions, 89 * or a long series of pop and/or near-return instructions. 90 * 91 * http://support.amd.com/us/Processor_TechDocs/41322_10h_Rev_Gd.pdf 92 * http://support.amd.com/us/Processor_TechDocs/44739_12h_Rev_Gd.pdf 93 */ 94 switch (CPUID_TO_FAMILY(cpu_id)) { 95 case 0x10: 96 case 0x12: 97 wrmsr(0xc0011029, rdmsr(0xc0011029) | 1); 98 break; 99 } 100 } 101 102 /* 103 * Initialize special VIA C3/C7 features 104 */ 105 static void 106 init_via(void) 107 { 108 u_int regs[4], val; 109 u_int64_t msreg; 110 111 do_cpuid(0xc0000000, regs); 112 val = regs[0]; 113 if (val >= 0xc0000001) { 114 do_cpuid(0xc0000001, regs); 115 val = regs[3]; 116 } else 117 val = 0; 118 119 /* Enable RNG if present and disabled */ 120 if (val & VIA_CPUID_HAS_RNG) { 121 if (!(val & VIA_CPUID_DO_RNG)) { 122 msreg = rdmsr(0x110B); 123 msreg |= 0x40; 124 wrmsr(0x110B, msreg); 125 } 126 via_feature_rng = VIA_HAS_RNG; 127 } 128 /* Enable AES engine if present and disabled */ 129 if (val & VIA_CPUID_HAS_ACE) { 130 if (!(val & VIA_CPUID_DO_ACE)) { 131 msreg = rdmsr(0x1107); 132 msreg |= (0x01 << 28); 133 wrmsr(0x1107, msreg); 134 } 135 via_feature_xcrypt |= VIA_HAS_AES; 136 } 137 /* Enable ACE2 engine if present and disabled */ 138 if (val & VIA_CPUID_HAS_ACE2) { 139 if (!(val & VIA_CPUID_DO_ACE2)) { 140 msreg = rdmsr(0x1107); 141 msreg |= (0x01 << 28); 142 wrmsr(0x1107, msreg); 143 } 144 via_feature_xcrypt |= VIA_HAS_AESCTR; 145 } 146 /* Enable SHA engine if present and disabled */ 147 if (val & VIA_CPUID_HAS_PHE) { 148 if (!(val & VIA_CPUID_DO_PHE)) { 149 msreg = rdmsr(0x1107); 150 msreg |= (0x01 << 28/**/); 151 wrmsr(0x1107, msreg); 152 } 153 via_feature_xcrypt |= VIA_HAS_SHA; 154 } 155 /* Enable MM engine if present and disabled */ 156 if (val & VIA_CPUID_HAS_PMM) { 157 if (!(val & VIA_CPUID_DO_PMM)) { 158 msreg = rdmsr(0x1107); 159 msreg |= (0x01 << 28/**/); 160 wrmsr(0x1107, msreg); 161 } 162 via_feature_xcrypt |= VIA_HAS_MM; 163 } 164 } 165 166 /* 167 * Initialize CPU control registers 168 */ 169 void 170 initializecpu(void) 171 { 172 uint64_t msr; 173 174 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { 175 load_cr4(rcr4() | CR4_FXSR | CR4_XMM); 176 cpu_fxsr = hw_instruction_sse = 1; 177 } 178 if ((amd_feature & AMDID_NX) != 0) { 179 msr = rdmsr(MSR_EFER) | EFER_NXE; 180 wrmsr(MSR_EFER, msr); 181 pg_nx = PG_NX; 182 } 183 switch (cpu_vendor_id) { 184 case CPU_VENDOR_AMD: 185 init_amd(); 186 break; 187 case CPU_VENDOR_CENTAUR: 188 if (CPUID_TO_FAMILY(cpu_id) == 0x6 && 189 CPUID_TO_MODEL(cpu_id) >= 0xf) 190 init_via(); 191 break; 192 } 193 } 194 195 void 196 initializecpucache() 197 { 198 199 /* 200 * CPUID with %eax = 1, %ebx returns 201 * Bits 15-8: CLFLUSH line size 202 * (Value * 8 = cache line size in bytes) 203 */ 204 if ((cpu_feature & CPUID_CLFSH) != 0) 205 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8; 206 /* 207 * XXXKIB: (temporary) hack to work around traps generated 208 * when CLFLUSHing APIC register window under virtualization 209 * environments. These environments tend to disable the 210 * CPUID_SS feature even though the native CPU supports it. 211 */ 212 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable); 213 if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1) 214 cpu_feature &= ~CPUID_CLFSH; 215 /* 216 * Allow to disable CLFLUSH feature manually by 217 * hw.clflush_disable tunable. 218 */ 219 if (hw_clflush_disable == 1) 220 cpu_feature &= ~CPUID_CLFSH; 221 }
Cache object: f40125fdf8c423a6aaa05795fa0691ab
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