Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/initcpu.c
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1 /*- 2 * Copyright (c) KATO Takenori, 1997, 1998. 3 * 4 * All rights reserved. Unpublished rights reserved under the copyright 5 * laws of Japan. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer as 13 * the first lines of this file unmodified. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD: releng/8.0/sys/amd64/amd64/initcpu.c 198991 2009-11-06 17:09:04Z attilio $"); 32 33 #include "opt_cpu.h" 34 35 #include <sys/param.h> 36 #include <sys/kernel.h> 37 #include <sys/systm.h> 38 #include <sys/sysctl.h> 39 40 #include <machine/cputypes.h> 41 #include <machine/md_var.h> 42 #include <machine/specialreg.h> 43 44 #include <vm/vm.h> 45 #include <vm/pmap.h> 46 47 static int hw_instruction_sse; 48 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 49 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 50 51 int cpu; /* Are we 386, 386sx, 486, etc? */ 52 u_int cpu_feature; /* Feature flags */ 53 u_int cpu_feature2; /* Feature flags */ 54 u_int amd_feature; /* AMD feature flags */ 55 u_int amd_feature2; /* AMD feature flags */ 56 u_int amd_pminfo; /* AMD advanced power management info */ 57 u_int via_feature_rng; /* VIA RNG features */ 58 u_int via_feature_xcrypt; /* VIA ACE features */ 59 u_int cpu_high; /* Highest arg to CPUID */ 60 u_int cpu_exthigh; /* Highest arg to extended CPUID */ 61 u_int cpu_id; /* Stepping ID */ 62 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ 63 u_int cpu_procinfo2; /* Multicore info */ 64 char cpu_vendor[20]; /* CPU Origin code */ 65 u_int cpu_vendor_id; /* CPU vendor ID */ 66 u_int cpu_fxsr; /* SSE enabled */ 67 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ 68 u_int cpu_clflush_line_size = 32; 69 70 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 71 &via_feature_rng, 0, "VIA C3/C7 RNG feature available in CPU"); 72 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 73 &via_feature_xcrypt, 0, "VIA C3/C7 xcrypt feature available in CPU"); 74 75 /* 76 * Initialize special VIA C3/C7 features 77 */ 78 static void 79 init_via(void) 80 { 81 u_int regs[4], val; 82 u_int64_t msreg; 83 84 do_cpuid(0xc0000000, regs); 85 val = regs[0]; 86 if (val >= 0xc0000001) { 87 do_cpuid(0xc0000001, regs); 88 val = regs[3]; 89 } else 90 val = 0; 91 92 /* Enable RNG if present and disabled */ 93 if (val & VIA_CPUID_HAS_RNG) { 94 if (!(val & VIA_CPUID_DO_RNG)) { 95 msreg = rdmsr(0x110B); 96 msreg |= 0x40; 97 wrmsr(0x110B, msreg); 98 } 99 via_feature_rng = VIA_HAS_RNG; 100 } 101 /* Enable AES engine if present and disabled */ 102 if (val & VIA_CPUID_HAS_ACE) { 103 if (!(val & VIA_CPUID_DO_ACE)) { 104 msreg = rdmsr(0x1107); 105 msreg |= (0x01 << 28); 106 wrmsr(0x1107, msreg); 107 } 108 via_feature_xcrypt |= VIA_HAS_AES; 109 } 110 /* Enable ACE2 engine if present and disabled */ 111 if (val & VIA_CPUID_HAS_ACE2) { 112 if (!(val & VIA_CPUID_DO_ACE2)) { 113 msreg = rdmsr(0x1107); 114 msreg |= (0x01 << 28); 115 wrmsr(0x1107, msreg); 116 } 117 via_feature_xcrypt |= VIA_HAS_AESCTR; 118 } 119 /* Enable SHA engine if present and disabled */ 120 if (val & VIA_CPUID_HAS_PHE) { 121 if (!(val & VIA_CPUID_DO_PHE)) { 122 msreg = rdmsr(0x1107); 123 msreg |= (0x01 << 28/**/); 124 wrmsr(0x1107, msreg); 125 } 126 via_feature_xcrypt |= VIA_HAS_SHA; 127 } 128 /* Enable MM engine if present and disabled */ 129 if (val & VIA_CPUID_HAS_PMM) { 130 if (!(val & VIA_CPUID_DO_PMM)) { 131 msreg = rdmsr(0x1107); 132 msreg |= (0x01 << 28/**/); 133 wrmsr(0x1107, msreg); 134 } 135 via_feature_xcrypt |= VIA_HAS_MM; 136 } 137 } 138 139 /* 140 * Initialize CPU control registers 141 */ 142 void 143 initializecpu(void) 144 { 145 uint64_t msr; 146 147 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { 148 load_cr4(rcr4() | CR4_FXSR | CR4_XMM); 149 cpu_fxsr = hw_instruction_sse = 1; 150 } 151 if ((amd_feature & AMDID_NX) != 0) { 152 msr = rdmsr(MSR_EFER) | EFER_NXE; 153 wrmsr(MSR_EFER, msr); 154 pg_nx = PG_NX; 155 } 156 if (cpu_vendor_id == CPU_VENDOR_CENTAUR && 157 CPUID_TO_FAMILY(cpu_id) == 0x6 && 158 CPUID_TO_MODEL(cpu_id) >= 0xf) 159 init_via(); 160 161 /* 162 * CPUID with %eax = 1, %ebx returns 163 * Bits 15-8: CLFLUSH line size 164 * (Value * 8 = cache line size in bytes) 165 */ 166 if ((cpu_feature & CPUID_CLFSH) != 0) 167 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8; 168 /* 169 * XXXKIB: (temporary) hack to work around traps generated when 170 * CLFLUSHing APIC registers window. 171 */ 172 if (cpu_vendor_id == CPU_VENDOR_INTEL && !(cpu_feature & CPUID_SS)) 173 cpu_feature &= ~CPUID_CLFSH; 174 }
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