initcpu.c

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    1 /*-
    2  * Copyright (c) KATO Takenori, 1997, 1998.
    3  * 
    4  * All rights reserved.  Unpublished rights reserved under the copyright
    5  * laws of Japan.
    6  * 
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer as
   13  *    the first lines of this file unmodified.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 
   18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   23  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   27  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   28  */
   29 
   30 #include <sys/cdefs.h>
   31 __FBSDID("$FreeBSD: releng/8.4/sys/amd64/amd64/initcpu.c 239561 2012-08-22 05:38:06Z kib $");
   32 
   33 #include "opt_cpu.h"
   34 
   35 #include <sys/param.h>
   36 #include <sys/kernel.h>
   37 #include <sys/systm.h>
   38 #include <sys/sysctl.h>
   39 
   40 #include <machine/cputypes.h>
   41 #include <machine/md_var.h>
   42 #include <machine/specialreg.h>
   43 
   44 #include <vm/vm.h>
   45 #include <vm/pmap.h>
   46 
   47 static int      hw_instruction_sse;
   48 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
   49     &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
   50 /*
   51  * -1: automatic (default)
   52  *  0: keep enable CLFLUSH
   53  *  1: force disable CLFLUSH
   54  */
   55 static int      hw_clflush_disable = -1;
   56 
   57 int     cpu;                    /* Are we 386, 386sx, 486, etc? */
   58 u_int   cpu_feature;            /* Feature flags */
   59 u_int   cpu_feature2;           /* Feature flags */
   60 u_int   amd_feature;            /* AMD feature flags */
   61 u_int   amd_feature2;           /* AMD feature flags */
   62 u_int   amd_pminfo;             /* AMD advanced power management info */
   63 u_int   via_feature_rng;        /* VIA RNG features */
   64 u_int   via_feature_xcrypt;     /* VIA ACE features */
   65 u_int   cpu_high;               /* Highest arg to CPUID */
   66 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
   67 u_int   cpu_id;                 /* Stepping ID */
   68 u_int   cpu_procinfo;           /* HyperThreading Info / Brand Index / CLFUSH */
   69 u_int   cpu_procinfo2;          /* Multicore info */
   70 char    cpu_vendor[20];         /* CPU Origin code */
   71 u_int   cpu_vendor_id;          /* CPU vendor ID */
   72 u_int   cpu_fxsr;               /* SSE enabled */
   73 u_int   cpu_mxcsr_mask;         /* Valid bits in mxcsr */
   74 u_int   cpu_clflush_line_size = 32;
   75 u_int   cpu_max_ext_state_size;
   76 
   77 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
   78         &via_feature_rng, 0, "VIA C3/C7 RNG feature available in CPU");
   79 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
   80         &via_feature_xcrypt, 0, "VIA C3/C7 xcrypt feature available in CPU");
   81 
   82 static void
   83 init_amd(void)
   84 {
   85 
   86         /*
   87          * Work around Erratum 721 for Family 10h and 12h processors.
   88          * These processors may incorrectly update the stack pointer
   89          * after a long series of push and/or near-call instructions,
   90          * or a long series of pop and/or near-return instructions.
   91          *
   92          * http://support.amd.com/us/Processor_TechDocs/41322_10h_Rev_Gd.pdf
   93          * http://support.amd.com/us/Processor_TechDocs/44739_12h_Rev_Gd.pdf
   94          *
   95          * Hypervisors do not provide access to the errata MSR,
   96          * causing #GP exception on attempt to apply the errata.  The
   97          * MSR write shall be done on host and persist globally
   98          * anyway, so do not try to do it when under virtualization.
   99          */
  100         switch (CPUID_TO_FAMILY(cpu_id)) {
  101         case 0x10:
  102         case 0x12:
  103                 if ((cpu_feature2 & CPUID2_HV) == 0)
  104                         wrmsr(0xc0011029, rdmsr(0xc0011029) | 1);
  105                 break;
  106         }
  107 }
  108 
  109 /*
  110  * Initialize special VIA C3/C7 features
  111  */
  112 static void
  113 init_via(void)
  114 {
  115         u_int regs[4], val;
  116         u_int64_t msreg;
  117 
  118         do_cpuid(0xc0000000, regs);
  119         val = regs[0];
  120         if (val >= 0xc0000001) {
  121                 do_cpuid(0xc0000001, regs);
  122                 val = regs[3];
  123         } else
  124                 val = 0;
  125 
  126         /* Enable RNG if present and disabled */
  127         if (val & VIA_CPUID_HAS_RNG) {
  128                 if (!(val & VIA_CPUID_DO_RNG)) {
  129                         msreg = rdmsr(0x110B);
  130                         msreg |= 0x40;
  131                         wrmsr(0x110B, msreg);
  132                 }
  133                 via_feature_rng = VIA_HAS_RNG;
  134         }
  135         /* Enable AES engine if present and disabled */
  136         if (val & VIA_CPUID_HAS_ACE) {
  137                 if (!(val & VIA_CPUID_DO_ACE)) {
  138                         msreg = rdmsr(0x1107);
  139                         msreg |= (0x01 << 28);
  140                         wrmsr(0x1107, msreg);
  141                 }
  142                 via_feature_xcrypt |= VIA_HAS_AES;
  143         }
  144         /* Enable ACE2 engine if present and disabled */
  145         if (val & VIA_CPUID_HAS_ACE2) {
  146                 if (!(val & VIA_CPUID_DO_ACE2)) {
  147                         msreg = rdmsr(0x1107);
  148                         msreg |= (0x01 << 28);
  149                         wrmsr(0x1107, msreg);
  150                 }
  151                 via_feature_xcrypt |= VIA_HAS_AESCTR;
  152         }
  153         /* Enable SHA engine if present and disabled */
  154         if (val & VIA_CPUID_HAS_PHE) {
  155                 if (!(val & VIA_CPUID_DO_PHE)) {
  156                         msreg = rdmsr(0x1107);
  157                         msreg |= (0x01 << 28/**/);
  158                         wrmsr(0x1107, msreg);
  159                 }
  160                 via_feature_xcrypt |= VIA_HAS_SHA;
  161         }
  162         /* Enable MM engine if present and disabled */
  163         if (val & VIA_CPUID_HAS_PMM) {
  164                 if (!(val & VIA_CPUID_DO_PMM)) {
  165                         msreg = rdmsr(0x1107);
  166                         msreg |= (0x01 << 28/**/);
  167                         wrmsr(0x1107, msreg);
  168                 }
  169                 via_feature_xcrypt |= VIA_HAS_MM;
  170         }
  171 }
  172 
  173 /*
  174  * Initialize CPU control registers
  175  */
  176 void
  177 initializecpu(void)
  178 {
  179         uint64_t msr;
  180 
  181         if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
  182                 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
  183                 cpu_fxsr = hw_instruction_sse = 1;
  184         }
  185         if ((amd_feature & AMDID_NX) != 0) {
  186                 msr = rdmsr(MSR_EFER) | EFER_NXE;
  187                 wrmsr(MSR_EFER, msr);
  188                 pg_nx = PG_NX;
  189         }
  190         switch (cpu_vendor_id) {
  191         case CPU_VENDOR_AMD:
  192                 init_amd();
  193                 break;
  194         case CPU_VENDOR_CENTAUR:
  195                 if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
  196                     CPUID_TO_MODEL(cpu_id) >= 0xf)
  197                         init_via();
  198                 break;
  199         }
  200 }
  201 
  202 void
  203 initializecpucache()
  204 {
  205 
  206         /*
  207          * CPUID with %eax = 1, %ebx returns
  208          * Bits 15-8: CLFLUSH line size
  209          *      (Value * 8 = cache line size in bytes)
  210          */
  211         if ((cpu_feature & CPUID_CLFSH) != 0)
  212                 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8;
  213         /*
  214          * XXXKIB: (temporary) hack to work around traps generated
  215          * when CLFLUSHing APIC register window under virtualization
  216          * environments.  These environments tend to disable the
  217          * CPUID_SS feature even though the native CPU supports it.
  218          */
  219         TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
  220         if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1)
  221                 cpu_feature &= ~CPUID_CLFSH;
  222         /*
  223          * Allow to disable CLFLUSH feature manually by
  224          * hw.clflush_disable tunable.
  225          */
  226         if (hw_clflush_disable == 1)
  227                 cpu_feature &= ~CPUID_CLFSH;
  228 }

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FreeBSD/Linux Kernel Cross Reference sys/amd64/amd64/initcpu.c

FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/initcpu.c