1 /*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD$
30 */
31
32 /*
33 * Machine dependent interrupt code for amd64. For amd64, we have to
34 * deal with different PICs. Thus, we use the passed in vector to lookup
35 * an interrupt source associated with that vector. The interrupt source
36 * describes which PIC the source belongs to and includes methods to handle
37 * that source.
38 */
39
40 #include "opt_atpic.h"
41 #include "opt_ddb.h"
42
43 #include <sys/param.h>
44 #include <sys/bus.h>
45 #include <sys/interrupt.h>
46 #include <sys/ktr.h>
47 #include <sys/kernel.h>
48 #include <sys/lock.h>
49 #include <sys/mutex.h>
50 #include <sys/proc.h>
51 #include <sys/smp.h>
52 #include <sys/syslog.h>
53 #include <sys/systm.h>
54 #include <sys/sx.h>
55 #include <machine/clock.h>
56 #include <machine/intr_machdep.h>
57 #include <machine/smp.h>
58 #ifdef DDB
59 #include <ddb/ddb.h>
60 #endif
61
62 #ifndef DEV_ATPIC
63 #include <machine/segments.h>
64 #include <machine/frame.h>
65 #include <dev/ic/i8259.h>
66 #include <amd64/isa/icu.h>
67 #include <amd64/isa/isa.h>
68 #endif
69
70 #define MAX_STRAY_LOG 5
71
72 typedef void (*mask_fn)(void *);
73
74 static int intrcnt_index;
75 static struct intsrc *interrupt_sources[NUM_IO_INTS];
76 static struct sx intr_table_lock;
77 static struct mtx intrcnt_lock;
78 static STAILQ_HEAD(, pic) pics;
79
80 #ifdef SMP
81 static int assign_cpu;
82
83 static void intr_assign_next_cpu(struct intsrc *isrc);
84 #endif
85
86 static int intr_assign_cpu(void *arg, u_char cpu);
87 static void intr_disable_src(void *arg);
88 static void intr_init(void *__dummy);
89 static int intr_pic_registered(struct pic *pic);
90 static void intrcnt_setname(const char *name, int index);
91 static void intrcnt_updatename(struct intsrc *is);
92 static void intrcnt_register(struct intsrc *is);
93
94 static int
95 intr_pic_registered(struct pic *pic)
96 {
97 struct pic *p;
98
99 STAILQ_FOREACH(p, &pics, pics) {
100 if (p == pic)
101 return (1);
102 }
103 return (0);
104 }
105
106 /*
107 * Register a new interrupt controller (PIC). This is to support suspend
108 * and resume where we suspend/resume controllers rather than individual
109 * sources. This also allows controllers with no active sources (such as
110 * 8259As in a system using the APICs) to participate in suspend and resume.
111 */
112 int
113 intr_register_pic(struct pic *pic)
114 {
115 int error;
116
117 sx_xlock(&intr_table_lock);
118 if (intr_pic_registered(pic))
119 error = EBUSY;
120 else {
121 STAILQ_INSERT_TAIL(&pics, pic, pics);
122 error = 0;
123 }
124 sx_xunlock(&intr_table_lock);
125 return (error);
126 }
127
128 /*
129 * Register a new interrupt source with the global interrupt system.
130 * The global interrupts need to be disabled when this function is
131 * called.
132 */
133 int
134 intr_register_source(struct intsrc *isrc)
135 {
136 int error, vector;
137
138 KASSERT(intr_pic_registered(isrc->is_pic), ("unregistered PIC"));
139 vector = isrc->is_pic->pic_vector(isrc);
140 if (interrupt_sources[vector] != NULL)
141 return (EEXIST);
142 error = intr_event_create(&isrc->is_event, isrc, 0, vector,
143 intr_disable_src, (mask_fn)isrc->is_pic->pic_enable_source,
144 (mask_fn)isrc->is_pic->pic_eoi_source, intr_assign_cpu, "irq%d:",
145 vector);
146 if (error)
147 return (error);
148 sx_xlock(&intr_table_lock);
149 if (interrupt_sources[vector] != NULL) {
150 sx_xunlock(&intr_table_lock);
151 intr_event_destroy(isrc->is_event);
152 return (EEXIST);
153 }
154 intrcnt_register(isrc);
155 interrupt_sources[vector] = isrc;
156 isrc->is_handlers = 0;
157 sx_xunlock(&intr_table_lock);
158 return (0);
159 }
160
161 struct intsrc *
162 intr_lookup_source(int vector)
163 {
164
165 return (interrupt_sources[vector]);
166 }
167
168 int
169 intr_add_handler(const char *name, int vector, driver_filter_t filter,
170 driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep)
171 {
172 struct intsrc *isrc;
173 int error;
174
175 isrc = intr_lookup_source(vector);
176 if (isrc == NULL)
177 return (EINVAL);
178 error = intr_event_add_handler(isrc->is_event, name, filter, handler,
179 arg, intr_priority(flags), flags, cookiep);
180 if (error == 0) {
181 sx_xlock(&intr_table_lock);
182 intrcnt_updatename(isrc);
183 isrc->is_handlers++;
184 if (isrc->is_handlers == 1) {
185 #ifdef SMP
186 if (assign_cpu)
187 intr_assign_next_cpu(isrc);
188 #endif
189 isrc->is_pic->pic_enable_intr(isrc);
190 isrc->is_pic->pic_enable_source(isrc);
191 }
192 sx_xunlock(&intr_table_lock);
193 }
194 return (error);
195 }
196
197 int
198 intr_remove_handler(void *cookie)
199 {
200 struct intsrc *isrc;
201 int error;
202
203 isrc = intr_handler_source(cookie);
204 error = intr_event_remove_handler(cookie);
205 if (error == 0) {
206 sx_xlock(&intr_table_lock);
207 isrc->is_handlers--;
208 if (isrc->is_handlers == 0) {
209 isrc->is_pic->pic_disable_source(isrc, PIC_NO_EOI);
210 isrc->is_pic->pic_disable_intr(isrc);
211 }
212 intrcnt_updatename(isrc);
213 sx_xunlock(&intr_table_lock);
214 }
215 return (error);
216 }
217
218 int
219 intr_config_intr(int vector, enum intr_trigger trig, enum intr_polarity pol)
220 {
221 struct intsrc *isrc;
222
223 isrc = intr_lookup_source(vector);
224 if (isrc == NULL)
225 return (EINVAL);
226 return (isrc->is_pic->pic_config_intr(isrc, trig, pol));
227 }
228
229 static void
230 intr_disable_src(void *arg)
231 {
232 struct intsrc *isrc;
233
234 isrc = arg;
235 isrc->is_pic->pic_disable_source(isrc, PIC_EOI);
236 }
237
238 void
239 intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame)
240 {
241 struct intr_event *ie;
242 int vector;
243
244 /*
245 * We count software interrupts when we process them. The
246 * code here follows previous practice, but there's an
247 * argument for counting hardware interrupts when they're
248 * processed too.
249 */
250 (*isrc->is_count)++;
251 PCPU_INC(cnt.v_intr);
252
253 ie = isrc->is_event;
254
255 /*
256 * XXX: We assume that IRQ 0 is only used for the ISA timer
257 * device (clk).
258 */
259 vector = isrc->is_pic->pic_vector(isrc);
260 if (vector == 0)
261 clkintr_pending = 1;
262
263 /*
264 * For stray interrupts, mask and EOI the source, bump the
265 * stray count, and log the condition.
266 */
267 if (intr_event_handle(ie, frame) != 0) {
268 isrc->is_pic->pic_disable_source(isrc, PIC_EOI);
269 (*isrc->is_straycount)++;
270 if (*isrc->is_straycount < MAX_STRAY_LOG)
271 log(LOG_ERR, "stray irq%d\n", vector);
272 else if (*isrc->is_straycount == MAX_STRAY_LOG)
273 log(LOG_CRIT,
274 "too many stray irq %d's: not logging anymore\n",
275 vector);
276 }
277 }
278
279 void
280 intr_resume(void)
281 {
282 struct pic *pic;
283
284 #ifndef DEV_ATPIC
285 atpic_reset();
286 #endif
287 sx_xlock(&intr_table_lock);
288 STAILQ_FOREACH(pic, &pics, pics) {
289 if (pic->pic_resume != NULL)
290 pic->pic_resume(pic);
291 }
292 sx_xunlock(&intr_table_lock);
293 }
294
295 void
296 intr_suspend(void)
297 {
298 struct pic *pic;
299
300 sx_xlock(&intr_table_lock);
301 STAILQ_FOREACH(pic, &pics, pics) {
302 if (pic->pic_suspend != NULL)
303 pic->pic_suspend(pic);
304 }
305 sx_xunlock(&intr_table_lock);
306 }
307
308 static int
309 intr_assign_cpu(void *arg, u_char cpu)
310 {
311 #ifdef SMP
312 struct intsrc *isrc;
313
314 /*
315 * Don't do anything during early boot. We will pick up the
316 * assignment once the APs are started.
317 */
318 if (assign_cpu && cpu != NOCPU) {
319 isrc = arg;
320 sx_xlock(&intr_table_lock);
321 isrc->is_pic->pic_assign_cpu(isrc, cpu_apic_ids[cpu]);
322 sx_xunlock(&intr_table_lock);
323 }
324 return (0);
325 #else
326 return (EOPNOTSUPP);
327 #endif
328 }
329
330 static void
331 intrcnt_setname(const char *name, int index)
332 {
333
334 snprintf(intrnames + (MAXCOMLEN + 1) * index, MAXCOMLEN + 1, "%-*s",
335 MAXCOMLEN, name);
336 }
337
338 static void
339 intrcnt_updatename(struct intsrc *is)
340 {
341
342 intrcnt_setname(is->is_event->ie_fullname, is->is_index);
343 }
344
345 static void
346 intrcnt_register(struct intsrc *is)
347 {
348 char straystr[MAXCOMLEN + 1];
349
350 KASSERT(is->is_event != NULL, ("%s: isrc with no event", __func__));
351 mtx_lock_spin(&intrcnt_lock);
352 is->is_index = intrcnt_index;
353 intrcnt_index += 2;
354 snprintf(straystr, MAXCOMLEN + 1, "stray irq%d",
355 is->is_pic->pic_vector(is));
356 intrcnt_updatename(is);
357 is->is_count = &intrcnt[is->is_index];
358 intrcnt_setname(straystr, is->is_index + 1);
359 is->is_straycount = &intrcnt[is->is_index + 1];
360 mtx_unlock_spin(&intrcnt_lock);
361 }
362
363 void
364 intrcnt_add(const char *name, u_long **countp)
365 {
366
367 mtx_lock_spin(&intrcnt_lock);
368 *countp = &intrcnt[intrcnt_index];
369 intrcnt_setname(name, intrcnt_index);
370 intrcnt_index++;
371 mtx_unlock_spin(&intrcnt_lock);
372 }
373
374 static void
375 intr_init(void *dummy __unused)
376 {
377
378 intrcnt_setname("???", 0);
379 intrcnt_index = 1;
380 STAILQ_INIT(&pics);
381 sx_init(&intr_table_lock, "intr sources");
382 mtx_init(&intrcnt_lock, "intrcnt", NULL, MTX_SPIN);
383 }
384 SYSINIT(intr_init, SI_SUB_INTR, SI_ORDER_FIRST, intr_init, NULL);
385
386 #ifndef DEV_ATPIC
387 /* Initialize the two 8259A's to a known-good shutdown state. */
388 void
389 atpic_reset(void)
390 {
391
392 outb(IO_ICU1, ICW1_RESET | ICW1_IC4);
393 outb(IO_ICU1 + ICU_IMR_OFFSET, IDT_IO_INTS);
394 outb(IO_ICU1 + ICU_IMR_OFFSET, 1 << 2);
395 outb(IO_ICU1 + ICU_IMR_OFFSET, ICW4_8086);
396 outb(IO_ICU1 + ICU_IMR_OFFSET, 0xff);
397 outb(IO_ICU1, OCW3_SEL | OCW3_RR);
398
399 outb(IO_ICU2, ICW1_RESET | ICW1_IC4);
400 outb(IO_ICU2 + ICU_IMR_OFFSET, IDT_IO_INTS + 8);
401 outb(IO_ICU2 + ICU_IMR_OFFSET, 2);
402 outb(IO_ICU2 + ICU_IMR_OFFSET, ICW4_8086);
403 outb(IO_ICU2 + ICU_IMR_OFFSET, 0xff);
404 outb(IO_ICU2, OCW3_SEL | OCW3_RR);
405 }
406 #endif
407
408 /* Add a description to an active interrupt handler. */
409 int
410 intr_describe(u_int vector, void *ih, const char *descr)
411 {
412 struct intsrc *isrc;
413 int error;
414
415 isrc = intr_lookup_source(vector);
416 if (isrc == NULL)
417 return (EINVAL);
418 error = intr_event_describe_handler(isrc->is_event, ih, descr);
419 if (error)
420 return (error);
421 intrcnt_updatename(isrc);
422 return (0);
423 }
424
425 #ifdef DDB
426 /*
427 * Dump data about interrupt handlers
428 */
429 DB_SHOW_COMMAND(irqs, db_show_irqs)
430 {
431 struct intsrc **isrc;
432 int i, verbose;
433
434 if (strcmp(modif, "v") == 0)
435 verbose = 1;
436 else
437 verbose = 0;
438 isrc = interrupt_sources;
439 for (i = 0; i < NUM_IO_INTS && !db_pager_quit; i++, isrc++)
440 if (*isrc != NULL)
441 db_dump_intr_event((*isrc)->is_event, verbose);
442 }
443 #endif
444
445 #ifdef SMP
446 /*
447 * Support for balancing interrupt sources across CPUs. For now we just
448 * allocate CPUs round-robin.
449 */
450
451 /* The BSP is always a valid target. */
452 static cpumask_t intr_cpus = (1 << 0);
453 static int current_cpu;
454
455 static void
456 intr_assign_next_cpu(struct intsrc *isrc)
457 {
458
459 /*
460 * Assign this source to a local APIC in a round-robin fashion.
461 */
462 isrc->is_pic->pic_assign_cpu(isrc, cpu_apic_ids[current_cpu]);
463 do {
464 current_cpu++;
465 if (current_cpu > mp_maxid)
466 current_cpu = 0;
467 } while (!(intr_cpus & (1 << current_cpu)));
468 }
469
470 /* Attempt to bind the specified IRQ to the specified CPU. */
471 int
472 intr_bind(u_int vector, u_char cpu)
473 {
474 struct intsrc *isrc;
475
476 isrc = intr_lookup_source(vector);
477 if (isrc == NULL)
478 return (EINVAL);
479 return (intr_event_bind(isrc->is_event, cpu));
480 }
481
482 /*
483 * Add a CPU to our mask of valid CPUs that can be destinations of
484 * interrupts.
485 */
486 void
487 intr_add_cpu(u_int cpu)
488 {
489
490 if (cpu >= MAXCPU)
491 panic("%s: Invalid CPU ID", __func__);
492 if (bootverbose)
493 printf("INTR: Adding local APIC %d as a target\n",
494 cpu_apic_ids[cpu]);
495
496 intr_cpus |= (1 << cpu);
497 }
498
499 /*
500 * Distribute all the interrupt sources among the available CPUs once the
501 * AP's have been launched.
502 */
503 static void
504 intr_shuffle_irqs(void *arg __unused)
505 {
506 struct intsrc *isrc;
507 int i;
508
509 /* Don't bother on UP. */
510 if (mp_ncpus == 1)
511 return;
512
513 /* Round-robin assign a CPU to each enabled source. */
514 sx_xlock(&intr_table_lock);
515 assign_cpu = 1;
516 for (i = 0; i < NUM_IO_INTS; i++) {
517 isrc = interrupt_sources[i];
518 if (isrc != NULL && isrc->is_handlers > 0) {
519 /*
520 * If this event is already bound to a CPU,
521 * then assign the source to that CPU instead
522 * of picking one via round-robin.
523 */
524 if (isrc->is_event->ie_cpu != NOCPU)
525 isrc->is_pic->pic_assign_cpu(isrc,
526 cpu_apic_ids[isrc->is_event->ie_cpu]);
527 else
528 intr_assign_next_cpu(isrc);
529 }
530 }
531 sx_xunlock(&intr_table_lock);
532 }
533 SYSINIT(intr_shuffle_irqs, SI_SUB_SMP, SI_ORDER_SECOND, intr_shuffle_irqs,
534 NULL);
535 #endif
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