The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/intr_machdep.c

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    1 /*-
    2  * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. Neither the name of the author nor the names of any co-contributors
   14  *    may be used to endorse or promote products derived from this software
   15  *    without specific prior written permission.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  * $FreeBSD: releng/8.3/sys/amd64/amd64/intr_machdep.c 214788 2010-11-04 17:19:16Z jhb $
   30  */
   31 
   32 /*
   33  * Machine dependent interrupt code for amd64.  For amd64, we have to
   34  * deal with different PICs.  Thus, we use the passed in vector to lookup
   35  * an interrupt source associated with that vector.  The interrupt source
   36  * describes which PIC the source belongs to and includes methods to handle
   37  * that source.
   38  */
   39 
   40 #include "opt_atpic.h"
   41 #include "opt_ddb.h"
   42 
   43 #include <sys/param.h>
   44 #include <sys/bus.h>
   45 #include <sys/interrupt.h>
   46 #include <sys/ktr.h>
   47 #include <sys/kernel.h>
   48 #include <sys/lock.h>
   49 #include <sys/mutex.h>
   50 #include <sys/proc.h>
   51 #include <sys/smp.h>
   52 #include <sys/syslog.h>
   53 #include <sys/systm.h>
   54 #include <machine/clock.h>
   55 #include <machine/intr_machdep.h>
   56 #include <machine/smp.h>
   57 #ifdef DDB
   58 #include <ddb/ddb.h>
   59 #endif
   60 
   61 #ifndef DEV_ATPIC
   62 #include <machine/segments.h>
   63 #include <machine/frame.h>
   64 #include <dev/ic/i8259.h>
   65 #include <amd64/isa/icu.h>
   66 #include <amd64/isa/isa.h>
   67 #endif
   68 
   69 #define MAX_STRAY_LOG   5
   70 
   71 typedef void (*mask_fn)(void *);
   72 
   73 static int intrcnt_index;
   74 static struct intsrc *interrupt_sources[NUM_IO_INTS];
   75 static struct mtx intr_table_lock;
   76 static struct mtx intrcnt_lock;
   77 static STAILQ_HEAD(, pic) pics;
   78 
   79 #ifdef SMP
   80 static int assign_cpu;
   81 #endif
   82 
   83 static int      intr_assign_cpu(void *arg, u_char cpu);
   84 static void     intr_disable_src(void *arg);
   85 static void     intr_init(void *__dummy);
   86 static int      intr_pic_registered(struct pic *pic);
   87 static void     intrcnt_setname(const char *name, int index);
   88 static void     intrcnt_updatename(struct intsrc *is);
   89 static void     intrcnt_register(struct intsrc *is);
   90 
   91 static int
   92 intr_pic_registered(struct pic *pic)
   93 {
   94         struct pic *p;
   95 
   96         STAILQ_FOREACH(p, &pics, pics) {
   97                 if (p == pic)
   98                         return (1);
   99         }
  100         return (0);
  101 }
  102 
  103 /*
  104  * Register a new interrupt controller (PIC).  This is to support suspend
  105  * and resume where we suspend/resume controllers rather than individual
  106  * sources.  This also allows controllers with no active sources (such as
  107  * 8259As in a system using the APICs) to participate in suspend and resume.
  108  */
  109 int
  110 intr_register_pic(struct pic *pic)
  111 {
  112         int error;
  113 
  114         mtx_lock(&intr_table_lock);
  115         if (intr_pic_registered(pic))
  116                 error = EBUSY;
  117         else {
  118                 STAILQ_INSERT_TAIL(&pics, pic, pics);
  119                 error = 0;
  120         }
  121         mtx_unlock(&intr_table_lock);
  122         return (error);
  123 }
  124 
  125 /*
  126  * Register a new interrupt source with the global interrupt system.
  127  * The global interrupts need to be disabled when this function is
  128  * called.
  129  */
  130 int
  131 intr_register_source(struct intsrc *isrc)
  132 {
  133         int error, vector;
  134 
  135         KASSERT(intr_pic_registered(isrc->is_pic), ("unregistered PIC"));
  136         vector = isrc->is_pic->pic_vector(isrc);
  137         if (interrupt_sources[vector] != NULL)
  138                 return (EEXIST);
  139         error = intr_event_create(&isrc->is_event, isrc, 0, vector,
  140             intr_disable_src, (mask_fn)isrc->is_pic->pic_enable_source,
  141             (mask_fn)isrc->is_pic->pic_eoi_source, intr_assign_cpu, "irq%d:",
  142             vector);
  143         if (error)
  144                 return (error);
  145         mtx_lock(&intr_table_lock);
  146         if (interrupt_sources[vector] != NULL) {
  147                 mtx_unlock(&intr_table_lock);
  148                 intr_event_destroy(isrc->is_event);
  149                 return (EEXIST);
  150         }
  151         intrcnt_register(isrc);
  152         interrupt_sources[vector] = isrc;
  153         isrc->is_handlers = 0;
  154         mtx_unlock(&intr_table_lock);
  155         return (0);
  156 }
  157 
  158 struct intsrc *
  159 intr_lookup_source(int vector)
  160 {
  161 
  162         return (interrupt_sources[vector]);
  163 }
  164 
  165 int
  166 intr_add_handler(const char *name, int vector, driver_filter_t filter,
  167     driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep)
  168 {
  169         struct intsrc *isrc;
  170         int error;
  171 
  172         isrc = intr_lookup_source(vector);
  173         if (isrc == NULL)
  174                 return (EINVAL);
  175         error = intr_event_add_handler(isrc->is_event, name, filter, handler,
  176             arg, intr_priority(flags), flags, cookiep);
  177         if (error == 0) {
  178                 mtx_lock(&intr_table_lock);
  179                 intrcnt_updatename(isrc);
  180                 isrc->is_handlers++;
  181                 if (isrc->is_handlers == 1) {
  182                         isrc->is_pic->pic_enable_intr(isrc);
  183                         isrc->is_pic->pic_enable_source(isrc);
  184                 }
  185                 mtx_unlock(&intr_table_lock);
  186         }
  187         return (error);
  188 }
  189 
  190 int
  191 intr_remove_handler(void *cookie)
  192 {
  193         struct intsrc *isrc;
  194         int error;
  195 
  196         isrc = intr_handler_source(cookie);
  197         error = intr_event_remove_handler(cookie);
  198         if (error == 0) {
  199                 mtx_lock(&intr_table_lock);
  200                 isrc->is_handlers--;
  201                 if (isrc->is_handlers == 0) {
  202                         isrc->is_pic->pic_disable_source(isrc, PIC_NO_EOI);
  203                         isrc->is_pic->pic_disable_intr(isrc);
  204                 }
  205                 intrcnt_updatename(isrc);
  206                 mtx_unlock(&intr_table_lock);
  207         }
  208         return (error);
  209 }
  210 
  211 int
  212 intr_config_intr(int vector, enum intr_trigger trig, enum intr_polarity pol)
  213 {
  214         struct intsrc *isrc;
  215 
  216         isrc = intr_lookup_source(vector);
  217         if (isrc == NULL)
  218                 return (EINVAL);
  219         return (isrc->is_pic->pic_config_intr(isrc, trig, pol));
  220 }
  221 
  222 static void
  223 intr_disable_src(void *arg)
  224 {
  225         struct intsrc *isrc;
  226 
  227         isrc = arg;
  228         isrc->is_pic->pic_disable_source(isrc, PIC_EOI);
  229 }
  230 
  231 void
  232 intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame)
  233 {
  234         struct intr_event *ie;
  235         int vector;
  236 
  237         /*
  238          * We count software interrupts when we process them.  The
  239          * code here follows previous practice, but there's an
  240          * argument for counting hardware interrupts when they're
  241          * processed too.
  242          */
  243         (*isrc->is_count)++;
  244         PCPU_INC(cnt.v_intr);
  245 
  246         ie = isrc->is_event;
  247 
  248         /*
  249          * XXX: We assume that IRQ 0 is only used for the ISA timer
  250          * device (clk).
  251          */
  252         vector = isrc->is_pic->pic_vector(isrc);
  253         if (vector == 0)
  254                 clkintr_pending = 1;
  255 
  256         /*
  257          * For stray interrupts, mask and EOI the source, bump the
  258          * stray count, and log the condition.
  259          */
  260         if (intr_event_handle(ie, frame) != 0) {
  261                 isrc->is_pic->pic_disable_source(isrc, PIC_EOI);
  262                 (*isrc->is_straycount)++;
  263                 if (*isrc->is_straycount < MAX_STRAY_LOG)
  264                         log(LOG_ERR, "stray irq%d\n", vector);
  265                 else if (*isrc->is_straycount == MAX_STRAY_LOG)
  266                         log(LOG_CRIT,
  267                             "too many stray irq %d's: not logging anymore\n",
  268                             vector);
  269         }
  270 }
  271 
  272 void
  273 intr_resume(void)
  274 {
  275         struct pic *pic;
  276 
  277 #ifndef DEV_ATPIC
  278         atpic_reset();
  279 #endif
  280         mtx_lock(&intr_table_lock);
  281         STAILQ_FOREACH(pic, &pics, pics) {
  282                 if (pic->pic_resume != NULL)
  283                         pic->pic_resume(pic);
  284         }
  285         mtx_unlock(&intr_table_lock);
  286 }
  287 
  288 void
  289 intr_suspend(void)
  290 {
  291         struct pic *pic;
  292 
  293         mtx_lock(&intr_table_lock);
  294         STAILQ_FOREACH(pic, &pics, pics) {
  295                 if (pic->pic_suspend != NULL)
  296                         pic->pic_suspend(pic);
  297         }
  298         mtx_unlock(&intr_table_lock);
  299 }
  300 
  301 static int
  302 intr_assign_cpu(void *arg, u_char cpu)
  303 {
  304 #ifdef SMP
  305         struct intsrc *isrc;
  306         int error;
  307 
  308         /*
  309          * Don't do anything during early boot.  We will pick up the
  310          * assignment once the APs are started.
  311          */
  312         if (assign_cpu && cpu != NOCPU) {
  313                 isrc = arg;
  314                 mtx_lock(&intr_table_lock);
  315                 error = isrc->is_pic->pic_assign_cpu(isrc, cpu_apic_ids[cpu]);
  316                 mtx_unlock(&intr_table_lock);
  317         } else
  318                 error = 0;
  319         return (error);
  320 #else
  321         return (EOPNOTSUPP);
  322 #endif
  323 }
  324 
  325 static void
  326 intrcnt_setname(const char *name, int index)
  327 {
  328 
  329         snprintf(intrnames + (MAXCOMLEN + 1) * index, MAXCOMLEN + 1, "%-*s",
  330             MAXCOMLEN, name);
  331 }
  332 
  333 static void
  334 intrcnt_updatename(struct intsrc *is)
  335 {
  336 
  337         intrcnt_setname(is->is_event->ie_fullname, is->is_index);
  338 }
  339 
  340 static void
  341 intrcnt_register(struct intsrc *is)
  342 {
  343         char straystr[MAXCOMLEN + 1];
  344 
  345         KASSERT(is->is_event != NULL, ("%s: isrc with no event", __func__));
  346         mtx_lock_spin(&intrcnt_lock);
  347         is->is_index = intrcnt_index;
  348         intrcnt_index += 2;
  349         snprintf(straystr, MAXCOMLEN + 1, "stray irq%d",
  350             is->is_pic->pic_vector(is));
  351         intrcnt_updatename(is);
  352         is->is_count = &intrcnt[is->is_index];
  353         intrcnt_setname(straystr, is->is_index + 1);
  354         is->is_straycount = &intrcnt[is->is_index + 1];
  355         mtx_unlock_spin(&intrcnt_lock);
  356 }
  357 
  358 void
  359 intrcnt_add(const char *name, u_long **countp)
  360 {
  361 
  362         mtx_lock_spin(&intrcnt_lock);
  363         *countp = &intrcnt[intrcnt_index];
  364         intrcnt_setname(name, intrcnt_index);
  365         intrcnt_index++;
  366         mtx_unlock_spin(&intrcnt_lock);
  367 }
  368 
  369 static void
  370 intr_init(void *dummy __unused)
  371 {
  372 
  373         intrcnt_setname("???", 0);
  374         intrcnt_index = 1;
  375         STAILQ_INIT(&pics);
  376         mtx_init(&intr_table_lock, "intr sources", NULL, MTX_DEF);
  377         mtx_init(&intrcnt_lock, "intrcnt", NULL, MTX_SPIN);
  378 }
  379 SYSINIT(intr_init, SI_SUB_INTR, SI_ORDER_FIRST, intr_init, NULL);
  380 
  381 #ifndef DEV_ATPIC
  382 /* Initialize the two 8259A's to a known-good shutdown state. */
  383 void
  384 atpic_reset(void)
  385 {
  386 
  387         outb(IO_ICU1, ICW1_RESET | ICW1_IC4);
  388         outb(IO_ICU1 + ICU_IMR_OFFSET, IDT_IO_INTS);
  389         outb(IO_ICU1 + ICU_IMR_OFFSET, 1 << 2);
  390         outb(IO_ICU1 + ICU_IMR_OFFSET, ICW4_8086);
  391         outb(IO_ICU1 + ICU_IMR_OFFSET, 0xff);
  392         outb(IO_ICU1, OCW3_SEL | OCW3_RR);
  393 
  394         outb(IO_ICU2, ICW1_RESET | ICW1_IC4);
  395         outb(IO_ICU2 + ICU_IMR_OFFSET, IDT_IO_INTS + 8);
  396         outb(IO_ICU2 + ICU_IMR_OFFSET, 2);
  397         outb(IO_ICU2 + ICU_IMR_OFFSET, ICW4_8086);
  398         outb(IO_ICU2 + ICU_IMR_OFFSET, 0xff);
  399         outb(IO_ICU2, OCW3_SEL | OCW3_RR);
  400 }
  401 #endif
  402 
  403 /* Add a description to an active interrupt handler. */
  404 int
  405 intr_describe(u_int vector, void *ih, const char *descr)
  406 {
  407         struct intsrc *isrc;
  408         int error;
  409 
  410         isrc = intr_lookup_source(vector);
  411         if (isrc == NULL)
  412                 return (EINVAL);
  413         error = intr_event_describe_handler(isrc->is_event, ih, descr);
  414         if (error)
  415                 return (error);
  416         intrcnt_updatename(isrc);
  417         return (0);
  418 }
  419 
  420 #ifdef DDB
  421 /*
  422  * Dump data about interrupt handlers
  423  */
  424 DB_SHOW_COMMAND(irqs, db_show_irqs)
  425 {
  426         struct intsrc **isrc;
  427         int i, verbose;
  428 
  429         if (strcmp(modif, "v") == 0)
  430                 verbose = 1;
  431         else
  432                 verbose = 0;
  433         isrc = interrupt_sources;
  434         for (i = 0; i < NUM_IO_INTS && !db_pager_quit; i++, isrc++)
  435                 if (*isrc != NULL)
  436                         db_dump_intr_event((*isrc)->is_event, verbose);
  437 }
  438 #endif
  439 
  440 #ifdef SMP
  441 /*
  442  * Support for balancing interrupt sources across CPUs.  For now we just
  443  * allocate CPUs round-robin.
  444  */
  445 
  446 /* The BSP is always a valid target. */
  447 static cpumask_t intr_cpus = (1 << 0);
  448 static int current_cpu;
  449 
  450 /*
  451  * Return the CPU that the next interrupt source should use.  For now
  452  * this just returns the next local APIC according to round-robin.
  453  */
  454 u_int
  455 intr_next_cpu(void)
  456 {
  457         u_int apic_id;
  458 
  459         /* Leave all interrupts on the BSP during boot. */
  460         if (!assign_cpu)
  461                 return (PCPU_GET(apic_id));
  462 
  463         mtx_lock_spin(&icu_lock);
  464         apic_id = cpu_apic_ids[current_cpu];
  465         do {
  466                 current_cpu++;
  467                 if (current_cpu > mp_maxid)
  468                         current_cpu = 0;
  469         } while (!(intr_cpus & (1 << current_cpu)));
  470         mtx_unlock_spin(&icu_lock);
  471         return (apic_id);
  472 }
  473 
  474 /* Attempt to bind the specified IRQ to the specified CPU. */
  475 int
  476 intr_bind(u_int vector, u_char cpu)
  477 {
  478         struct intsrc *isrc;
  479 
  480         isrc = intr_lookup_source(vector);
  481         if (isrc == NULL)
  482                 return (EINVAL);
  483         return (intr_event_bind(isrc->is_event, cpu));
  484 }
  485 
  486 /*
  487  * Add a CPU to our mask of valid CPUs that can be destinations of
  488  * interrupts.
  489  */
  490 void
  491 intr_add_cpu(u_int cpu)
  492 {
  493 
  494         if (cpu >= MAXCPU)
  495                 panic("%s: Invalid CPU ID", __func__);
  496         if (bootverbose)
  497                 printf("INTR: Adding local APIC %d as a target\n",
  498                     cpu_apic_ids[cpu]);
  499 
  500         intr_cpus |= (1 << cpu);
  501 }
  502 
  503 /*
  504  * Distribute all the interrupt sources among the available CPUs once the
  505  * AP's have been launched.
  506  */
  507 static void
  508 intr_shuffle_irqs(void *arg __unused)
  509 {
  510         struct intsrc *isrc;
  511         int i;
  512 
  513         /* Don't bother on UP. */
  514         if (mp_ncpus == 1)
  515                 return;
  516 
  517         /* Round-robin assign a CPU to each enabled source. */
  518         mtx_lock(&intr_table_lock);
  519         assign_cpu = 1;
  520         for (i = 0; i < NUM_IO_INTS; i++) {
  521                 isrc = interrupt_sources[i];
  522                 if (isrc != NULL && isrc->is_handlers > 0) {
  523                         /*
  524                          * If this event is already bound to a CPU,
  525                          * then assign the source to that CPU instead
  526                          * of picking one via round-robin.  Note that
  527                          * this is careful to only advance the
  528                          * round-robin if the CPU assignment succeeds.
  529                          */
  530                         if (isrc->is_event->ie_cpu != NOCPU)
  531                                 (void)isrc->is_pic->pic_assign_cpu(isrc,
  532                                     cpu_apic_ids[isrc->is_event->ie_cpu]);
  533                         else if (isrc->is_pic->pic_assign_cpu(isrc,
  534                                 cpu_apic_ids[current_cpu]) == 0)
  535                                 (void)intr_next_cpu();
  536 
  537                 }
  538         }
  539         mtx_unlock(&intr_table_lock);
  540 }
  541 SYSINIT(intr_shuffle_irqs, SI_SUB_SMP, SI_ORDER_SECOND, intr_shuffle_irqs,
  542     NULL);
  543 #else
  544 /*
  545  * Always route interrupts to the current processor in the UP case.
  546  */
  547 u_int
  548 intr_next_cpu(void)
  549 {
  550 
  551         return (PCPU_GET(apic_id));
  552 }
  553 #endif

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