1 /*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD: releng/9.0/sys/amd64/amd64/intr_machdep.c 224187 2011-07-18 15:19:40Z attilio $
30 */
31
32 /*
33 * Machine dependent interrupt code for amd64. For amd64, we have to
34 * deal with different PICs. Thus, we use the passed in vector to lookup
35 * an interrupt source associated with that vector. The interrupt source
36 * describes which PIC the source belongs to and includes methods to handle
37 * that source.
38 */
39
40 #include "opt_atpic.h"
41 #include "opt_ddb.h"
42
43 #include <sys/param.h>
44 #include <sys/bus.h>
45 #include <sys/interrupt.h>
46 #include <sys/ktr.h>
47 #include <sys/kernel.h>
48 #include <sys/lock.h>
49 #include <sys/mutex.h>
50 #include <sys/proc.h>
51 #include <sys/smp.h>
52 #include <sys/syslog.h>
53 #include <sys/systm.h>
54 #include <machine/clock.h>
55 #include <machine/intr_machdep.h>
56 #include <machine/smp.h>
57 #ifdef DDB
58 #include <ddb/ddb.h>
59 #endif
60
61 #ifndef DEV_ATPIC
62 #include <machine/segments.h>
63 #include <machine/frame.h>
64 #include <dev/ic/i8259.h>
65 #include <x86/isa/icu.h>
66 #include <x86/isa/isa.h>
67 #endif
68
69 #define MAX_STRAY_LOG 5
70
71 typedef void (*mask_fn)(void *);
72
73 static int intrcnt_index;
74 static struct intsrc *interrupt_sources[NUM_IO_INTS];
75 static struct mtx intr_table_lock;
76 static struct mtx intrcnt_lock;
77 static STAILQ_HEAD(, pic) pics;
78
79 #ifdef SMP
80 static int assign_cpu;
81 #endif
82
83 u_long intrcnt[INTRCNT_COUNT];
84 char intrnames[INTRCNT_COUNT * (MAXCOMLEN + 1)];
85 size_t sintrcnt = sizeof(intrcnt);
86 size_t sintrnames = sizeof(intrnames);
87
88 static int intr_assign_cpu(void *arg, u_char cpu);
89 static void intr_disable_src(void *arg);
90 static void intr_init(void *__dummy);
91 static int intr_pic_registered(struct pic *pic);
92 static void intrcnt_setname(const char *name, int index);
93 static void intrcnt_updatename(struct intsrc *is);
94 static void intrcnt_register(struct intsrc *is);
95
96 static int
97 intr_pic_registered(struct pic *pic)
98 {
99 struct pic *p;
100
101 STAILQ_FOREACH(p, &pics, pics) {
102 if (p == pic)
103 return (1);
104 }
105 return (0);
106 }
107
108 /*
109 * Register a new interrupt controller (PIC). This is to support suspend
110 * and resume where we suspend/resume controllers rather than individual
111 * sources. This also allows controllers with no active sources (such as
112 * 8259As in a system using the APICs) to participate in suspend and resume.
113 */
114 int
115 intr_register_pic(struct pic *pic)
116 {
117 int error;
118
119 mtx_lock(&intr_table_lock);
120 if (intr_pic_registered(pic))
121 error = EBUSY;
122 else {
123 STAILQ_INSERT_TAIL(&pics, pic, pics);
124 error = 0;
125 }
126 mtx_unlock(&intr_table_lock);
127 return (error);
128 }
129
130 /*
131 * Register a new interrupt source with the global interrupt system.
132 * The global interrupts need to be disabled when this function is
133 * called.
134 */
135 int
136 intr_register_source(struct intsrc *isrc)
137 {
138 int error, vector;
139
140 KASSERT(intr_pic_registered(isrc->is_pic), ("unregistered PIC"));
141 vector = isrc->is_pic->pic_vector(isrc);
142 if (interrupt_sources[vector] != NULL)
143 return (EEXIST);
144 error = intr_event_create(&isrc->is_event, isrc, 0, vector,
145 intr_disable_src, (mask_fn)isrc->is_pic->pic_enable_source,
146 (mask_fn)isrc->is_pic->pic_eoi_source, intr_assign_cpu, "irq%d:",
147 vector);
148 if (error)
149 return (error);
150 mtx_lock(&intr_table_lock);
151 if (interrupt_sources[vector] != NULL) {
152 mtx_unlock(&intr_table_lock);
153 intr_event_destroy(isrc->is_event);
154 return (EEXIST);
155 }
156 intrcnt_register(isrc);
157 interrupt_sources[vector] = isrc;
158 isrc->is_handlers = 0;
159 mtx_unlock(&intr_table_lock);
160 return (0);
161 }
162
163 struct intsrc *
164 intr_lookup_source(int vector)
165 {
166
167 return (interrupt_sources[vector]);
168 }
169
170 int
171 intr_add_handler(const char *name, int vector, driver_filter_t filter,
172 driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep)
173 {
174 struct intsrc *isrc;
175 int error;
176
177 isrc = intr_lookup_source(vector);
178 if (isrc == NULL)
179 return (EINVAL);
180 error = intr_event_add_handler(isrc->is_event, name, filter, handler,
181 arg, intr_priority(flags), flags, cookiep);
182 if (error == 0) {
183 mtx_lock(&intr_table_lock);
184 intrcnt_updatename(isrc);
185 isrc->is_handlers++;
186 if (isrc->is_handlers == 1) {
187 isrc->is_pic->pic_enable_intr(isrc);
188 isrc->is_pic->pic_enable_source(isrc);
189 }
190 mtx_unlock(&intr_table_lock);
191 }
192 return (error);
193 }
194
195 int
196 intr_remove_handler(void *cookie)
197 {
198 struct intsrc *isrc;
199 int error;
200
201 isrc = intr_handler_source(cookie);
202 error = intr_event_remove_handler(cookie);
203 if (error == 0) {
204 mtx_lock(&intr_table_lock);
205 isrc->is_handlers--;
206 if (isrc->is_handlers == 0) {
207 isrc->is_pic->pic_disable_source(isrc, PIC_NO_EOI);
208 isrc->is_pic->pic_disable_intr(isrc);
209 }
210 intrcnt_updatename(isrc);
211 mtx_unlock(&intr_table_lock);
212 }
213 return (error);
214 }
215
216 int
217 intr_config_intr(int vector, enum intr_trigger trig, enum intr_polarity pol)
218 {
219 struct intsrc *isrc;
220
221 isrc = intr_lookup_source(vector);
222 if (isrc == NULL)
223 return (EINVAL);
224 return (isrc->is_pic->pic_config_intr(isrc, trig, pol));
225 }
226
227 static void
228 intr_disable_src(void *arg)
229 {
230 struct intsrc *isrc;
231
232 isrc = arg;
233 isrc->is_pic->pic_disable_source(isrc, PIC_EOI);
234 }
235
236 void
237 intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame)
238 {
239 struct intr_event *ie;
240 int vector;
241
242 /*
243 * We count software interrupts when we process them. The
244 * code here follows previous practice, but there's an
245 * argument for counting hardware interrupts when they're
246 * processed too.
247 */
248 (*isrc->is_count)++;
249 PCPU_INC(cnt.v_intr);
250
251 ie = isrc->is_event;
252
253 /*
254 * XXX: We assume that IRQ 0 is only used for the ISA timer
255 * device (clk).
256 */
257 vector = isrc->is_pic->pic_vector(isrc);
258 if (vector == 0)
259 clkintr_pending = 1;
260
261 /*
262 * For stray interrupts, mask and EOI the source, bump the
263 * stray count, and log the condition.
264 */
265 if (intr_event_handle(ie, frame) != 0) {
266 isrc->is_pic->pic_disable_source(isrc, PIC_EOI);
267 (*isrc->is_straycount)++;
268 if (*isrc->is_straycount < MAX_STRAY_LOG)
269 log(LOG_ERR, "stray irq%d\n", vector);
270 else if (*isrc->is_straycount == MAX_STRAY_LOG)
271 log(LOG_CRIT,
272 "too many stray irq %d's: not logging anymore\n",
273 vector);
274 }
275 }
276
277 void
278 intr_resume(void)
279 {
280 struct pic *pic;
281
282 #ifndef DEV_ATPIC
283 atpic_reset();
284 #endif
285 mtx_lock(&intr_table_lock);
286 STAILQ_FOREACH(pic, &pics, pics) {
287 if (pic->pic_resume != NULL)
288 pic->pic_resume(pic);
289 }
290 mtx_unlock(&intr_table_lock);
291 }
292
293 void
294 intr_suspend(void)
295 {
296 struct pic *pic;
297
298 mtx_lock(&intr_table_lock);
299 STAILQ_FOREACH(pic, &pics, pics) {
300 if (pic->pic_suspend != NULL)
301 pic->pic_suspend(pic);
302 }
303 mtx_unlock(&intr_table_lock);
304 }
305
306 static int
307 intr_assign_cpu(void *arg, u_char cpu)
308 {
309 #ifdef SMP
310 struct intsrc *isrc;
311 int error;
312
313 /*
314 * Don't do anything during early boot. We will pick up the
315 * assignment once the APs are started.
316 */
317 if (assign_cpu && cpu != NOCPU) {
318 isrc = arg;
319 mtx_lock(&intr_table_lock);
320 error = isrc->is_pic->pic_assign_cpu(isrc, cpu_apic_ids[cpu]);
321 mtx_unlock(&intr_table_lock);
322 } else
323 error = 0;
324 return (error);
325 #else
326 return (EOPNOTSUPP);
327 #endif
328 }
329
330 static void
331 intrcnt_setname(const char *name, int index)
332 {
333
334 snprintf(intrnames + (MAXCOMLEN + 1) * index, MAXCOMLEN + 1, "%-*s",
335 MAXCOMLEN, name);
336 }
337
338 static void
339 intrcnt_updatename(struct intsrc *is)
340 {
341
342 intrcnt_setname(is->is_event->ie_fullname, is->is_index);
343 }
344
345 static void
346 intrcnt_register(struct intsrc *is)
347 {
348 char straystr[MAXCOMLEN + 1];
349
350 KASSERT(is->is_event != NULL, ("%s: isrc with no event", __func__));
351 mtx_lock_spin(&intrcnt_lock);
352 is->is_index = intrcnt_index;
353 intrcnt_index += 2;
354 snprintf(straystr, MAXCOMLEN + 1, "stray irq%d",
355 is->is_pic->pic_vector(is));
356 intrcnt_updatename(is);
357 is->is_count = &intrcnt[is->is_index];
358 intrcnt_setname(straystr, is->is_index + 1);
359 is->is_straycount = &intrcnt[is->is_index + 1];
360 mtx_unlock_spin(&intrcnt_lock);
361 }
362
363 void
364 intrcnt_add(const char *name, u_long **countp)
365 {
366
367 mtx_lock_spin(&intrcnt_lock);
368 *countp = &intrcnt[intrcnt_index];
369 intrcnt_setname(name, intrcnt_index);
370 intrcnt_index++;
371 mtx_unlock_spin(&intrcnt_lock);
372 }
373
374 static void
375 intr_init(void *dummy __unused)
376 {
377
378 intrcnt_setname("???", 0);
379 intrcnt_index = 1;
380 STAILQ_INIT(&pics);
381 mtx_init(&intr_table_lock, "intr sources", NULL, MTX_DEF);
382 mtx_init(&intrcnt_lock, "intrcnt", NULL, MTX_SPIN);
383 }
384 SYSINIT(intr_init, SI_SUB_INTR, SI_ORDER_FIRST, intr_init, NULL);
385
386 #ifndef DEV_ATPIC
387 /* Initialize the two 8259A's to a known-good shutdown state. */
388 void
389 atpic_reset(void)
390 {
391
392 outb(IO_ICU1, ICW1_RESET | ICW1_IC4);
393 outb(IO_ICU1 + ICU_IMR_OFFSET, IDT_IO_INTS);
394 outb(IO_ICU1 + ICU_IMR_OFFSET, 1 << 2);
395 outb(IO_ICU1 + ICU_IMR_OFFSET, ICW4_8086);
396 outb(IO_ICU1 + ICU_IMR_OFFSET, 0xff);
397 outb(IO_ICU1, OCW3_SEL | OCW3_RR);
398
399 outb(IO_ICU2, ICW1_RESET | ICW1_IC4);
400 outb(IO_ICU2 + ICU_IMR_OFFSET, IDT_IO_INTS + 8);
401 outb(IO_ICU2 + ICU_IMR_OFFSET, 2);
402 outb(IO_ICU2 + ICU_IMR_OFFSET, ICW4_8086);
403 outb(IO_ICU2 + ICU_IMR_OFFSET, 0xff);
404 outb(IO_ICU2, OCW3_SEL | OCW3_RR);
405 }
406 #endif
407
408 /* Add a description to an active interrupt handler. */
409 int
410 intr_describe(u_int vector, void *ih, const char *descr)
411 {
412 struct intsrc *isrc;
413 int error;
414
415 isrc = intr_lookup_source(vector);
416 if (isrc == NULL)
417 return (EINVAL);
418 error = intr_event_describe_handler(isrc->is_event, ih, descr);
419 if (error)
420 return (error);
421 intrcnt_updatename(isrc);
422 return (0);
423 }
424
425 #ifdef DDB
426 /*
427 * Dump data about interrupt handlers
428 */
429 DB_SHOW_COMMAND(irqs, db_show_irqs)
430 {
431 struct intsrc **isrc;
432 int i, verbose;
433
434 if (strcmp(modif, "v") == 0)
435 verbose = 1;
436 else
437 verbose = 0;
438 isrc = interrupt_sources;
439 for (i = 0; i < NUM_IO_INTS && !db_pager_quit; i++, isrc++)
440 if (*isrc != NULL)
441 db_dump_intr_event((*isrc)->is_event, verbose);
442 }
443 #endif
444
445 #ifdef SMP
446 /*
447 * Support for balancing interrupt sources across CPUs. For now we just
448 * allocate CPUs round-robin.
449 */
450
451 static cpuset_t intr_cpus;
452 static int current_cpu;
453
454 /*
455 * Return the CPU that the next interrupt source should use. For now
456 * this just returns the next local APIC according to round-robin.
457 */
458 u_int
459 intr_next_cpu(void)
460 {
461 u_int apic_id;
462
463 /* Leave all interrupts on the BSP during boot. */
464 if (!assign_cpu)
465 return (PCPU_GET(apic_id));
466
467 mtx_lock_spin(&icu_lock);
468 apic_id = cpu_apic_ids[current_cpu];
469 do {
470 current_cpu++;
471 if (current_cpu > mp_maxid)
472 current_cpu = 0;
473 } while (!CPU_ISSET(current_cpu, &intr_cpus));
474 mtx_unlock_spin(&icu_lock);
475 return (apic_id);
476 }
477
478 /* Attempt to bind the specified IRQ to the specified CPU. */
479 int
480 intr_bind(u_int vector, u_char cpu)
481 {
482 struct intsrc *isrc;
483
484 isrc = intr_lookup_source(vector);
485 if (isrc == NULL)
486 return (EINVAL);
487 return (intr_event_bind(isrc->is_event, cpu));
488 }
489
490 /*
491 * Add a CPU to our mask of valid CPUs that can be destinations of
492 * interrupts.
493 */
494 void
495 intr_add_cpu(u_int cpu)
496 {
497
498 if (cpu >= MAXCPU)
499 panic("%s: Invalid CPU ID", __func__);
500 if (bootverbose)
501 printf("INTR: Adding local APIC %d as a target\n",
502 cpu_apic_ids[cpu]);
503
504 CPU_SET(cpu, &intr_cpus);
505 }
506
507 /*
508 * Distribute all the interrupt sources among the available CPUs once the
509 * AP's have been launched.
510 */
511 static void
512 intr_shuffle_irqs(void *arg __unused)
513 {
514 struct intsrc *isrc;
515 int i;
516
517 /* The BSP is always a valid target. */
518 CPU_SETOF(0, &intr_cpus);
519
520 /* Don't bother on UP. */
521 if (mp_ncpus == 1)
522 return;
523
524 /* Round-robin assign a CPU to each enabled source. */
525 mtx_lock(&intr_table_lock);
526 assign_cpu = 1;
527 for (i = 0; i < NUM_IO_INTS; i++) {
528 isrc = interrupt_sources[i];
529 if (isrc != NULL && isrc->is_handlers > 0) {
530 /*
531 * If this event is already bound to a CPU,
532 * then assign the source to that CPU instead
533 * of picking one via round-robin. Note that
534 * this is careful to only advance the
535 * round-robin if the CPU assignment succeeds.
536 */
537 if (isrc->is_event->ie_cpu != NOCPU)
538 (void)isrc->is_pic->pic_assign_cpu(isrc,
539 cpu_apic_ids[isrc->is_event->ie_cpu]);
540 else if (isrc->is_pic->pic_assign_cpu(isrc,
541 cpu_apic_ids[current_cpu]) == 0)
542 (void)intr_next_cpu();
543
544 }
545 }
546 mtx_unlock(&intr_table_lock);
547 }
548 SYSINIT(intr_shuffle_irqs, SI_SUB_SMP, SI_ORDER_SECOND, intr_shuffle_irqs,
549 NULL);
550 #else
551 /*
552 * Always route interrupts to the current processor in the UP case.
553 */
554 u_int
555 intr_next_cpu(void)
556 {
557
558 return (PCPU_GET(apic_id));
559 }
560 #endif
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