The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/io_apic.c

Version: -  FREEBSD  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-2  -  FREEBSD-11-1  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-4  -  FREEBSD-10-3  -  FREEBSD-10-2  -  FREEBSD-10-1  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-3  -  FREEBSD-9-2  -  FREEBSD-9-1  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-4  -  FREEBSD-8-3  -  FREEBSD-8-2  -  FREEBSD-8-1  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-4  -  FREEBSD-7-3  -  FREEBSD-7-2  -  FREEBSD-7-1  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-4  -  FREEBSD-6-3  -  FREEBSD-6-2  -  FREEBSD-6-1  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-5  -  FREEBSD-5-4  -  FREEBSD-5-3  -  FREEBSD-5-2  -  FREEBSD-5-1  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  linux-2.6  -  linux-2.4.22  -  MK83  -  MK84  -  PLAN9  -  DFBSD  -  NETBSD  -  NETBSD5  -  NETBSD4  -  NETBSD3  -  NETBSD20  -  OPENBSD  -  xnu-517  -  xnu-792  -  xnu-792.6.70  -  xnu-1228  -  xnu-1456.1.26  -  xnu-1699.24.8  -  xnu-2050.18.24  -  OPENSOLARIS  -  minix-3-1-1 
SearchContext: -  none  -  3  -  10 

    1 /*-
    2  * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. Neither the name of the author nor the names of any co-contributors
   14  *    may be used to endorse or promote products derived from this software
   15  *    without specific prior written permission.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  */
   29 
   30 #include <sys/cdefs.h>
   31 __FBSDID("$FreeBSD: releng/5.4/sys/amd64/amd64/io_apic.c 145335 2005-04-20 19:11:07Z cvs2svn $");
   32 
   33 #include "opt_atpic.h"
   34 #include "opt_isa.h"
   35 #include "opt_no_mixed_mode.h"
   36 
   37 #include <sys/param.h>
   38 #include <sys/systm.h>
   39 #include <sys/bus.h>
   40 #include <sys/kernel.h>
   41 #include <sys/malloc.h>
   42 #include <sys/lock.h>
   43 #include <sys/mutex.h>
   44 
   45 #include <vm/vm.h>
   46 #include <vm/pmap.h>
   47 
   48 #include <machine/apicreg.h>
   49 #include <machine/frame.h>
   50 #include <machine/intr_machdep.h>
   51 #include <machine/apicvar.h>
   52 #include <machine/segments.h>
   53 
   54 #define IOAPIC_ISA_INTS         16
   55 #define IOAPIC_MEM_REGION       32
   56 #define IOAPIC_REDTBL_LO(i)     (IOAPIC_REDTBL + (i) * 2)
   57 #define IOAPIC_REDTBL_HI(i)     (IOAPIC_REDTBL_LO(i) + 1)
   58 
   59 #define VECTOR_EXTINT           252
   60 #define VECTOR_NMI              253
   61 #define VECTOR_SMI              254
   62 #define VECTOR_DISABLED         255
   63 
   64 #define DEST_NONE               -1
   65 #define DEST_EXTINT             -2
   66 
   67 #define TODO            printf("%s: not implemented!\n", __func__)
   68 
   69 MALLOC_DEFINE(M_IOAPIC, "I/O APIC", "I/O APIC structures");
   70 
   71 /*
   72  * New interrupt support code..
   73  *
   74  * XXX: we really should have the interrupt cookie passed up from new-bus
   75  * just be a int pin, and not map 1:1 to interrupt vector number but should
   76  * use INTR_TYPE_FOO to set priority bands for device classes and do all the
   77  * magic remapping of intpin to vector in here.  For now we just cheat as on
   78  * ia64 and map intpin X to vector NRSVIDT + X.  Note that we assume that the
   79  * first IO APIC has ISA interrupts on pins 1-15.  Not sure how you are
   80  * really supposed to figure out which IO APIC in a system with multiple IO
   81  * APIC's actually has the ISA interrupts routed to it.  As far as interrupt
   82  * pin numbers, we use the ACPI System Interrupt number model where each
   83  * IO APIC has a contiguous chunk of the System Interrupt address space.
   84  */
   85 
   86 /*
   87  * Direct the ExtINT pin on the first I/O APIC to a logical cluster of
   88  * CPUs rather than a physical destination of just the BSP.
   89  *
   90  * Note: This is disabled by default as test systems seem to croak with it
   91  * enabled.
   92 #define ENABLE_EXTINT_LOGICAL_DESTINATION
   93  */
   94 
   95 struct ioapic_intsrc {
   96         struct intsrc io_intsrc;
   97         u_int io_intpin:8;
   98         u_int io_vector:8;
   99         u_int io_activehi:1;
  100         u_int io_edgetrigger:1;
  101         u_int io_masked:1;
  102         int io_dest:5;
  103         int io_bus:4;
  104 };
  105 
  106 struct ioapic {
  107         struct pic io_pic;
  108         u_int io_id:8;                  /* logical ID */
  109         u_int io_apic_id:4;
  110         u_int io_intbase:8;             /* System Interrupt base */
  111         u_int io_numintr:8;
  112         volatile ioapic_t *io_addr;     /* XXX: should use bus_space */
  113         STAILQ_ENTRY(ioapic) io_next;
  114         struct ioapic_intsrc io_pins[0];
  115 };
  116 
  117 static u_int    ioapic_read(volatile ioapic_t *apic, int reg);
  118 static void     ioapic_write(volatile ioapic_t *apic, int reg, u_int val);
  119 static const char *ioapic_bus_string(int bus_type);
  120 static void     ioapic_print_vector(struct ioapic_intsrc *intpin);
  121 static void     ioapic_enable_source(struct intsrc *isrc);
  122 static void     ioapic_disable_source(struct intsrc *isrc, int eoi);
  123 static void     ioapic_eoi_source(struct intsrc *isrc);
  124 static void     ioapic_enable_intr(struct intsrc *isrc);
  125 static int      ioapic_vector(struct intsrc *isrc);
  126 static int      ioapic_source_pending(struct intsrc *isrc);
  127 static int      ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
  128                     enum intr_polarity pol);
  129 static void     ioapic_suspend(struct intsrc *isrc);
  130 static void     ioapic_resume(struct intsrc *isrc);
  131 static void     ioapic_program_destination(struct ioapic_intsrc *intpin);
  132 static void     ioapic_program_intpin(struct ioapic_intsrc *intpin);
  133 static void     ioapic_setup_mixed_mode(struct ioapic_intsrc *intpin);
  134 
  135 static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list);
  136 struct pic ioapic_template = { ioapic_enable_source, ioapic_disable_source,
  137                                ioapic_eoi_source, ioapic_enable_intr,
  138                                ioapic_vector, ioapic_source_pending,
  139                                ioapic_suspend, ioapic_resume,
  140                                ioapic_config_intr };
  141         
  142 static int bsp_id, current_cluster, logical_clusters, next_ioapic_base;
  143 static u_int mixed_mode_enabled, next_id, program_logical_dest;
  144 #if defined(NO_MIXED_MODE) || !defined(DEV_ATPIC)
  145 static int mixed_mode_active = 0;
  146 #else
  147 static int mixed_mode_active = 1;
  148 #endif
  149 TUNABLE_INT("hw.apic.mixed_mode", &mixed_mode_active);
  150 
  151 static __inline void
  152 _ioapic_eoi_source(struct intsrc *isrc)
  153 {
  154         lapic_eoi();
  155 }
  156 
  157 static u_int
  158 ioapic_read(volatile ioapic_t *apic, int reg)
  159 {
  160 
  161         mtx_assert(&icu_lock, MA_OWNED);
  162         apic->ioregsel = reg;
  163         return (apic->iowin);
  164 }
  165 
  166 static void
  167 ioapic_write(volatile ioapic_t *apic, int reg, u_int val)
  168 {
  169 
  170         mtx_assert(&icu_lock, MA_OWNED);
  171         apic->ioregsel = reg;
  172         apic->iowin = val;
  173 }
  174 
  175 static const char *
  176 ioapic_bus_string(int bus_type)
  177 {
  178 
  179         switch (bus_type) {
  180         case APIC_BUS_ISA:
  181                 return ("ISA");
  182         case APIC_BUS_EISA:
  183                 return ("EISA");
  184         case APIC_BUS_PCI:
  185                 return ("PCI");
  186         default:
  187                 return ("unknown");
  188         }
  189 }
  190 
  191 static void
  192 ioapic_print_vector(struct ioapic_intsrc *intpin)
  193 {
  194 
  195         switch (intpin->io_vector) {
  196         case VECTOR_DISABLED:
  197                 printf("disabled");
  198                 break;
  199         case VECTOR_EXTINT:
  200                 printf("ExtINT");
  201                 break;
  202         case VECTOR_NMI:
  203                 printf("NMI");
  204                 break;
  205         case VECTOR_SMI:
  206                 printf("SMI");
  207                 break;
  208         default:
  209                 printf("%s IRQ %u", ioapic_bus_string(intpin->io_bus),
  210                     intpin->io_vector);
  211         }
  212 }
  213 
  214 static void
  215 ioapic_enable_source(struct intsrc *isrc)
  216 {
  217         struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
  218         struct ioapic *io = (struct ioapic *)isrc->is_pic;
  219         uint32_t flags;
  220 
  221         mtx_lock_spin(&icu_lock);
  222         if (intpin->io_masked) {
  223                 flags = ioapic_read(io->io_addr,
  224                     IOAPIC_REDTBL_LO(intpin->io_intpin));
  225                 flags &= ~(IOART_INTMASK);
  226                 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
  227                     flags);
  228                 intpin->io_masked = 0;
  229         }
  230         mtx_unlock_spin(&icu_lock);
  231 }
  232 
  233 static void
  234 ioapic_disable_source(struct intsrc *isrc, int eoi)
  235 {
  236         struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
  237         struct ioapic *io = (struct ioapic *)isrc->is_pic;
  238         uint32_t flags;
  239 
  240         mtx_lock_spin(&icu_lock);
  241         if (!intpin->io_masked && !intpin->io_edgetrigger) {
  242                 flags = ioapic_read(io->io_addr,
  243                     IOAPIC_REDTBL_LO(intpin->io_intpin));
  244                 flags |= IOART_INTMSET;
  245                 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
  246                     flags);
  247                 intpin->io_masked = 1;
  248         }
  249 
  250         if (eoi == PIC_EOI)
  251                 _ioapic_eoi_source(isrc);
  252 
  253         mtx_unlock_spin(&icu_lock);
  254 }
  255 
  256 static void
  257 ioapic_eoi_source(struct intsrc *isrc)
  258 {
  259 
  260         _ioapic_eoi_source(isrc);
  261 }
  262 
  263 /*
  264  * Completely program an intpin based on the data in its interrupt source
  265  * structure.
  266  */
  267 static void
  268 ioapic_program_intpin(struct ioapic_intsrc *intpin)
  269 {
  270         struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
  271         uint32_t low, high, value;
  272 
  273         /*
  274          * For pins routed via mixed mode or disabled, just ensure that
  275          * they are masked.
  276          */
  277         if (intpin->io_dest == DEST_EXTINT ||
  278             intpin->io_vector == VECTOR_DISABLED) {
  279                 low = ioapic_read(io->io_addr,
  280                     IOAPIC_REDTBL_LO(intpin->io_intpin));
  281                 if ((low & IOART_INTMASK) == IOART_INTMCLR)
  282                         ioapic_write(io->io_addr,
  283                             IOAPIC_REDTBL_LO(intpin->io_intpin),
  284                             low | IOART_INTMSET);
  285                 return;
  286         }
  287 
  288         /* Set the destination. */
  289         if (intpin->io_dest == DEST_NONE) {
  290                 low = IOART_DESTPHY;
  291                 high = bsp_id << APIC_ID_SHIFT;
  292         } else {
  293                 low = IOART_DESTLOG;
  294                 high = (intpin->io_dest << APIC_ID_CLUSTER_SHIFT |
  295                     APIC_ID_CLUSTER_ID) << APIC_ID_SHIFT;
  296         }
  297 
  298         /* Program the rest of the low word. */
  299         if (intpin->io_edgetrigger)
  300                 low |= IOART_TRGREDG;
  301         else
  302                 low |= IOART_TRGRLVL;
  303         if (intpin->io_activehi)
  304                 low |= IOART_INTAHI;
  305         else
  306                 low |= IOART_INTALO;
  307         if (intpin->io_masked)
  308                 low |= IOART_INTMSET;
  309         switch (intpin->io_vector) {
  310         case VECTOR_EXTINT:
  311                 KASSERT(intpin->io_edgetrigger,
  312                     ("EXTINT not edge triggered"));
  313                 low |= IOART_DELEXINT;
  314                 break;
  315         case VECTOR_NMI:
  316                 KASSERT(intpin->io_edgetrigger,
  317                     ("NMI not edge triggered"));
  318                 low |= IOART_DELNMI;
  319                 break;
  320         case VECTOR_SMI:
  321                 KASSERT(intpin->io_edgetrigger,
  322                     ("SMI not edge triggered"));
  323                 low |= IOART_DELSMI;
  324                 break;
  325         default:
  326                 low |= IOART_DELLOPRI | apic_irq_to_idt(intpin->io_vector);
  327         }
  328 
  329         /* Write the values to the APIC. */
  330         mtx_lock_spin(&icu_lock);
  331         ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low);
  332         value = ioapic_read(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin));
  333         value &= ~IOART_DEST;
  334         value |= high;
  335         ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), value);
  336         mtx_unlock_spin(&icu_lock);
  337 }
  338 
  339 /*
  340  * Program an individual intpin's logical destination.
  341  */
  342 static void
  343 ioapic_program_destination(struct ioapic_intsrc *intpin)
  344 {
  345         struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
  346 
  347         KASSERT(intpin->io_dest != DEST_NONE,
  348             ("intpin not assigned to a cluster"));
  349         KASSERT(intpin->io_dest != DEST_EXTINT,
  350             ("intpin routed via ExtINT"));
  351         if (bootverbose) {
  352                 printf("ioapic%u: routing intpin %u (", io->io_id,
  353                     intpin->io_intpin);
  354                 ioapic_print_vector(intpin);
  355                 printf(") to cluster %u\n", intpin->io_dest);
  356         }
  357         ioapic_program_intpin(intpin);
  358 }
  359 
  360 static void
  361 ioapic_assign_cluster(struct ioapic_intsrc *intpin)
  362 {
  363 
  364         /*
  365          * Assign this intpin to a logical APIC cluster in a
  366          * round-robin fashion.  We don't actually use the logical
  367          * destination for this intpin until after all the CPU's
  368          * have been started so that we don't end up with interrupts
  369          * that don't go anywhere.  Another alternative might be to
  370          * start up the CPU's earlier so that they can handle interrupts
  371          * sooner.
  372          */
  373         intpin->io_dest = current_cluster;
  374         current_cluster++;
  375         if (current_cluster >= logical_clusters)
  376                 current_cluster = 0;
  377         if (program_logical_dest)
  378                 ioapic_program_destination(intpin);
  379 }
  380 
  381 static void
  382 ioapic_enable_intr(struct intsrc *isrc)
  383 {
  384         struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
  385 
  386         KASSERT(intpin->io_dest != DEST_EXTINT,
  387             ("ExtINT pin trying to use ioapic enable_intr method"));
  388         if (intpin->io_dest == DEST_NONE) {
  389                 ioapic_assign_cluster(intpin);
  390                 lapic_enable_intr(intpin->io_vector);
  391         }
  392 }
  393 
  394 static int
  395 ioapic_vector(struct intsrc *isrc)
  396 {
  397         struct ioapic_intsrc *pin;
  398 
  399         pin = (struct ioapic_intsrc *)isrc;
  400         return (pin->io_vector);
  401 }
  402 
  403 static int
  404 ioapic_source_pending(struct intsrc *isrc)
  405 {
  406         struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
  407 
  408         return (lapic_intr_pending(intpin->io_vector));
  409 }
  410 
  411 static int
  412 ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
  413     enum intr_polarity pol)
  414 {
  415         struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
  416         struct ioapic *io = (struct ioapic *)isrc->is_pic;
  417         int changed;
  418 
  419         KASSERT(!(trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM),
  420             ("%s: Conforming trigger or polarity\n", __func__));
  421 
  422         /*
  423          * EISA interrupts always use active high polarity, so don't allow
  424          * them to be set to active low.
  425          *
  426          * XXX: Should we write to the ELCR if the trigger mode changes for
  427          * an EISA IRQ or an ISA IRQ with the ELCR present?
  428          */
  429         if (intpin->io_bus == APIC_BUS_EISA)
  430                 pol = INTR_POLARITY_HIGH;
  431         changed = 0;
  432         if (intpin->io_edgetrigger != (trig == INTR_TRIGGER_EDGE)) {
  433                 if (bootverbose)
  434                         printf("ioapic%u: Changing trigger for pin %u to %s\n",
  435                             io->io_id, intpin->io_intpin,
  436                             trig == INTR_TRIGGER_EDGE ? "edge" : "level");
  437                 intpin->io_edgetrigger = (trig == INTR_TRIGGER_EDGE);
  438                 changed++;
  439         }
  440         if (intpin->io_activehi != (pol == INTR_POLARITY_HIGH)) {
  441                 if (bootverbose)
  442                         printf("ioapic%u: Changing polarity for pin %u to %s\n",
  443                             io->io_id, intpin->io_intpin,
  444                             pol == INTR_POLARITY_HIGH ? "high" : "low");
  445                 intpin->io_activehi = (pol == INTR_POLARITY_HIGH);
  446                 changed++;
  447         }
  448         if (changed)
  449                 ioapic_program_intpin(intpin);
  450         return (0);
  451 }
  452 
  453 static void
  454 ioapic_suspend(struct intsrc *isrc)
  455 {
  456 
  457         TODO;
  458 }
  459 
  460 static void
  461 ioapic_resume(struct intsrc *isrc)
  462 {
  463 
  464         ioapic_program_intpin((struct ioapic_intsrc *)isrc);
  465 }
  466 
  467 /*
  468  * APIC enumerators call this function to indicate that the 8259A AT PICs
  469  * are available and that mixed mode can be used.
  470  */
  471 void
  472 ioapic_enable_mixed_mode(void)
  473 {
  474 
  475         mixed_mode_enabled = 1;
  476 }
  477 
  478 /*
  479  * Allocate and return a logical cluster ID.  Note that the first time
  480  * this is called, it returns cluster 0.  ioapic_enable_intr() treats
  481  * the two cases of logical_clusters == 0 and logical_clusters == 1 the
  482  * same: one cluster of ID 0 exists.  The logical_clusters == 0 case is
  483  * for UP kernels, which should never call this function.
  484  */
  485 int
  486 ioapic_next_logical_cluster(void)
  487 {
  488 
  489         if (logical_clusters >= APIC_MAX_CLUSTER)
  490                 panic("WARNING: Local APIC cluster IDs exhausted!");
  491         return (logical_clusters++);
  492 }
  493 
  494 /*
  495  * Create a plain I/O APIC object.
  496  */
  497 void *
  498 ioapic_create(uintptr_t addr, int32_t apic_id, int intbase)
  499 {
  500         struct ioapic *io;
  501         struct ioapic_intsrc *intpin;
  502         volatile ioapic_t *apic;
  503         u_int numintr, i;
  504         uint32_t value;
  505 
  506         apic = (ioapic_t *)pmap_mapdev(addr, IOAPIC_MEM_REGION);
  507         mtx_lock_spin(&icu_lock);
  508         numintr = ((ioapic_read(apic, IOAPIC_VER) & IOART_VER_MAXREDIR) >>
  509             MAXREDIRSHIFT) + 1;
  510         mtx_unlock_spin(&icu_lock);
  511         io = malloc(sizeof(struct ioapic) +
  512             numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK);
  513         io->io_pic = ioapic_template;
  514         mtx_lock_spin(&icu_lock);
  515         io->io_id = next_id++;
  516         io->io_apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT; 
  517         if (apic_id != -1 && io->io_apic_id != apic_id) {
  518                 ioapic_write(apic, IOAPIC_ID, apic_id << APIC_ID_SHIFT);
  519                 mtx_unlock_spin(&icu_lock);
  520                 io->io_apic_id = apic_id;
  521                 printf("ioapic%u: Changing APIC ID to %d\n", io->io_id,
  522                     apic_id);
  523         } else
  524                 mtx_unlock_spin(&icu_lock);
  525         if (intbase == -1) {
  526                 intbase = next_ioapic_base;
  527                 printf("ioapic%u: Assuming intbase of %d\n", io->io_id,
  528                     intbase);
  529         } else if (intbase != next_ioapic_base)
  530                 printf("ioapic%u: WARNING: intbase %d != expected base %d\n",
  531                     io->io_id, intbase, next_ioapic_base);
  532         io->io_intbase = intbase;
  533         next_ioapic_base = intbase + numintr;
  534         io->io_numintr = numintr;
  535         io->io_addr = apic;
  536 
  537         /*
  538          * Initialize pins.  Start off with interrupts disabled.  Default
  539          * to active-hi and edge-triggered for ISA interrupts and active-lo
  540          * and level-triggered for all others.
  541          */
  542         bzero(io->io_pins, sizeof(struct ioapic_intsrc) * numintr);
  543         mtx_lock_spin(&icu_lock);
  544         for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) {
  545                 intpin->io_intsrc.is_pic = (struct pic *)io;
  546                 intpin->io_intpin = i;
  547                 intpin->io_vector = intbase + i;
  548 
  549                 /*
  550                  * Assume that pin 0 on the first I/O APIC is an ExtINT pin
  551                  * if mixed mode is enabled and an ISA interrupt if not.
  552                  * Assume that pins 1-15 are ISA interrupts and that all
  553                  * other pins are PCI interrupts.
  554                  */
  555                 if (intpin->io_vector == 0 && mixed_mode_enabled)
  556                         ioapic_set_extint(io, i);
  557                 else if (intpin->io_vector < IOAPIC_ISA_INTS) {
  558                         intpin->io_bus = APIC_BUS_ISA;
  559                         intpin->io_activehi = 1;
  560                         intpin->io_edgetrigger = 1;
  561                         intpin->io_masked = 1;
  562                 } else {
  563                         intpin->io_bus = APIC_BUS_PCI;
  564                         intpin->io_activehi = 0;
  565                         intpin->io_edgetrigger = 0;
  566                         intpin->io_masked = 1;
  567                 }
  568 
  569                 /*
  570                  * Route interrupts to the BSP by default using physical
  571                  * addressing.  Vectored interrupts get readdressed using
  572                  * logical IDs to CPU clusters when they are enabled.
  573                  */
  574                 intpin->io_dest = DEST_NONE;
  575                 if (bootverbose && intpin->io_vector != VECTOR_DISABLED) {
  576                         printf("ioapic%u: intpin %d -> ",  io->io_id, i);
  577                         ioapic_print_vector(intpin);
  578                         printf(" (%s, %s)\n", intpin->io_edgetrigger ?
  579                             "edge" : "level", intpin->io_activehi ? "high" :
  580                             "low");
  581                 }
  582                 value = ioapic_read(apic, IOAPIC_REDTBL_LO(i));
  583                 ioapic_write(apic, IOAPIC_REDTBL_LO(i), value | IOART_INTMSET);
  584         }
  585         mtx_unlock_spin(&icu_lock);
  586 
  587         return (io);
  588 }
  589 
  590 int
  591 ioapic_get_vector(void *cookie, u_int pin)
  592 {
  593         struct ioapic *io;
  594 
  595         io = (struct ioapic *)cookie;
  596         if (pin >= io->io_numintr)
  597                 return (-1);
  598         return (io->io_pins[pin].io_vector);
  599 }
  600 
  601 int
  602 ioapic_disable_pin(void *cookie, u_int pin)
  603 {
  604         struct ioapic *io;
  605 
  606         io = (struct ioapic *)cookie;
  607         if (pin >= io->io_numintr)
  608                 return (EINVAL);
  609         if (io->io_pins[pin].io_vector == VECTOR_DISABLED)
  610                 return (EINVAL);
  611         io->io_pins[pin].io_vector = VECTOR_DISABLED;
  612         if (bootverbose)
  613                 printf("ioapic%u: intpin %d disabled\n", io->io_id, pin);
  614         return (0);
  615 }
  616 
  617 int
  618 ioapic_remap_vector(void *cookie, u_int pin, int vector)
  619 {
  620         struct ioapic *io;
  621 
  622         io = (struct ioapic *)cookie;
  623         if (pin >= io->io_numintr || vector < 0)
  624                 return (EINVAL);
  625         if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
  626                 return (EINVAL);
  627         io->io_pins[pin].io_vector = vector;
  628         if (bootverbose)
  629                 printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id,
  630                     vector, pin);
  631         return (0);
  632 }
  633 
  634 int
  635 ioapic_set_bus(void *cookie, u_int pin, int bus_type)
  636 {
  637         struct ioapic *io;
  638 
  639         if (bus_type < 0 || bus_type > APIC_BUS_MAX)
  640                 return (EINVAL);
  641         io = (struct ioapic *)cookie;
  642         if (pin >= io->io_numintr)
  643                 return (EINVAL);
  644         if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
  645                 return (EINVAL);
  646         io->io_pins[pin].io_bus = bus_type;
  647         if (bootverbose)
  648                 printf("ioapic%u: intpin %d bus %s\n", io->io_id, pin,
  649                     ioapic_bus_string(bus_type));
  650         return (0);
  651 }
  652 
  653 int
  654 ioapic_set_nmi(void *cookie, u_int pin)
  655 {
  656         struct ioapic *io;
  657 
  658         io = (struct ioapic *)cookie;
  659         if (pin >= io->io_numintr)
  660                 return (EINVAL);
  661         if (io->io_pins[pin].io_vector == VECTOR_NMI)
  662                 return (0);
  663         if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
  664                 return (EINVAL);
  665         io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
  666         io->io_pins[pin].io_vector = VECTOR_NMI;
  667         io->io_pins[pin].io_masked = 0;
  668         io->io_pins[pin].io_edgetrigger = 1;
  669         io->io_pins[pin].io_activehi = 1;
  670         if (bootverbose)
  671                 printf("ioapic%u: Routing NMI -> intpin %d\n",
  672                     io->io_id, pin);
  673         return (0);
  674 }
  675 
  676 int
  677 ioapic_set_smi(void *cookie, u_int pin)
  678 {
  679         struct ioapic *io;
  680 
  681         io = (struct ioapic *)cookie;
  682         if (pin >= io->io_numintr)
  683                 return (EINVAL);
  684         if (io->io_pins[pin].io_vector == VECTOR_SMI)
  685                 return (0);
  686         if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
  687                 return (EINVAL);
  688         io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
  689         io->io_pins[pin].io_vector = VECTOR_SMI;
  690         io->io_pins[pin].io_masked = 0;
  691         io->io_pins[pin].io_edgetrigger = 1;
  692         io->io_pins[pin].io_activehi = 1;
  693         if (bootverbose)
  694                 printf("ioapic%u: Routing SMI -> intpin %d\n",
  695                     io->io_id, pin);
  696         return (0);
  697 }
  698 
  699 int
  700 ioapic_set_extint(void *cookie, u_int pin)
  701 {
  702         struct ioapic *io;
  703 
  704         io = (struct ioapic *)cookie;
  705         if (pin >= io->io_numintr)
  706                 return (EINVAL);
  707         if (io->io_pins[pin].io_vector == VECTOR_EXTINT)
  708                 return (0);
  709         if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
  710                 return (EINVAL);
  711         io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
  712         io->io_pins[pin].io_vector = VECTOR_EXTINT;
  713 
  714         /* Enable this pin if mixed mode is available and active. */
  715         if (mixed_mode_enabled && mixed_mode_active)
  716                 io->io_pins[pin].io_masked = 0;
  717         else
  718                 io->io_pins[pin].io_masked = 1;
  719         io->io_pins[pin].io_edgetrigger = 1;
  720         io->io_pins[pin].io_activehi = 1;
  721         if (bootverbose)
  722                 printf("ioapic%u: Routing external 8259A's -> intpin %d\n",
  723                     io->io_id, pin);
  724         return (0);
  725 }
  726 
  727 int
  728 ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol)
  729 {
  730         struct ioapic *io;
  731 
  732         io = (struct ioapic *)cookie;
  733         if (pin >= io->io_numintr || pol == INTR_POLARITY_CONFORM)
  734                 return (EINVAL);
  735         if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
  736                 return (EINVAL);
  737         io->io_pins[pin].io_activehi = (pol == INTR_POLARITY_HIGH);
  738         if (bootverbose)
  739                 printf("ioapic%u: intpin %d polarity: %s\n", io->io_id, pin,
  740                     pol == INTR_POLARITY_HIGH ? "high" : "low");
  741         return (0);
  742 }
  743 
  744 int
  745 ioapic_set_triggermode(void *cookie, u_int pin, enum intr_trigger trigger)
  746 {
  747         struct ioapic *io;
  748 
  749         io = (struct ioapic *)cookie;
  750         if (pin >= io->io_numintr || trigger == INTR_TRIGGER_CONFORM)
  751                 return (EINVAL);
  752         if (io->io_pins[pin].io_vector >= NUM_IO_INTS)
  753                 return (EINVAL);
  754         io->io_pins[pin].io_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
  755         if (bootverbose)
  756                 printf("ioapic%u: intpin %d trigger: %s\n", io->io_id, pin,
  757                     trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
  758         return (0);
  759 }
  760 
  761 /*
  762  * Register a complete I/O APIC object with the interrupt subsystem.
  763  */
  764 void
  765 ioapic_register(void *cookie)
  766 {
  767         struct ioapic_intsrc *pin;
  768         struct ioapic *io;
  769         volatile ioapic_t *apic;
  770         uint32_t flags;
  771         int i;
  772 
  773         io = (struct ioapic *)cookie;
  774         apic = io->io_addr;
  775         mtx_lock_spin(&icu_lock);
  776         flags = ioapic_read(apic, IOAPIC_VER) & IOART_VER_VERSION;
  777         STAILQ_INSERT_TAIL(&ioapic_list, io, io_next);
  778         mtx_unlock_spin(&icu_lock);
  779         printf("ioapic%u <Version %u.%u> irqs %u-%u on motherboard\n",
  780             io->io_id, flags >> 4, flags & 0xf, io->io_intbase,
  781             io->io_intbase + io->io_numintr - 1);
  782         bsp_id = PCPU_GET(apic_id);
  783         for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) {
  784                 /*
  785                  * Finish initializing the pins by programming the vectors
  786                  * and delivery mode.
  787                  */
  788                 if (pin->io_vector == VECTOR_DISABLED)
  789                         continue;
  790                 ioapic_program_intpin(pin);
  791                 if (pin->io_vector >= NUM_IO_INTS)
  792                         continue;
  793                 /*
  794                  * Route IRQ0 via the 8259A using mixed mode if mixed mode
  795                  * is available and turned on.
  796                  */
  797                 if (pin->io_vector == 0 && mixed_mode_active &&
  798                     mixed_mode_enabled)
  799                         ioapic_setup_mixed_mode(pin);
  800                 else
  801                         intr_register_source(&pin->io_intsrc);
  802         }
  803 }
  804 
  805 /*
  806  * Program all the intpins to use logical destinations once the AP's
  807  * have been launched.
  808  */
  809 static void
  810 ioapic_set_logical_destinations(void *arg __unused)
  811 {
  812         struct ioapic *io;
  813         int i;
  814 
  815         program_logical_dest = 1;
  816         STAILQ_FOREACH(io, &ioapic_list, io_next)
  817             for (i = 0; i < io->io_numintr; i++)
  818                     if (io->io_pins[i].io_dest != DEST_NONE &&
  819                         io->io_pins[i].io_dest != DEST_EXTINT)
  820                             ioapic_program_destination(&io->io_pins[i]);
  821 }
  822 SYSINIT(ioapic_destinations, SI_SUB_SMP, SI_ORDER_SECOND,
  823     ioapic_set_logical_destinations, NULL)
  824 
  825 /*
  826  * Support for mixed-mode interrupt sources.  These sources route an ISA
  827  * IRQ through the 8259A's via the ExtINT on pin 0 of the I/O APIC that
  828  * routes the ISA interrupts.  We just ignore the intpins that use this
  829  * mode and allow the atpic driver to register its interrupt source for
  830  * that IRQ instead.
  831  */
  832 
  833 static void
  834 ioapic_setup_mixed_mode(struct ioapic_intsrc *intpin)
  835 {
  836         struct ioapic_intsrc *extint;
  837         struct ioapic *io;
  838 
  839         /*
  840          * Mark the associated I/O APIC intpin as being delivered via
  841          * ExtINT and enable the ExtINT pin on the I/O APIC if needed.
  842          */
  843         intpin->io_dest = DEST_EXTINT;
  844         io = (struct ioapic *)intpin->io_intsrc.is_pic;
  845         extint = &io->io_pins[0];
  846         if (extint->io_vector != VECTOR_EXTINT)
  847                 panic("Can't find ExtINT pin to route through!");
  848 #ifdef ENABLE_EXTINT_LOGICAL_DESTINATION
  849         if (extint->io_dest == DEST_NONE)
  850                 ioapic_assign_cluster(extint);
  851 #endif
  852 }

Cache object: 95cf4e2be11323118b9be8a6097491fa


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.