1 /*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD: releng/8.1/sys/amd64/amd64/io_apic.c 195415 2009-07-06 18:23:00Z jhb $");
32
33 #include "opt_isa.h"
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/bus.h>
38 #include <sys/kernel.h>
39 #include <sys/lock.h>
40 #include <sys/malloc.h>
41 #include <sys/module.h>
42 #include <sys/mutex.h>
43 #include <sys/sysctl.h>
44
45 #include <dev/pci/pcireg.h>
46 #include <dev/pci/pcivar.h>
47
48 #include <vm/vm.h>
49 #include <vm/pmap.h>
50
51 #include <machine/apicreg.h>
52 #include <machine/frame.h>
53 #include <machine/intr_machdep.h>
54 #include <machine/apicvar.h>
55 #include <machine/resource.h>
56 #include <machine/segments.h>
57
58 #define IOAPIC_ISA_INTS 16
59 #define IOAPIC_MEM_REGION 32
60 #define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2)
61 #define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1)
62
63 #define IRQ_EXTINT (NUM_IO_INTS + 1)
64 #define IRQ_NMI (NUM_IO_INTS + 2)
65 #define IRQ_SMI (NUM_IO_INTS + 3)
66 #define IRQ_DISABLED (NUM_IO_INTS + 4)
67
68 static MALLOC_DEFINE(M_IOAPIC, "io_apic", "I/O APIC structures");
69
70 /*
71 * I/O APIC interrupt source driver. Each pin is assigned an IRQ cookie
72 * as laid out in the ACPI System Interrupt number model where each I/O
73 * APIC has a contiguous chunk of the System Interrupt address space.
74 * We assume that IRQs 1 - 15 behave like ISA IRQs and that all other
75 * IRQs behave as PCI IRQs by default. We also assume that the pin for
76 * IRQ 0 is actually an ExtINT pin. The apic enumerators override the
77 * configuration of individual pins as indicated by their tables.
78 *
79 * Documentation for the I/O APIC: "82093AA I/O Advanced Programmable
80 * Interrupt Controller (IOAPIC)", May 1996, Intel Corp.
81 * ftp://download.intel.com/design/chipsets/datashts/29056601.pdf
82 */
83
84 struct ioapic_intsrc {
85 struct intsrc io_intsrc;
86 u_int io_irq;
87 u_int io_intpin:8;
88 u_int io_vector:8;
89 u_int io_cpu:8;
90 u_int io_activehi:1;
91 u_int io_edgetrigger:1;
92 u_int io_masked:1;
93 int io_bus:4;
94 uint32_t io_lowreg;
95 };
96
97 struct ioapic {
98 struct pic io_pic;
99 u_int io_id:8; /* logical ID */
100 u_int io_apic_id:4;
101 u_int io_intbase:8; /* System Interrupt base */
102 u_int io_numintr:8;
103 volatile ioapic_t *io_addr; /* XXX: should use bus_space */
104 vm_paddr_t io_paddr;
105 STAILQ_ENTRY(ioapic) io_next;
106 struct ioapic_intsrc io_pins[0];
107 };
108
109 static u_int ioapic_read(volatile ioapic_t *apic, int reg);
110 static void ioapic_write(volatile ioapic_t *apic, int reg, u_int val);
111 static const char *ioapic_bus_string(int bus_type);
112 static void ioapic_print_irq(struct ioapic_intsrc *intpin);
113 static void ioapic_enable_source(struct intsrc *isrc);
114 static void ioapic_disable_source(struct intsrc *isrc, int eoi);
115 static void ioapic_eoi_source(struct intsrc *isrc);
116 static void ioapic_enable_intr(struct intsrc *isrc);
117 static void ioapic_disable_intr(struct intsrc *isrc);
118 static int ioapic_vector(struct intsrc *isrc);
119 static int ioapic_source_pending(struct intsrc *isrc);
120 static int ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
121 enum intr_polarity pol);
122 static void ioapic_resume(struct pic *pic);
123 static int ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id);
124 static void ioapic_program_intpin(struct ioapic_intsrc *intpin);
125
126 static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list);
127 struct pic ioapic_template = { ioapic_enable_source, ioapic_disable_source,
128 ioapic_eoi_source, ioapic_enable_intr,
129 ioapic_disable_intr, ioapic_vector,
130 ioapic_source_pending, NULL, ioapic_resume,
131 ioapic_config_intr, ioapic_assign_cpu };
132
133 static int next_ioapic_base;
134 static u_int next_id;
135
136 SYSCTL_NODE(_hw, OID_AUTO, apic, CTLFLAG_RD, 0, "APIC options");
137 static int enable_extint;
138 SYSCTL_INT(_hw_apic, OID_AUTO, enable_extint, CTLFLAG_RDTUN, &enable_extint, 0,
139 "Enable the ExtINT pin in the first I/O APIC");
140 TUNABLE_INT("hw.apic.enable_extint", &enable_extint);
141
142 static __inline void
143 _ioapic_eoi_source(struct intsrc *isrc)
144 {
145 lapic_eoi();
146 }
147
148 static u_int
149 ioapic_read(volatile ioapic_t *apic, int reg)
150 {
151
152 mtx_assert(&icu_lock, MA_OWNED);
153 apic->ioregsel = reg;
154 return (apic->iowin);
155 }
156
157 static void
158 ioapic_write(volatile ioapic_t *apic, int reg, u_int val)
159 {
160
161 mtx_assert(&icu_lock, MA_OWNED);
162 apic->ioregsel = reg;
163 apic->iowin = val;
164 }
165
166 static const char *
167 ioapic_bus_string(int bus_type)
168 {
169
170 switch (bus_type) {
171 case APIC_BUS_ISA:
172 return ("ISA");
173 case APIC_BUS_EISA:
174 return ("EISA");
175 case APIC_BUS_PCI:
176 return ("PCI");
177 default:
178 return ("unknown");
179 }
180 }
181
182 static void
183 ioapic_print_irq(struct ioapic_intsrc *intpin)
184 {
185
186 switch (intpin->io_irq) {
187 case IRQ_DISABLED:
188 printf("disabled");
189 break;
190 case IRQ_EXTINT:
191 printf("ExtINT");
192 break;
193 case IRQ_NMI:
194 printf("NMI");
195 break;
196 case IRQ_SMI:
197 printf("SMI");
198 break;
199 default:
200 printf("%s IRQ %u", ioapic_bus_string(intpin->io_bus),
201 intpin->io_irq);
202 }
203 }
204
205 static void
206 ioapic_enable_source(struct intsrc *isrc)
207 {
208 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
209 struct ioapic *io = (struct ioapic *)isrc->is_pic;
210 uint32_t flags;
211
212 mtx_lock_spin(&icu_lock);
213 if (intpin->io_masked) {
214 flags = intpin->io_lowreg & ~IOART_INTMASK;
215 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
216 flags);
217 intpin->io_masked = 0;
218 }
219 mtx_unlock_spin(&icu_lock);
220 }
221
222 static void
223 ioapic_disable_source(struct intsrc *isrc, int eoi)
224 {
225 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
226 struct ioapic *io = (struct ioapic *)isrc->is_pic;
227 uint32_t flags;
228
229 mtx_lock_spin(&icu_lock);
230 if (!intpin->io_masked && !intpin->io_edgetrigger) {
231 flags = intpin->io_lowreg | IOART_INTMSET;
232 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin),
233 flags);
234 intpin->io_masked = 1;
235 }
236
237 if (eoi == PIC_EOI)
238 _ioapic_eoi_source(isrc);
239
240 mtx_unlock_spin(&icu_lock);
241 }
242
243 static void
244 ioapic_eoi_source(struct intsrc *isrc)
245 {
246
247 _ioapic_eoi_source(isrc);
248 }
249
250 /*
251 * Completely program an intpin based on the data in its interrupt source
252 * structure.
253 */
254 static void
255 ioapic_program_intpin(struct ioapic_intsrc *intpin)
256 {
257 struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
258 uint32_t low, high, value;
259
260 /*
261 * If a pin is completely invalid or if it is valid but hasn't
262 * been enabled yet, just ensure that the pin is masked.
263 */
264 if (intpin->io_irq == IRQ_DISABLED || (intpin->io_irq < NUM_IO_INTS &&
265 intpin->io_vector == 0)) {
266 mtx_lock_spin(&icu_lock);
267 low = ioapic_read(io->io_addr,
268 IOAPIC_REDTBL_LO(intpin->io_intpin));
269 if ((low & IOART_INTMASK) == IOART_INTMCLR)
270 ioapic_write(io->io_addr,
271 IOAPIC_REDTBL_LO(intpin->io_intpin),
272 low | IOART_INTMSET);
273 mtx_unlock_spin(&icu_lock);
274 return;
275 }
276
277 /* Set the destination. */
278 low = IOART_DESTPHY;
279 high = intpin->io_cpu << APIC_ID_SHIFT;
280
281 /* Program the rest of the low word. */
282 if (intpin->io_edgetrigger)
283 low |= IOART_TRGREDG;
284 else
285 low |= IOART_TRGRLVL;
286 if (intpin->io_activehi)
287 low |= IOART_INTAHI;
288 else
289 low |= IOART_INTALO;
290 if (intpin->io_masked)
291 low |= IOART_INTMSET;
292 switch (intpin->io_irq) {
293 case IRQ_EXTINT:
294 KASSERT(intpin->io_edgetrigger,
295 ("ExtINT not edge triggered"));
296 low |= IOART_DELEXINT;
297 break;
298 case IRQ_NMI:
299 KASSERT(intpin->io_edgetrigger,
300 ("NMI not edge triggered"));
301 low |= IOART_DELNMI;
302 break;
303 case IRQ_SMI:
304 KASSERT(intpin->io_edgetrigger,
305 ("SMI not edge triggered"));
306 low |= IOART_DELSMI;
307 break;
308 default:
309 KASSERT(intpin->io_vector != 0, ("No vector for IRQ %u",
310 intpin->io_irq));
311 low |= IOART_DELFIXED | intpin->io_vector;
312 }
313
314 /* Write the values to the APIC. */
315 mtx_lock_spin(&icu_lock);
316 intpin->io_lowreg = low;
317 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low);
318 value = ioapic_read(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin));
319 value &= ~IOART_DEST;
320 value |= high;
321 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), value);
322 mtx_unlock_spin(&icu_lock);
323 }
324
325 static int
326 ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id)
327 {
328 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
329 struct ioapic *io = (struct ioapic *)isrc->is_pic;
330 u_int old_vector, new_vector;
331 u_int old_id;
332
333 /*
334 * keep 1st core as the destination for NMI
335 */
336 if (intpin->io_irq == IRQ_NMI)
337 apic_id = 0;
338
339 /*
340 * Set us up to free the old irq.
341 */
342 old_vector = intpin->io_vector;
343 old_id = intpin->io_cpu;
344 if (old_vector && apic_id == old_id)
345 return (0);
346
347 /*
348 * Allocate an APIC vector for this interrupt pin. Once
349 * we have a vector we program the interrupt pin.
350 */
351 new_vector = apic_alloc_vector(apic_id, intpin->io_irq);
352 if (new_vector == 0)
353 return (ENOSPC);
354
355 intpin->io_cpu = apic_id;
356 intpin->io_vector = new_vector;
357 if (isrc->is_handlers > 0)
358 apic_enable_vector(intpin->io_cpu, intpin->io_vector);
359 if (bootverbose) {
360 printf("ioapic%u: routing intpin %u (", io->io_id,
361 intpin->io_intpin);
362 ioapic_print_irq(intpin);
363 printf(") to lapic %u vector %u\n", intpin->io_cpu,
364 intpin->io_vector);
365 }
366 ioapic_program_intpin(intpin);
367 /*
368 * Free the old vector after the new one is established. This is done
369 * to prevent races where we could miss an interrupt.
370 */
371 if (old_vector) {
372 if (isrc->is_handlers > 0)
373 apic_disable_vector(old_id, old_vector);
374 apic_free_vector(old_id, old_vector, intpin->io_irq);
375 }
376 return (0);
377 }
378
379 static void
380 ioapic_enable_intr(struct intsrc *isrc)
381 {
382 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
383
384 if (intpin->io_vector == 0)
385 if (ioapic_assign_cpu(isrc, intr_next_cpu()) != 0)
386 panic("Couldn't find an APIC vector for IRQ %d",
387 intpin->io_irq);
388 apic_enable_vector(intpin->io_cpu, intpin->io_vector);
389 }
390
391
392 static void
393 ioapic_disable_intr(struct intsrc *isrc)
394 {
395 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
396 u_int vector;
397
398 if (intpin->io_vector != 0) {
399 /* Mask this interrupt pin and free its APIC vector. */
400 vector = intpin->io_vector;
401 apic_disable_vector(intpin->io_cpu, vector);
402 intpin->io_masked = 1;
403 intpin->io_vector = 0;
404 ioapic_program_intpin(intpin);
405 apic_free_vector(intpin->io_cpu, vector, intpin->io_irq);
406 }
407 }
408
409 static int
410 ioapic_vector(struct intsrc *isrc)
411 {
412 struct ioapic_intsrc *pin;
413
414 pin = (struct ioapic_intsrc *)isrc;
415 return (pin->io_irq);
416 }
417
418 static int
419 ioapic_source_pending(struct intsrc *isrc)
420 {
421 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
422
423 if (intpin->io_vector == 0)
424 return 0;
425 return (lapic_intr_pending(intpin->io_vector));
426 }
427
428 static int
429 ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
430 enum intr_polarity pol)
431 {
432 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
433 struct ioapic *io = (struct ioapic *)isrc->is_pic;
434 int changed;
435
436 KASSERT(!(trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM),
437 ("%s: Conforming trigger or polarity\n", __func__));
438
439 /*
440 * EISA interrupts always use active high polarity, so don't allow
441 * them to be set to active low.
442 *
443 * XXX: Should we write to the ELCR if the trigger mode changes for
444 * an EISA IRQ or an ISA IRQ with the ELCR present?
445 */
446 if (intpin->io_bus == APIC_BUS_EISA)
447 pol = INTR_POLARITY_HIGH;
448 changed = 0;
449 if (intpin->io_edgetrigger != (trig == INTR_TRIGGER_EDGE)) {
450 if (bootverbose)
451 printf("ioapic%u: Changing trigger for pin %u to %s\n",
452 io->io_id, intpin->io_intpin,
453 trig == INTR_TRIGGER_EDGE ? "edge" : "level");
454 intpin->io_edgetrigger = (trig == INTR_TRIGGER_EDGE);
455 changed++;
456 }
457 if (intpin->io_activehi != (pol == INTR_POLARITY_HIGH)) {
458 if (bootverbose)
459 printf("ioapic%u: Changing polarity for pin %u to %s\n",
460 io->io_id, intpin->io_intpin,
461 pol == INTR_POLARITY_HIGH ? "high" : "low");
462 intpin->io_activehi = (pol == INTR_POLARITY_HIGH);
463 changed++;
464 }
465 if (changed)
466 ioapic_program_intpin(intpin);
467 return (0);
468 }
469
470 static void
471 ioapic_resume(struct pic *pic)
472 {
473 struct ioapic *io = (struct ioapic *)pic;
474 int i;
475
476 for (i = 0; i < io->io_numintr; i++)
477 ioapic_program_intpin(&io->io_pins[i]);
478 }
479
480 /*
481 * Create a plain I/O APIC object.
482 */
483 void *
484 ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase)
485 {
486 struct ioapic *io;
487 struct ioapic_intsrc *intpin;
488 volatile ioapic_t *apic;
489 u_int numintr, i;
490 uint32_t value;
491
492 /* Map the register window so we can access the device. */
493 apic = pmap_mapdev(addr, IOAPIC_MEM_REGION);
494 mtx_lock_spin(&icu_lock);
495 value = ioapic_read(apic, IOAPIC_VER);
496 mtx_unlock_spin(&icu_lock);
497
498 /* If it's version register doesn't seem to work, punt. */
499 if (value == 0xffffffff) {
500 pmap_unmapdev((vm_offset_t)apic, IOAPIC_MEM_REGION);
501 return (NULL);
502 }
503
504 /* Determine the number of vectors and set the APIC ID. */
505 numintr = ((value & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1;
506 io = malloc(sizeof(struct ioapic) +
507 numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK);
508 io->io_pic = ioapic_template;
509 mtx_lock_spin(&icu_lock);
510 io->io_id = next_id++;
511 io->io_apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT;
512 if (apic_id != -1 && io->io_apic_id != apic_id) {
513 ioapic_write(apic, IOAPIC_ID, apic_id << APIC_ID_SHIFT);
514 mtx_unlock_spin(&icu_lock);
515 io->io_apic_id = apic_id;
516 printf("ioapic%u: Changing APIC ID to %d\n", io->io_id,
517 apic_id);
518 } else
519 mtx_unlock_spin(&icu_lock);
520 if (intbase == -1) {
521 intbase = next_ioapic_base;
522 printf("ioapic%u: Assuming intbase of %d\n", io->io_id,
523 intbase);
524 } else if (intbase != next_ioapic_base && bootverbose)
525 printf("ioapic%u: WARNING: intbase %d != expected base %d\n",
526 io->io_id, intbase, next_ioapic_base);
527 io->io_intbase = intbase;
528 next_ioapic_base = intbase + numintr;
529 io->io_numintr = numintr;
530 io->io_addr = apic;
531 io->io_paddr = addr;
532
533 /*
534 * Initialize pins. Start off with interrupts disabled. Default
535 * to active-hi and edge-triggered for ISA interrupts and active-lo
536 * and level-triggered for all others.
537 */
538 bzero(io->io_pins, sizeof(struct ioapic_intsrc) * numintr);
539 mtx_lock_spin(&icu_lock);
540 for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) {
541 intpin->io_intsrc.is_pic = (struct pic *)io;
542 intpin->io_intpin = i;
543 intpin->io_irq = intbase + i;
544
545 /*
546 * Assume that pin 0 on the first I/O APIC is an ExtINT pin.
547 * Assume that pins 1-15 are ISA interrupts and that all
548 * other pins are PCI interrupts.
549 */
550 if (intpin->io_irq == 0)
551 ioapic_set_extint(io, i);
552 else if (intpin->io_irq < IOAPIC_ISA_INTS) {
553 intpin->io_bus = APIC_BUS_ISA;
554 intpin->io_activehi = 1;
555 intpin->io_edgetrigger = 1;
556 intpin->io_masked = 1;
557 } else {
558 intpin->io_bus = APIC_BUS_PCI;
559 intpin->io_activehi = 0;
560 intpin->io_edgetrigger = 0;
561 intpin->io_masked = 1;
562 }
563
564 /*
565 * Route interrupts to the BSP by default. Interrupts may
566 * be routed to other CPUs later after they are enabled.
567 */
568 intpin->io_cpu = PCPU_GET(apic_id);
569 value = ioapic_read(apic, IOAPIC_REDTBL_LO(i));
570 ioapic_write(apic, IOAPIC_REDTBL_LO(i), value | IOART_INTMSET);
571 }
572 mtx_unlock_spin(&icu_lock);
573
574 return (io);
575 }
576
577 int
578 ioapic_get_vector(void *cookie, u_int pin)
579 {
580 struct ioapic *io;
581
582 io = (struct ioapic *)cookie;
583 if (pin >= io->io_numintr)
584 return (-1);
585 return (io->io_pins[pin].io_irq);
586 }
587
588 int
589 ioapic_disable_pin(void *cookie, u_int pin)
590 {
591 struct ioapic *io;
592
593 io = (struct ioapic *)cookie;
594 if (pin >= io->io_numintr)
595 return (EINVAL);
596 if (io->io_pins[pin].io_irq == IRQ_DISABLED)
597 return (EINVAL);
598 io->io_pins[pin].io_irq = IRQ_DISABLED;
599 if (bootverbose)
600 printf("ioapic%u: intpin %d disabled\n", io->io_id, pin);
601 return (0);
602 }
603
604 int
605 ioapic_remap_vector(void *cookie, u_int pin, int vector)
606 {
607 struct ioapic *io;
608
609 io = (struct ioapic *)cookie;
610 if (pin >= io->io_numintr || vector < 0)
611 return (EINVAL);
612 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
613 return (EINVAL);
614 io->io_pins[pin].io_irq = vector;
615 if (bootverbose)
616 printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id,
617 vector, pin);
618 return (0);
619 }
620
621 int
622 ioapic_set_bus(void *cookie, u_int pin, int bus_type)
623 {
624 struct ioapic *io;
625
626 if (bus_type < 0 || bus_type > APIC_BUS_MAX)
627 return (EINVAL);
628 io = (struct ioapic *)cookie;
629 if (pin >= io->io_numintr)
630 return (EINVAL);
631 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
632 return (EINVAL);
633 if (io->io_pins[pin].io_bus == bus_type)
634 return (0);
635 io->io_pins[pin].io_bus = bus_type;
636 if (bootverbose)
637 printf("ioapic%u: intpin %d bus %s\n", io->io_id, pin,
638 ioapic_bus_string(bus_type));
639 return (0);
640 }
641
642 int
643 ioapic_set_nmi(void *cookie, u_int pin)
644 {
645 struct ioapic *io;
646
647 io = (struct ioapic *)cookie;
648 if (pin >= io->io_numintr)
649 return (EINVAL);
650 if (io->io_pins[pin].io_irq == IRQ_NMI)
651 return (0);
652 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
653 return (EINVAL);
654 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
655 io->io_pins[pin].io_irq = IRQ_NMI;
656 io->io_pins[pin].io_masked = 0;
657 io->io_pins[pin].io_edgetrigger = 1;
658 io->io_pins[pin].io_activehi = 1;
659 if (bootverbose)
660 printf("ioapic%u: Routing NMI -> intpin %d\n",
661 io->io_id, pin);
662 return (0);
663 }
664
665 int
666 ioapic_set_smi(void *cookie, u_int pin)
667 {
668 struct ioapic *io;
669
670 io = (struct ioapic *)cookie;
671 if (pin >= io->io_numintr)
672 return (EINVAL);
673 if (io->io_pins[pin].io_irq == IRQ_SMI)
674 return (0);
675 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
676 return (EINVAL);
677 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
678 io->io_pins[pin].io_irq = IRQ_SMI;
679 io->io_pins[pin].io_masked = 0;
680 io->io_pins[pin].io_edgetrigger = 1;
681 io->io_pins[pin].io_activehi = 1;
682 if (bootverbose)
683 printf("ioapic%u: Routing SMI -> intpin %d\n",
684 io->io_id, pin);
685 return (0);
686 }
687
688 int
689 ioapic_set_extint(void *cookie, u_int pin)
690 {
691 struct ioapic *io;
692
693 io = (struct ioapic *)cookie;
694 if (pin >= io->io_numintr)
695 return (EINVAL);
696 if (io->io_pins[pin].io_irq == IRQ_EXTINT)
697 return (0);
698 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
699 return (EINVAL);
700 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
701 io->io_pins[pin].io_irq = IRQ_EXTINT;
702 if (enable_extint)
703 io->io_pins[pin].io_masked = 0;
704 else
705 io->io_pins[pin].io_masked = 1;
706 io->io_pins[pin].io_edgetrigger = 1;
707 io->io_pins[pin].io_activehi = 1;
708 if (bootverbose)
709 printf("ioapic%u: Routing external 8259A's -> intpin %d\n",
710 io->io_id, pin);
711 return (0);
712 }
713
714 int
715 ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol)
716 {
717 struct ioapic *io;
718 int activehi;
719
720 io = (struct ioapic *)cookie;
721 if (pin >= io->io_numintr || pol == INTR_POLARITY_CONFORM)
722 return (EINVAL);
723 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
724 return (EINVAL);
725 activehi = (pol == INTR_POLARITY_HIGH);
726 if (io->io_pins[pin].io_activehi == activehi)
727 return (0);
728 io->io_pins[pin].io_activehi = activehi;
729 if (bootverbose)
730 printf("ioapic%u: intpin %d polarity: %s\n", io->io_id, pin,
731 pol == INTR_POLARITY_HIGH ? "high" : "low");
732 return (0);
733 }
734
735 int
736 ioapic_set_triggermode(void *cookie, u_int pin, enum intr_trigger trigger)
737 {
738 struct ioapic *io;
739 int edgetrigger;
740
741 io = (struct ioapic *)cookie;
742 if (pin >= io->io_numintr || trigger == INTR_TRIGGER_CONFORM)
743 return (EINVAL);
744 if (io->io_pins[pin].io_irq >= NUM_IO_INTS)
745 return (EINVAL);
746 edgetrigger = (trigger == INTR_TRIGGER_EDGE);
747 if (io->io_pins[pin].io_edgetrigger == edgetrigger)
748 return (0);
749 io->io_pins[pin].io_edgetrigger = edgetrigger;
750 if (bootverbose)
751 printf("ioapic%u: intpin %d trigger: %s\n", io->io_id, pin,
752 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
753 return (0);
754 }
755
756 /*
757 * Register a complete I/O APIC object with the interrupt subsystem.
758 */
759 void
760 ioapic_register(void *cookie)
761 {
762 struct ioapic_intsrc *pin;
763 struct ioapic *io;
764 volatile ioapic_t *apic;
765 uint32_t flags;
766 int i;
767
768 io = (struct ioapic *)cookie;
769 apic = io->io_addr;
770 mtx_lock_spin(&icu_lock);
771 flags = ioapic_read(apic, IOAPIC_VER) & IOART_VER_VERSION;
772 STAILQ_INSERT_TAIL(&ioapic_list, io, io_next);
773 mtx_unlock_spin(&icu_lock);
774 printf("ioapic%u <Version %u.%u> irqs %u-%u on motherboard\n",
775 io->io_id, flags >> 4, flags & 0xf, io->io_intbase,
776 io->io_intbase + io->io_numintr - 1);
777
778 /* Register valid pins as interrupt sources. */
779 intr_register_pic(&io->io_pic);
780 for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++)
781 if (pin->io_irq < NUM_IO_INTS)
782 intr_register_source(&pin->io_intsrc);
783 }
784
785 /* A simple new-bus driver to consume PCI I/O APIC devices. */
786 static int
787 ioapic_pci_probe(device_t dev)
788 {
789
790 if (pci_get_class(dev) == PCIC_BASEPERIPH &&
791 pci_get_subclass(dev) == PCIS_BASEPERIPH_PIC) {
792 switch (pci_get_progif(dev)) {
793 case PCIP_BASEPERIPH_PIC_IO_APIC:
794 device_set_desc(dev, "IO APIC");
795 break;
796 case PCIP_BASEPERIPH_PIC_IOX_APIC:
797 device_set_desc(dev, "IO(x) APIC");
798 break;
799 default:
800 return (ENXIO);
801 }
802 device_quiet(dev);
803 return (-10000);
804 }
805 return (ENXIO);
806 }
807
808 static int
809 ioapic_pci_attach(device_t dev)
810 {
811
812 return (0);
813 }
814
815 static device_method_t ioapic_pci_methods[] = {
816 /* Device interface */
817 DEVMETHOD(device_probe, ioapic_pci_probe),
818 DEVMETHOD(device_attach, ioapic_pci_attach),
819
820 { 0, 0 }
821 };
822
823 DEFINE_CLASS_0(ioapic, ioapic_pci_driver, ioapic_pci_methods, 0);
824
825 static devclass_t ioapic_devclass;
826 DRIVER_MODULE(ioapic, pci, ioapic_pci_driver, ioapic_devclass, 0, 0);
827
828 /*
829 * A new-bus driver to consume the memory resources associated with
830 * the APICs in the system. On some systems ACPI or PnPBIOS system
831 * resource devices may already claim these resources. To keep from
832 * breaking those devices, we attach ourself to the nexus device after
833 * legacy0 and acpi0 and ignore any allocation failures.
834 */
835 static void
836 apic_identify(driver_t *driver, device_t parent)
837 {
838
839 /*
840 * Add at order 12. acpi0 is probed at order 10 and legacy0
841 * is probed at order 11.
842 */
843 if (lapic_paddr != 0)
844 BUS_ADD_CHILD(parent, 12, "apic", 0);
845 }
846
847 static int
848 apic_probe(device_t dev)
849 {
850
851 device_set_desc(dev, "APIC resources");
852 device_quiet(dev);
853 return (0);
854 }
855
856 static void
857 apic_add_resource(device_t dev, int rid, vm_paddr_t base, size_t length)
858 {
859 int error;
860
861 error = bus_set_resource(dev, SYS_RES_MEMORY, rid, base, length);
862 if (error)
863 panic("apic_add_resource: resource %d failed set with %d", rid,
864 error);
865 bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 0);
866 }
867
868 static int
869 apic_attach(device_t dev)
870 {
871 struct ioapic *io;
872 int i;
873
874 /* Reserve the local APIC. */
875 apic_add_resource(dev, 0, lapic_paddr, sizeof(lapic_t));
876 i = 1;
877 STAILQ_FOREACH(io, &ioapic_list, io_next) {
878 apic_add_resource(dev, i, io->io_paddr, IOAPIC_MEM_REGION);
879 i++;
880 }
881 return (0);
882 }
883
884 static device_method_t apic_methods[] = {
885 /* Device interface */
886 DEVMETHOD(device_identify, apic_identify),
887 DEVMETHOD(device_probe, apic_probe),
888 DEVMETHOD(device_attach, apic_attach),
889
890 { 0, 0 }
891 };
892
893 DEFINE_CLASS_0(apic, apic_driver, apic_methods, 0);
894
895 static devclass_t apic_devclass;
896 DRIVER_MODULE(apic, nexus, apic_driver, apic_devclass, 0, 0);
Cache object: e24ee69609838ee278bbbea720b8f86c
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