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sys/amd64/amd64/io_apic.c
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1 /*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD: releng/8.4/sys/amd64/amd64/io_apic.c 216923 2011-01-03 17:57:44Z jhb $"); 32 33 #include "opt_isa.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/sysctl.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 48 #include <vm/vm.h> 49 #include <vm/pmap.h> 50 51 #include <machine/apicreg.h> 52 #include <machine/frame.h> 53 #include <machine/intr_machdep.h> 54 #include <machine/apicvar.h> 55 #include <machine/resource.h> 56 #include <machine/segments.h> 57 58 #define IOAPIC_ISA_INTS 16 59 #define IOAPIC_MEM_REGION 32 60 #define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2) 61 #define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1) 62 63 #define IRQ_EXTINT (NUM_IO_INTS + 1) 64 #define IRQ_NMI (NUM_IO_INTS + 2) 65 #define IRQ_SMI (NUM_IO_INTS + 3) 66 #define IRQ_DISABLED (NUM_IO_INTS + 4) 67 68 static MALLOC_DEFINE(M_IOAPIC, "io_apic", "I/O APIC structures"); 69 70 /* 71 * I/O APIC interrupt source driver. Each pin is assigned an IRQ cookie 72 * as laid out in the ACPI System Interrupt number model where each I/O 73 * APIC has a contiguous chunk of the System Interrupt address space. 74 * We assume that IRQs 1 - 15 behave like ISA IRQs and that all other 75 * IRQs behave as PCI IRQs by default. We also assume that the pin for 76 * IRQ 0 is actually an ExtINT pin. The apic enumerators override the 77 * configuration of individual pins as indicated by their tables. 78 * 79 * Documentation for the I/O APIC: "82093AA I/O Advanced Programmable 80 * Interrupt Controller (IOAPIC)", May 1996, Intel Corp. 81 * ftp://download.intel.com/design/chipsets/datashts/29056601.pdf 82 */ 83 84 struct ioapic_intsrc { 85 struct intsrc io_intsrc; 86 u_int io_irq; 87 u_int io_intpin:8; 88 u_int io_vector:8; 89 u_int io_cpu:8; 90 u_int io_activehi:1; 91 u_int io_edgetrigger:1; 92 u_int io_masked:1; 93 int io_bus:4; 94 uint32_t io_lowreg; 95 }; 96 97 struct ioapic { 98 struct pic io_pic; 99 u_int io_id:8; /* logical ID */ 100 u_int io_apic_id:4; 101 u_int io_intbase:8; /* System Interrupt base */ 102 u_int io_numintr:8; 103 volatile ioapic_t *io_addr; /* XXX: should use bus_space */ 104 vm_paddr_t io_paddr; 105 STAILQ_ENTRY(ioapic) io_next; 106 struct ioapic_intsrc io_pins[0]; 107 }; 108 109 static u_int ioapic_read(volatile ioapic_t *apic, int reg); 110 static void ioapic_write(volatile ioapic_t *apic, int reg, u_int val); 111 static const char *ioapic_bus_string(int bus_type); 112 static void ioapic_print_irq(struct ioapic_intsrc *intpin); 113 static void ioapic_enable_source(struct intsrc *isrc); 114 static void ioapic_disable_source(struct intsrc *isrc, int eoi); 115 static void ioapic_eoi_source(struct intsrc *isrc); 116 static void ioapic_enable_intr(struct intsrc *isrc); 117 static void ioapic_disable_intr(struct intsrc *isrc); 118 static int ioapic_vector(struct intsrc *isrc); 119 static int ioapic_source_pending(struct intsrc *isrc); 120 static int ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig, 121 enum intr_polarity pol); 122 static void ioapic_resume(struct pic *pic); 123 static int ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id); 124 static void ioapic_program_intpin(struct ioapic_intsrc *intpin); 125 126 static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list); 127 struct pic ioapic_template = { ioapic_enable_source, ioapic_disable_source, 128 ioapic_eoi_source, ioapic_enable_intr, 129 ioapic_disable_intr, ioapic_vector, 130 ioapic_source_pending, NULL, ioapic_resume, 131 ioapic_config_intr, ioapic_assign_cpu }; 132 133 static int next_ioapic_base; 134 static u_int next_id; 135 136 SYSCTL_NODE(_hw, OID_AUTO, apic, CTLFLAG_RD, 0, "APIC options"); 137 static int enable_extint; 138 SYSCTL_INT(_hw_apic, OID_AUTO, enable_extint, CTLFLAG_RDTUN, &enable_extint, 0, 139 "Enable the ExtINT pin in the first I/O APIC"); 140 TUNABLE_INT("hw.apic.enable_extint", &enable_extint); 141 142 static __inline void 143 _ioapic_eoi_source(struct intsrc *isrc) 144 { 145 lapic_eoi(); 146 } 147 148 static u_int 149 ioapic_read(volatile ioapic_t *apic, int reg) 150 { 151 152 mtx_assert(&icu_lock, MA_OWNED); 153 apic->ioregsel = reg; 154 return (apic->iowin); 155 } 156 157 static void 158 ioapic_write(volatile ioapic_t *apic, int reg, u_int val) 159 { 160 161 mtx_assert(&icu_lock, MA_OWNED); 162 apic->ioregsel = reg; 163 apic->iowin = val; 164 } 165 166 static const char * 167 ioapic_bus_string(int bus_type) 168 { 169 170 switch (bus_type) { 171 case APIC_BUS_ISA: 172 return ("ISA"); 173 case APIC_BUS_EISA: 174 return ("EISA"); 175 case APIC_BUS_PCI: 176 return ("PCI"); 177 default: 178 return ("unknown"); 179 } 180 } 181 182 static void 183 ioapic_print_irq(struct ioapic_intsrc *intpin) 184 { 185 186 switch (intpin->io_irq) { 187 case IRQ_DISABLED: 188 printf("disabled"); 189 break; 190 case IRQ_EXTINT: 191 printf("ExtINT"); 192 break; 193 case IRQ_NMI: 194 printf("NMI"); 195 break; 196 case IRQ_SMI: 197 printf("SMI"); 198 break; 199 default: 200 printf("%s IRQ %u", ioapic_bus_string(intpin->io_bus), 201 intpin->io_irq); 202 } 203 } 204 205 static void 206 ioapic_enable_source(struct intsrc *isrc) 207 { 208 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 209 struct ioapic *io = (struct ioapic *)isrc->is_pic; 210 uint32_t flags; 211 212 mtx_lock_spin(&icu_lock); 213 if (intpin->io_masked) { 214 flags = intpin->io_lowreg & ~IOART_INTMASK; 215 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), 216 flags); 217 intpin->io_masked = 0; 218 } 219 mtx_unlock_spin(&icu_lock); 220 } 221 222 static void 223 ioapic_disable_source(struct intsrc *isrc, int eoi) 224 { 225 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 226 struct ioapic *io = (struct ioapic *)isrc->is_pic; 227 uint32_t flags; 228 229 mtx_lock_spin(&icu_lock); 230 if (!intpin->io_masked && !intpin->io_edgetrigger) { 231 flags = intpin->io_lowreg | IOART_INTMSET; 232 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), 233 flags); 234 intpin->io_masked = 1; 235 } 236 237 if (eoi == PIC_EOI) 238 _ioapic_eoi_source(isrc); 239 240 mtx_unlock_spin(&icu_lock); 241 } 242 243 static void 244 ioapic_eoi_source(struct intsrc *isrc) 245 { 246 247 _ioapic_eoi_source(isrc); 248 } 249 250 /* 251 * Completely program an intpin based on the data in its interrupt source 252 * structure. 253 */ 254 static void 255 ioapic_program_intpin(struct ioapic_intsrc *intpin) 256 { 257 struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic; 258 uint32_t low, high, value; 259 260 /* 261 * If a pin is completely invalid or if it is valid but hasn't 262 * been enabled yet, just ensure that the pin is masked. 263 */ 264 mtx_assert(&icu_lock, MA_OWNED); 265 if (intpin->io_irq == IRQ_DISABLED || (intpin->io_irq < NUM_IO_INTS && 266 intpin->io_vector == 0)) { 267 low = ioapic_read(io->io_addr, 268 IOAPIC_REDTBL_LO(intpin->io_intpin)); 269 if ((low & IOART_INTMASK) == IOART_INTMCLR) 270 ioapic_write(io->io_addr, 271 IOAPIC_REDTBL_LO(intpin->io_intpin), 272 low | IOART_INTMSET); 273 return; 274 } 275 276 /* Set the destination. */ 277 low = IOART_DESTPHY; 278 high = intpin->io_cpu << APIC_ID_SHIFT; 279 280 /* Program the rest of the low word. */ 281 if (intpin->io_edgetrigger) 282 low |= IOART_TRGREDG; 283 else 284 low |= IOART_TRGRLVL; 285 if (intpin->io_activehi) 286 low |= IOART_INTAHI; 287 else 288 low |= IOART_INTALO; 289 if (intpin->io_masked) 290 low |= IOART_INTMSET; 291 switch (intpin->io_irq) { 292 case IRQ_EXTINT: 293 KASSERT(intpin->io_edgetrigger, 294 ("ExtINT not edge triggered")); 295 low |= IOART_DELEXINT; 296 break; 297 case IRQ_NMI: 298 KASSERT(intpin->io_edgetrigger, 299 ("NMI not edge triggered")); 300 low |= IOART_DELNMI; 301 break; 302 case IRQ_SMI: 303 KASSERT(intpin->io_edgetrigger, 304 ("SMI not edge triggered")); 305 low |= IOART_DELSMI; 306 break; 307 default: 308 KASSERT(intpin->io_vector != 0, ("No vector for IRQ %u", 309 intpin->io_irq)); 310 low |= IOART_DELFIXED | intpin->io_vector; 311 } 312 313 /* Write the values to the APIC. */ 314 intpin->io_lowreg = low; 315 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low); 316 value = ioapic_read(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin)); 317 value &= ~IOART_DEST; 318 value |= high; 319 ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), value); 320 } 321 322 static int 323 ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id) 324 { 325 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 326 struct ioapic *io = (struct ioapic *)isrc->is_pic; 327 u_int old_vector, new_vector; 328 u_int old_id; 329 330 /* 331 * keep 1st core as the destination for NMI 332 */ 333 if (intpin->io_irq == IRQ_NMI) 334 apic_id = 0; 335 336 /* 337 * Set us up to free the old irq. 338 */ 339 old_vector = intpin->io_vector; 340 old_id = intpin->io_cpu; 341 if (old_vector && apic_id == old_id) 342 return (0); 343 344 /* 345 * Allocate an APIC vector for this interrupt pin. Once 346 * we have a vector we program the interrupt pin. 347 */ 348 new_vector = apic_alloc_vector(apic_id, intpin->io_irq); 349 if (new_vector == 0) 350 return (ENOSPC); 351 352 /* 353 * Mask the old intpin if it is enabled while it is migrated. 354 * 355 * At least some level-triggered interrupts seem to need the 356 * extra DELAY() to avoid being stuck in a non-EOI'd state. 357 */ 358 mtx_lock_spin(&icu_lock); 359 if (!intpin->io_masked && !intpin->io_edgetrigger) { 360 ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), 361 intpin->io_lowreg | IOART_INTMSET); 362 mtx_unlock_spin(&icu_lock); 363 DELAY(100); 364 mtx_lock_spin(&icu_lock); 365 } 366 367 intpin->io_cpu = apic_id; 368 intpin->io_vector = new_vector; 369 if (isrc->is_handlers > 0) 370 apic_enable_vector(intpin->io_cpu, intpin->io_vector); 371 if (bootverbose) { 372 printf("ioapic%u: routing intpin %u (", io->io_id, 373 intpin->io_intpin); 374 ioapic_print_irq(intpin); 375 printf(") to lapic %u vector %u\n", intpin->io_cpu, 376 intpin->io_vector); 377 } 378 ioapic_program_intpin(intpin); 379 mtx_unlock_spin(&icu_lock); 380 381 /* 382 * Free the old vector after the new one is established. This is done 383 * to prevent races where we could miss an interrupt. 384 */ 385 if (old_vector) { 386 if (isrc->is_handlers > 0) 387 apic_disable_vector(old_id, old_vector); 388 apic_free_vector(old_id, old_vector, intpin->io_irq); 389 } 390 return (0); 391 } 392 393 static void 394 ioapic_enable_intr(struct intsrc *isrc) 395 { 396 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 397 398 if (intpin->io_vector == 0) 399 if (ioapic_assign_cpu(isrc, intr_next_cpu()) != 0) 400 panic("Couldn't find an APIC vector for IRQ %d", 401 intpin->io_irq); 402 apic_enable_vector(intpin->io_cpu, intpin->io_vector); 403 } 404 405 406 static void 407 ioapic_disable_intr(struct intsrc *isrc) 408 { 409 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 410 u_int vector; 411 412 if (intpin->io_vector != 0) { 413 /* Mask this interrupt pin and free its APIC vector. */ 414 vector = intpin->io_vector; 415 apic_disable_vector(intpin->io_cpu, vector); 416 mtx_lock_spin(&icu_lock); 417 intpin->io_masked = 1; 418 intpin->io_vector = 0; 419 ioapic_program_intpin(intpin); 420 mtx_unlock_spin(&icu_lock); 421 apic_free_vector(intpin->io_cpu, vector, intpin->io_irq); 422 } 423 } 424 425 static int 426 ioapic_vector(struct intsrc *isrc) 427 { 428 struct ioapic_intsrc *pin; 429 430 pin = (struct ioapic_intsrc *)isrc; 431 return (pin->io_irq); 432 } 433 434 static int 435 ioapic_source_pending(struct intsrc *isrc) 436 { 437 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 438 439 if (intpin->io_vector == 0) 440 return 0; 441 return (lapic_intr_pending(intpin->io_vector)); 442 } 443 444 static int 445 ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig, 446 enum intr_polarity pol) 447 { 448 struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 449 struct ioapic *io = (struct ioapic *)isrc->is_pic; 450 int changed; 451 452 KASSERT(!(trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM), 453 ("%s: Conforming trigger or polarity\n", __func__)); 454 455 /* 456 * EISA interrupts always use active high polarity, so don't allow 457 * them to be set to active low. 458 * 459 * XXX: Should we write to the ELCR if the trigger mode changes for 460 * an EISA IRQ or an ISA IRQ with the ELCR present? 461 */ 462 mtx_lock_spin(&icu_lock); 463 if (intpin->io_bus == APIC_BUS_EISA) 464 pol = INTR_POLARITY_HIGH; 465 changed = 0; 466 if (intpin->io_edgetrigger != (trig == INTR_TRIGGER_EDGE)) { 467 if (bootverbose) 468 printf("ioapic%u: Changing trigger for pin %u to %s\n", 469 io->io_id, intpin->io_intpin, 470 trig == INTR_TRIGGER_EDGE ? "edge" : "level"); 471 intpin->io_edgetrigger = (trig == INTR_TRIGGER_EDGE); 472 changed++; 473 } 474 if (intpin->io_activehi != (pol == INTR_POLARITY_HIGH)) { 475 if (bootverbose) 476 printf("ioapic%u: Changing polarity for pin %u to %s\n", 477 io->io_id, intpin->io_intpin, 478 pol == INTR_POLARITY_HIGH ? "high" : "low"); 479 intpin->io_activehi = (pol == INTR_POLARITY_HIGH); 480 changed++; 481 } 482 if (changed) 483 ioapic_program_intpin(intpin); 484 mtx_unlock_spin(&icu_lock); 485 return (0); 486 } 487 488 static void 489 ioapic_resume(struct pic *pic) 490 { 491 struct ioapic *io = (struct ioapic *)pic; 492 int i; 493 494 mtx_lock_spin(&icu_lock); 495 for (i = 0; i < io->io_numintr; i++) 496 ioapic_program_intpin(&io->io_pins[i]); 497 mtx_unlock_spin(&icu_lock); 498 } 499 500 /* 501 * Create a plain I/O APIC object. 502 */ 503 void * 504 ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase) 505 { 506 struct ioapic *io; 507 struct ioapic_intsrc *intpin; 508 volatile ioapic_t *apic; 509 u_int numintr, i; 510 uint32_t value; 511 512 /* Map the register window so we can access the device. */ 513 apic = pmap_mapdev(addr, IOAPIC_MEM_REGION); 514 mtx_lock_spin(&icu_lock); 515 value = ioapic_read(apic, IOAPIC_VER); 516 mtx_unlock_spin(&icu_lock); 517 518 /* If it's version register doesn't seem to work, punt. */ 519 if (value == 0xffffffff) { 520 pmap_unmapdev((vm_offset_t)apic, IOAPIC_MEM_REGION); 521 return (NULL); 522 } 523 524 /* Determine the number of vectors and set the APIC ID. */ 525 numintr = ((value & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1; 526 io = malloc(sizeof(struct ioapic) + 527 numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK); 528 io->io_pic = ioapic_template; 529 mtx_lock_spin(&icu_lock); 530 io->io_id = next_id++; 531 io->io_apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT; 532 if (apic_id != -1 && io->io_apic_id != apic_id) { 533 ioapic_write(apic, IOAPIC_ID, apic_id << APIC_ID_SHIFT); 534 mtx_unlock_spin(&icu_lock); 535 io->io_apic_id = apic_id; 536 printf("ioapic%u: Changing APIC ID to %d\n", io->io_id, 537 apic_id); 538 } else 539 mtx_unlock_spin(&icu_lock); 540 if (intbase == -1) { 541 intbase = next_ioapic_base; 542 printf("ioapic%u: Assuming intbase of %d\n", io->io_id, 543 intbase); 544 } else if (intbase != next_ioapic_base && bootverbose) 545 printf("ioapic%u: WARNING: intbase %d != expected base %d\n", 546 io->io_id, intbase, next_ioapic_base); 547 io->io_intbase = intbase; 548 next_ioapic_base = intbase + numintr; 549 io->io_numintr = numintr; 550 io->io_addr = apic; 551 io->io_paddr = addr; 552 553 /* 554 * Initialize pins. Start off with interrupts disabled. Default 555 * to active-hi and edge-triggered for ISA interrupts and active-lo 556 * and level-triggered for all others. 557 */ 558 bzero(io->io_pins, sizeof(struct ioapic_intsrc) * numintr); 559 mtx_lock_spin(&icu_lock); 560 for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) { 561 intpin->io_intsrc.is_pic = (struct pic *)io; 562 intpin->io_intpin = i; 563 intpin->io_irq = intbase + i; 564 565 /* 566 * Assume that pin 0 on the first I/O APIC is an ExtINT pin. 567 * Assume that pins 1-15 are ISA interrupts and that all 568 * other pins are PCI interrupts. 569 */ 570 if (intpin->io_irq == 0) 571 ioapic_set_extint(io, i); 572 else if (intpin->io_irq < IOAPIC_ISA_INTS) { 573 intpin->io_bus = APIC_BUS_ISA; 574 intpin->io_activehi = 1; 575 intpin->io_edgetrigger = 1; 576 intpin->io_masked = 1; 577 } else { 578 intpin->io_bus = APIC_BUS_PCI; 579 intpin->io_activehi = 0; 580 intpin->io_edgetrigger = 0; 581 intpin->io_masked = 1; 582 } 583 584 /* 585 * Route interrupts to the BSP by default. Interrupts may 586 * be routed to other CPUs later after they are enabled. 587 */ 588 intpin->io_cpu = PCPU_GET(apic_id); 589 value = ioapic_read(apic, IOAPIC_REDTBL_LO(i)); 590 ioapic_write(apic, IOAPIC_REDTBL_LO(i), value | IOART_INTMSET); 591 } 592 mtx_unlock_spin(&icu_lock); 593 594 return (io); 595 } 596 597 int 598 ioapic_get_vector(void *cookie, u_int pin) 599 { 600 struct ioapic *io; 601 602 io = (struct ioapic *)cookie; 603 if (pin >= io->io_numintr) 604 return (-1); 605 return (io->io_pins[pin].io_irq); 606 } 607 608 int 609 ioapic_disable_pin(void *cookie, u_int pin) 610 { 611 struct ioapic *io; 612 613 io = (struct ioapic *)cookie; 614 if (pin >= io->io_numintr) 615 return (EINVAL); 616 if (io->io_pins[pin].io_irq == IRQ_DISABLED) 617 return (EINVAL); 618 io->io_pins[pin].io_irq = IRQ_DISABLED; 619 if (bootverbose) 620 printf("ioapic%u: intpin %d disabled\n", io->io_id, pin); 621 return (0); 622 } 623 624 int 625 ioapic_remap_vector(void *cookie, u_int pin, int vector) 626 { 627 struct ioapic *io; 628 629 io = (struct ioapic *)cookie; 630 if (pin >= io->io_numintr || vector < 0) 631 return (EINVAL); 632 if (io->io_pins[pin].io_irq >= NUM_IO_INTS) 633 return (EINVAL); 634 io->io_pins[pin].io_irq = vector; 635 if (bootverbose) 636 printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id, 637 vector, pin); 638 return (0); 639 } 640 641 int 642 ioapic_set_bus(void *cookie, u_int pin, int bus_type) 643 { 644 struct ioapic *io; 645 646 if (bus_type < 0 || bus_type > APIC_BUS_MAX) 647 return (EINVAL); 648 io = (struct ioapic *)cookie; 649 if (pin >= io->io_numintr) 650 return (EINVAL); 651 if (io->io_pins[pin].io_irq >= NUM_IO_INTS) 652 return (EINVAL); 653 if (io->io_pins[pin].io_bus == bus_type) 654 return (0); 655 io->io_pins[pin].io_bus = bus_type; 656 if (bootverbose) 657 printf("ioapic%u: intpin %d bus %s\n", io->io_id, pin, 658 ioapic_bus_string(bus_type)); 659 return (0); 660 } 661 662 int 663 ioapic_set_nmi(void *cookie, u_int pin) 664 { 665 struct ioapic *io; 666 667 io = (struct ioapic *)cookie; 668 if (pin >= io->io_numintr) 669 return (EINVAL); 670 if (io->io_pins[pin].io_irq == IRQ_NMI) 671 return (0); 672 if (io->io_pins[pin].io_irq >= NUM_IO_INTS) 673 return (EINVAL); 674 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN; 675 io->io_pins[pin].io_irq = IRQ_NMI; 676 io->io_pins[pin].io_masked = 0; 677 io->io_pins[pin].io_edgetrigger = 1; 678 io->io_pins[pin].io_activehi = 1; 679 if (bootverbose) 680 printf("ioapic%u: Routing NMI -> intpin %d\n", 681 io->io_id, pin); 682 return (0); 683 } 684 685 int 686 ioapic_set_smi(void *cookie, u_int pin) 687 { 688 struct ioapic *io; 689 690 io = (struct ioapic *)cookie; 691 if (pin >= io->io_numintr) 692 return (EINVAL); 693 if (io->io_pins[pin].io_irq == IRQ_SMI) 694 return (0); 695 if (io->io_pins[pin].io_irq >= NUM_IO_INTS) 696 return (EINVAL); 697 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN; 698 io->io_pins[pin].io_irq = IRQ_SMI; 699 io->io_pins[pin].io_masked = 0; 700 io->io_pins[pin].io_edgetrigger = 1; 701 io->io_pins[pin].io_activehi = 1; 702 if (bootverbose) 703 printf("ioapic%u: Routing SMI -> intpin %d\n", 704 io->io_id, pin); 705 return (0); 706 } 707 708 int 709 ioapic_set_extint(void *cookie, u_int pin) 710 { 711 struct ioapic *io; 712 713 io = (struct ioapic *)cookie; 714 if (pin >= io->io_numintr) 715 return (EINVAL); 716 if (io->io_pins[pin].io_irq == IRQ_EXTINT) 717 return (0); 718 if (io->io_pins[pin].io_irq >= NUM_IO_INTS) 719 return (EINVAL); 720 io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN; 721 io->io_pins[pin].io_irq = IRQ_EXTINT; 722 if (enable_extint) 723 io->io_pins[pin].io_masked = 0; 724 else 725 io->io_pins[pin].io_masked = 1; 726 io->io_pins[pin].io_edgetrigger = 1; 727 io->io_pins[pin].io_activehi = 1; 728 if (bootverbose) 729 printf("ioapic%u: Routing external 8259A's -> intpin %d\n", 730 io->io_id, pin); 731 return (0); 732 } 733 734 int 735 ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol) 736 { 737 struct ioapic *io; 738 int activehi; 739 740 io = (struct ioapic *)cookie; 741 if (pin >= io->io_numintr || pol == INTR_POLARITY_CONFORM) 742 return (EINVAL); 743 if (io->io_pins[pin].io_irq >= NUM_IO_INTS) 744 return (EINVAL); 745 activehi = (pol == INTR_POLARITY_HIGH); 746 if (io->io_pins[pin].io_activehi == activehi) 747 return (0); 748 io->io_pins[pin].io_activehi = activehi; 749 if (bootverbose) 750 printf("ioapic%u: intpin %d polarity: %s\n", io->io_id, pin, 751 pol == INTR_POLARITY_HIGH ? "high" : "low"); 752 return (0); 753 } 754 755 int 756 ioapic_set_triggermode(void *cookie, u_int pin, enum intr_trigger trigger) 757 { 758 struct ioapic *io; 759 int edgetrigger; 760 761 io = (struct ioapic *)cookie; 762 if (pin >= io->io_numintr || trigger == INTR_TRIGGER_CONFORM) 763 return (EINVAL); 764 if (io->io_pins[pin].io_irq >= NUM_IO_INTS) 765 return (EINVAL); 766 edgetrigger = (trigger == INTR_TRIGGER_EDGE); 767 if (io->io_pins[pin].io_edgetrigger == edgetrigger) 768 return (0); 769 io->io_pins[pin].io_edgetrigger = edgetrigger; 770 if (bootverbose) 771 printf("ioapic%u: intpin %d trigger: %s\n", io->io_id, pin, 772 trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 773 return (0); 774 } 775 776 /* 777 * Register a complete I/O APIC object with the interrupt subsystem. 778 */ 779 void 780 ioapic_register(void *cookie) 781 { 782 struct ioapic_intsrc *pin; 783 struct ioapic *io; 784 volatile ioapic_t *apic; 785 uint32_t flags; 786 int i; 787 788 io = (struct ioapic *)cookie; 789 apic = io->io_addr; 790 mtx_lock_spin(&icu_lock); 791 flags = ioapic_read(apic, IOAPIC_VER) & IOART_VER_VERSION; 792 STAILQ_INSERT_TAIL(&ioapic_list, io, io_next); 793 mtx_unlock_spin(&icu_lock); 794 printf("ioapic%u <Version %u.%u> irqs %u-%u on motherboard\n", 795 io->io_id, flags >> 4, flags & 0xf, io->io_intbase, 796 io->io_intbase + io->io_numintr - 1); 797 798 /* Register valid pins as interrupt sources. */ 799 intr_register_pic(&io->io_pic); 800 for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) 801 if (pin->io_irq < NUM_IO_INTS) 802 intr_register_source(&pin->io_intsrc); 803 } 804 805 /* A simple new-bus driver to consume PCI I/O APIC devices. */ 806 static int 807 ioapic_pci_probe(device_t dev) 808 { 809 810 if (pci_get_class(dev) == PCIC_BASEPERIPH && 811 pci_get_subclass(dev) == PCIS_BASEPERIPH_PIC) { 812 switch (pci_get_progif(dev)) { 813 case PCIP_BASEPERIPH_PIC_IO_APIC: 814 device_set_desc(dev, "IO APIC"); 815 break; 816 case PCIP_BASEPERIPH_PIC_IOX_APIC: 817 device_set_desc(dev, "IO(x) APIC"); 818 break; 819 default: 820 return (ENXIO); 821 } 822 device_quiet(dev); 823 return (-10000); 824 } 825 return (ENXIO); 826 } 827 828 static int 829 ioapic_pci_attach(device_t dev) 830 { 831 832 return (0); 833 } 834 835 static device_method_t ioapic_pci_methods[] = { 836 /* Device interface */ 837 DEVMETHOD(device_probe, ioapic_pci_probe), 838 DEVMETHOD(device_attach, ioapic_pci_attach), 839 840 { 0, 0 } 841 }; 842 843 DEFINE_CLASS_0(ioapic, ioapic_pci_driver, ioapic_pci_methods, 0); 844 845 static devclass_t ioapic_devclass; 846 DRIVER_MODULE(ioapic, pci, ioapic_pci_driver, ioapic_devclass, 0, 0); 847 848 /* 849 * A new-bus driver to consume the memory resources associated with 850 * the APICs in the system. On some systems ACPI or PnPBIOS system 851 * resource devices may already claim these resources. To keep from 852 * breaking those devices, we attach ourself to the nexus device after 853 * legacy0 and acpi0 and ignore any allocation failures. 854 */ 855 static void 856 apic_identify(driver_t *driver, device_t parent) 857 { 858 859 /* 860 * Add at order 12. acpi0 is probed at order 10 and legacy0 861 * is probed at order 11. 862 */ 863 if (lapic_paddr != 0) 864 BUS_ADD_CHILD(parent, 12, "apic", 0); 865 } 866 867 static int 868 apic_probe(device_t dev) 869 { 870 871 device_set_desc(dev, "APIC resources"); 872 device_quiet(dev); 873 return (0); 874 } 875 876 static void 877 apic_add_resource(device_t dev, int rid, vm_paddr_t base, size_t length) 878 { 879 int error; 880 881 error = bus_set_resource(dev, SYS_RES_MEMORY, rid, base, length); 882 if (error) 883 panic("apic_add_resource: resource %d failed set with %d", rid, 884 error); 885 bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 0); 886 } 887 888 static int 889 apic_attach(device_t dev) 890 { 891 struct ioapic *io; 892 int i; 893 894 /* Reserve the local APIC. */ 895 apic_add_resource(dev, 0, lapic_paddr, sizeof(lapic_t)); 896 i = 1; 897 STAILQ_FOREACH(io, &ioapic_list, io_next) { 898 apic_add_resource(dev, i, io->io_paddr, IOAPIC_MEM_REGION); 899 i++; 900 } 901 return (0); 902 } 903 904 static device_method_t apic_methods[] = { 905 /* Device interface */ 906 DEVMETHOD(device_identify, apic_identify), 907 DEVMETHOD(device_probe, apic_probe), 908 DEVMETHOD(device_attach, apic_attach), 909 910 { 0, 0 } 911 }; 912 913 DEFINE_CLASS_0(apic, apic_driver, apic_methods, 0); 914 915 static devclass_t apic_devclass; 916 DRIVER_MODULE(apic, nexus, apic_driver, apic_devclass, 0, 0);
Cache object: cc04d8b9e37abf4911e00773cd0b9e09
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