1 /*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /*
31 * Local APIC support on Pentium and later processors.
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD: src/sys/amd64/amd64/local_apic.c,v 1.50 2008/12/11 15:56:30 jhb Exp $");
36
37 #include "opt_hwpmc_hooks.h"
38 #include "opt_kdtrace.h"
39
40 #include "opt_ddb.h"
41
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/bus.h>
45 #include <sys/kernel.h>
46 #include <sys/lock.h>
47 #include <sys/mutex.h>
48 #include <sys/pcpu.h>
49 #include <sys/smp.h>
50
51 #include <vm/vm.h>
52 #include <vm/pmap.h>
53
54 #include <machine/apicreg.h>
55 #include <machine/cpu.h>
56 #include <machine/cputypes.h>
57 #include <machine/frame.h>
58 #include <machine/intr_machdep.h>
59 #include <machine/apicvar.h>
60 #include <machine/md_var.h>
61 #include <machine/smp.h>
62 #include <machine/specialreg.h>
63
64 #ifdef DDB
65 #include <sys/interrupt.h>
66 #include <ddb/ddb.h>
67 #endif
68
69 #ifdef KDTRACE_HOOKS
70 #include <sys/dtrace_bsd.h>
71 cyclic_clock_func_t lapic_cyclic_clock_func[MAXCPU];
72 #endif
73
74 /* Sanity checks on IDT vectors. */
75 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
76 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
77 CTASSERT(APIC_LOCAL_INTS == 240);
78 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
79
80 /* Magic IRQ values for the timer and syscalls. */
81 #define IRQ_TIMER (NUM_IO_INTS + 1)
82 #define IRQ_SYSCALL (NUM_IO_INTS + 2)
83
84 /*
85 * Support for local APICs. Local APICs manage interrupts on each
86 * individual processor as opposed to I/O APICs which receive interrupts
87 * from I/O devices and then forward them on to the local APICs.
88 *
89 * Local APICs can also send interrupts to each other thus providing the
90 * mechanism for IPIs.
91 */
92
93 struct lvt {
94 u_int lvt_edgetrigger:1;
95 u_int lvt_activehi:1;
96 u_int lvt_masked:1;
97 u_int lvt_active:1;
98 u_int lvt_mode:16;
99 u_int lvt_vector:8;
100 };
101
102 struct lapic {
103 struct lvt la_lvts[LVT_MAX + 1];
104 u_int la_id:8;
105 u_int la_cluster:4;
106 u_int la_cluster_id:2;
107 u_int la_present:1;
108 u_long *la_timer_count;
109 u_long la_hard_ticks;
110 u_long la_stat_ticks;
111 u_long la_prof_ticks;
112 } static lapics[MAX_APIC_ID + 1];
113
114 /* XXX: should thermal be an NMI? */
115
116 /* Global defaults for local APIC LVT entries. */
117 static struct lvt lvts[LVT_MAX + 1] = {
118 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */
119 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */
120 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */
121 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */
122 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */
123 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */
124 };
125
126 static inthand_t *ioint_handlers[] = {
127 NULL, /* 0 - 31 */
128 IDTVEC(apic_isr1), /* 32 - 63 */
129 IDTVEC(apic_isr2), /* 64 - 95 */
130 IDTVEC(apic_isr3), /* 96 - 127 */
131 IDTVEC(apic_isr4), /* 128 - 159 */
132 IDTVEC(apic_isr5), /* 160 - 191 */
133 IDTVEC(apic_isr6), /* 192 - 223 */
134 IDTVEC(apic_isr7), /* 224 - 255 */
135 };
136
137 /* Include IDT_SYSCALL to make indexing easier. */
138 static u_int ioint_irqs[APIC_NUM_IOINTS + 1];
139
140 static u_int32_t lapic_timer_divisors[] = {
141 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
142 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
143 };
144
145 extern inthand_t IDTVEC(rsvd);
146
147 volatile lapic_t *lapic;
148 vm_paddr_t lapic_paddr;
149 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz;
150
151 static void lapic_enable(void);
152 static void lapic_resume(struct pic *pic);
153 static void lapic_timer_enable_intr(void);
154 static void lapic_timer_oneshot(u_int count);
155 static void lapic_timer_periodic(u_int count);
156 static void lapic_timer_set_divisor(u_int divisor);
157 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
158
159 struct pic lapic_pic = { .pic_resume = lapic_resume };
160
161 static uint32_t
162 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
163 {
164 struct lvt *lvt;
165
166 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin));
167 if (la->la_lvts[pin].lvt_active)
168 lvt = &la->la_lvts[pin];
169 else
170 lvt = &lvts[pin];
171
172 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
173 APIC_LVT_VECTOR);
174 if (lvt->lvt_edgetrigger == 0)
175 value |= APIC_LVT_TM;
176 if (lvt->lvt_activehi == 0)
177 value |= APIC_LVT_IIPP_INTALO;
178 if (lvt->lvt_masked)
179 value |= APIC_LVT_M;
180 value |= lvt->lvt_mode;
181 switch (lvt->lvt_mode) {
182 case APIC_LVT_DM_NMI:
183 case APIC_LVT_DM_SMI:
184 case APIC_LVT_DM_INIT:
185 case APIC_LVT_DM_EXTINT:
186 if (!lvt->lvt_edgetrigger) {
187 printf("lapic%u: Forcing LINT%u to edge trigger\n",
188 la->la_id, pin);
189 value |= APIC_LVT_TM;
190 }
191 /* Use a vector of 0. */
192 break;
193 case APIC_LVT_DM_FIXED:
194 value |= lvt->lvt_vector;
195 break;
196 default:
197 panic("bad APIC LVT delivery mode: %#x\n", value);
198 }
199 return (value);
200 }
201
202 /*
203 * Map the local APIC and setup necessary interrupt vectors.
204 */
205 void
206 lapic_init(vm_paddr_t addr)
207 {
208
209 /* Map the local APIC and setup the spurious interrupt handler. */
210 KASSERT(trunc_page(addr) == addr,
211 ("local APIC not aligned on a page boundary"));
212 lapic = pmap_mapdev(addr, sizeof(lapic_t));
213 lapic_paddr = addr;
214 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0);
215
216 /* Perform basic initialization of the BSP's local APIC. */
217 lapic_enable();
218 ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
219
220 /* Set BSP's per-CPU local APIC ID. */
221 PCPU_SET(apic_id, lapic_id());
222
223 /* Local APIC timer interrupt. */
224 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYSIGT, SEL_KPL, 0);
225 ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER;
226
227 /* XXX: error/thermal interrupts */
228 }
229
230 /*
231 * Create a local APIC instance.
232 */
233 void
234 lapic_create(u_int apic_id, int boot_cpu)
235 {
236 int i;
237
238 if (apic_id > MAX_APIC_ID) {
239 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
240 if (boot_cpu)
241 panic("Can't ignore BSP");
242 return;
243 }
244 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
245 apic_id));
246
247 /*
248 * Assume no local LVT overrides and a cluster of 0 and
249 * intra-cluster ID of 0.
250 */
251 lapics[apic_id].la_present = 1;
252 lapics[apic_id].la_id = apic_id;
253 for (i = 0; i < LVT_MAX; i++) {
254 lapics[apic_id].la_lvts[i] = lvts[i];
255 lapics[apic_id].la_lvts[i].lvt_active = 0;
256 }
257
258 #ifdef SMP
259 cpu_add(apic_id, boot_cpu);
260 #endif
261 }
262
263 /*
264 * Dump contents of local APIC registers
265 */
266 void
267 lapic_dump(const char* str)
268 {
269
270 printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
271 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n",
272 lapic->id, lapic->version, lapic->ldr, lapic->dfr);
273 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
274 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
275 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n",
276 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error,
277 lapic->lvt_pcint);
278 }
279
280 void
281 lapic_setup(int boot)
282 {
283 struct lapic *la;
284 u_int32_t maxlvt;
285 register_t eflags;
286 char buf[MAXCOMLEN + 1];
287
288 la = &lapics[lapic_id()];
289 KASSERT(la->la_present, ("missing APIC structure"));
290 eflags = intr_disable();
291 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
292
293 /* Initialize the TPR to allow all interrupts. */
294 lapic_set_tpr(0);
295
296 /* Setup spurious vector and enable the local APIC. */
297 lapic_enable();
298
299 /* Program LINT[01] LVT entries. */
300 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
301 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
302
303 #ifdef HWPMC_HOOKS
304 /* Program the PMC LVT entry if present. */
305 if (maxlvt >= LVT_PMC)
306 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
307 #endif
308
309 /* Program timer LVT and setup handler. */
310 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer);
311 if (boot) {
312 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid));
313 intrcnt_add(buf, &la->la_timer_count);
314 }
315
316 /* We don't setup the timer during boot on the BSP until later. */
317 if (!(boot && PCPU_GET(cpuid) == 0)) {
318 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor",
319 lapic_id()));
320 lapic_timer_set_divisor(lapic_timer_divisor);
321 lapic_timer_periodic(lapic_timer_period);
322 lapic_timer_enable_intr();
323 }
324
325 /* XXX: Error and thermal LVTs */
326
327 if (cpu_vendor_id == CPU_VENDOR_AMD) {
328 /*
329 * Detect the presence of C1E capability mostly on latest
330 * dual-cores (or future) k8 family. This feature renders
331 * the local APIC timer dead, so we disable it by reading
332 * the Interrupt Pending Message register and clearing both
333 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
334 *
335 * Reference:
336 * "BIOS and Kernel Developer's Guide for AMD NPT
337 * Family 0Fh Processors"
338 * #32559 revision 3.00
339 */
340 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
341 (cpu_id & 0x0fff0000) >= 0x00040000) {
342 uint64_t msr;
343
344 msr = rdmsr(0xc0010055);
345 if (msr & 0x18000000)
346 wrmsr(0xc0010055, msr & ~0x18000000ULL);
347 }
348 }
349
350 intr_restore(eflags);
351 }
352
353 /*
354 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so
355 * that it can drive hardclock, statclock, and profclock. This function
356 * returns true if it is able to use the local APIC timer to drive the
357 * clocks and false if it is not able.
358 */
359 int
360 lapic_setup_clock(void)
361 {
362 u_long value;
363
364 /* Can't drive the timer without a local APIC. */
365 if (lapic == NULL)
366 return (0);
367
368 /* Start off with a divisor of 2 (power on reset default). */
369 lapic_timer_divisor = 2;
370
371 /* Try to calibrate the local APIC timer. */
372 do {
373 lapic_timer_set_divisor(lapic_timer_divisor);
374 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
375 DELAY(2000000);
376 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
377 if (value != APIC_TIMER_MAX_COUNT)
378 break;
379 lapic_timer_divisor <<= 1;
380 } while (lapic_timer_divisor <= 128);
381 if (lapic_timer_divisor > 128)
382 panic("lapic: Divisor too big");
383 value /= 2;
384 if (bootverbose)
385 printf("lapic: Divisor %lu, Frequency %lu hz\n",
386 lapic_timer_divisor, value);
387
388 /*
389 * We want to run stathz in the neighborhood of 128hz. We would
390 * like profhz to run as often as possible, so we let it run on
391 * each clock tick. We try to honor the requested 'hz' value as
392 * much as possible.
393 *
394 * If 'hz' is above 1500, then we just let the lapic timer
395 * (and profhz) run at hz. If 'hz' is below 1500 but above
396 * 750, then we let the lapic timer run at 2 * 'hz'. If 'hz'
397 * is below 750 then we let the lapic timer run at 4 * 'hz'.
398 */
399 if (hz >= 1500)
400 lapic_timer_hz = hz;
401 else if (hz >= 750)
402 lapic_timer_hz = hz * 2;
403 else
404 lapic_timer_hz = hz * 4;
405 if (lapic_timer_hz < 128)
406 stathz = lapic_timer_hz;
407 else
408 stathz = lapic_timer_hz / (lapic_timer_hz / 128);
409 profhz = lapic_timer_hz;
410 lapic_timer_period = value / lapic_timer_hz;
411
412 /*
413 * Start up the timer on the BSP. The APs will kick off their
414 * timer during lapic_setup().
415 */
416 lapic_timer_periodic(lapic_timer_period);
417 lapic_timer_enable_intr();
418 return (1);
419 }
420
421 void
422 lapic_disable(void)
423 {
424 uint32_t value;
425
426 /* Software disable the local APIC. */
427 value = lapic->svr;
428 value &= ~APIC_SVR_SWEN;
429 lapic->svr = value;
430 }
431
432 static void
433 lapic_enable(void)
434 {
435 u_int32_t value;
436
437 /* Program the spurious vector to enable the local APIC. */
438 value = lapic->svr;
439 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
440 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
441 lapic->svr = value;
442 }
443
444 /* Reset the local APIC on the BSP during resume. */
445 static void
446 lapic_resume(struct pic *pic)
447 {
448
449 lapic_setup(0);
450 }
451
452 int
453 lapic_id(void)
454 {
455
456 KASSERT(lapic != NULL, ("local APIC is not mapped"));
457 return (lapic->id >> APIC_ID_SHIFT);
458 }
459
460 int
461 lapic_intr_pending(u_int vector)
462 {
463 volatile u_int32_t *irr;
464
465 /*
466 * The IRR registers are an array of 128-bit registers each of
467 * which only describes 32 interrupts in the low 32 bits.. Thus,
468 * we divide the vector by 32 to get the 128-bit index. We then
469 * multiply that index by 4 to get the equivalent index from
470 * treating the IRR as an array of 32-bit registers. Finally, we
471 * modulus the vector by 32 to determine the individual bit to
472 * test.
473 */
474 irr = &lapic->irr0;
475 return (irr[(vector / 32) * 4] & 1 << (vector % 32));
476 }
477
478 void
479 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
480 {
481 struct lapic *la;
482
483 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
484 __func__, apic_id));
485 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
486 __func__, cluster));
487 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
488 ("%s: intra cluster id %u too big", __func__, cluster_id));
489 la = &lapics[apic_id];
490 la->la_cluster = cluster;
491 la->la_cluster_id = cluster_id;
492 }
493
494 int
495 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
496 {
497
498 if (pin > LVT_MAX)
499 return (EINVAL);
500 if (apic_id == APIC_ID_ALL) {
501 lvts[pin].lvt_masked = masked;
502 if (bootverbose)
503 printf("lapic:");
504 } else {
505 KASSERT(lapics[apic_id].la_present,
506 ("%s: missing APIC %u", __func__, apic_id));
507 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
508 lapics[apic_id].la_lvts[pin].lvt_active = 1;
509 if (bootverbose)
510 printf("lapic%u:", apic_id);
511 }
512 if (bootverbose)
513 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
514 return (0);
515 }
516
517 int
518 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
519 {
520 struct lvt *lvt;
521
522 if (pin > LVT_MAX)
523 return (EINVAL);
524 if (apic_id == APIC_ID_ALL) {
525 lvt = &lvts[pin];
526 if (bootverbose)
527 printf("lapic:");
528 } else {
529 KASSERT(lapics[apic_id].la_present,
530 ("%s: missing APIC %u", __func__, apic_id));
531 lvt = &lapics[apic_id].la_lvts[pin];
532 lvt->lvt_active = 1;
533 if (bootverbose)
534 printf("lapic%u:", apic_id);
535 }
536 lvt->lvt_mode = mode;
537 switch (mode) {
538 case APIC_LVT_DM_NMI:
539 case APIC_LVT_DM_SMI:
540 case APIC_LVT_DM_INIT:
541 case APIC_LVT_DM_EXTINT:
542 lvt->lvt_edgetrigger = 1;
543 lvt->lvt_activehi = 1;
544 if (mode == APIC_LVT_DM_EXTINT)
545 lvt->lvt_masked = 1;
546 else
547 lvt->lvt_masked = 0;
548 break;
549 default:
550 panic("Unsupported delivery mode: 0x%x\n", mode);
551 }
552 if (bootverbose) {
553 printf(" Routing ");
554 switch (mode) {
555 case APIC_LVT_DM_NMI:
556 printf("NMI");
557 break;
558 case APIC_LVT_DM_SMI:
559 printf("SMI");
560 break;
561 case APIC_LVT_DM_INIT:
562 printf("INIT");
563 break;
564 case APIC_LVT_DM_EXTINT:
565 printf("ExtINT");
566 break;
567 }
568 printf(" -> LINT%u\n", pin);
569 }
570 return (0);
571 }
572
573 int
574 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
575 {
576
577 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM)
578 return (EINVAL);
579 if (apic_id == APIC_ID_ALL) {
580 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
581 if (bootverbose)
582 printf("lapic:");
583 } else {
584 KASSERT(lapics[apic_id].la_present,
585 ("%s: missing APIC %u", __func__, apic_id));
586 lapics[apic_id].la_lvts[pin].lvt_active = 1;
587 lapics[apic_id].la_lvts[pin].lvt_activehi =
588 (pol == INTR_POLARITY_HIGH);
589 if (bootverbose)
590 printf("lapic%u:", apic_id);
591 }
592 if (bootverbose)
593 printf(" LINT%u polarity: %s\n", pin,
594 pol == INTR_POLARITY_HIGH ? "high" : "low");
595 return (0);
596 }
597
598 int
599 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger)
600 {
601
602 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
603 return (EINVAL);
604 if (apic_id == APIC_ID_ALL) {
605 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
606 if (bootverbose)
607 printf("lapic:");
608 } else {
609 KASSERT(lapics[apic_id].la_present,
610 ("%s: missing APIC %u", __func__, apic_id));
611 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
612 (trigger == INTR_TRIGGER_EDGE);
613 lapics[apic_id].la_lvts[pin].lvt_active = 1;
614 if (bootverbose)
615 printf("lapic%u:", apic_id);
616 }
617 if (bootverbose)
618 printf(" LINT%u trigger: %s\n", pin,
619 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
620 return (0);
621 }
622
623 /*
624 * Adjust the TPR of the current CPU so that it blocks all interrupts below
625 * the passed in vector.
626 */
627 void
628 lapic_set_tpr(u_int vector)
629 {
630 #ifdef CHEAP_TPR
631 lapic->tpr = vector;
632 #else
633 u_int32_t tpr;
634
635 tpr = lapic->tpr & ~APIC_TPR_PRIO;
636 tpr |= vector;
637 lapic->tpr = tpr;
638 #endif
639 }
640
641 void
642 lapic_eoi(void)
643 {
644
645 lapic->eoi = 0;
646 }
647
648 /*
649 * Read the contents of the error status register. We have to write
650 * to the register first before reading from it.
651 */
652 u_int
653 lapic_error(void)
654 {
655
656 lapic->esr = 0;
657 return (lapic->esr);
658 }
659
660 void
661 lapic_handle_intr(int vector, struct trapframe *frame)
662 {
663 struct intsrc *isrc;
664
665 if (vector == -1)
666 panic("Couldn't get vector from ISR!");
667 isrc = intr_lookup_source(apic_idt_to_irq(vector));
668 intr_execute_handlers(isrc, frame);
669 }
670
671 void
672 lapic_handle_timer(struct trapframe *frame)
673 {
674 struct lapic *la;
675
676 /* Send EOI first thing. */
677 lapic_eoi();
678
679 #if defined(SMP) && !defined(SCHED_ULE)
680 /*
681 * Don't do any accounting for the disabled HTT cores, since it
682 * will provide misleading numbers for the userland.
683 *
684 * No locking is necessary here, since even if we loose the race
685 * when hlt_cpus_mask changes it is not a big deal, really.
686 *
687 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask
688 * and unlike other schedulers it actually schedules threads to
689 * those CPUs.
690 */
691 if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0)
692 return;
693 #endif
694
695 /* Look up our local APIC structure for the tick counters. */
696 la = &lapics[PCPU_GET(apic_id)];
697 (*la->la_timer_count)++;
698 critical_enter();
699
700 #ifdef KDTRACE_HOOKS
701 /*
702 * If the DTrace hooks are configured and a callback function
703 * has been registered, then call it to process the high speed
704 * timers.
705 */
706 int cpu = PCPU_GET(cpuid);
707 if (lapic_cyclic_clock_func[cpu] != NULL)
708 (*lapic_cyclic_clock_func[cpu])(frame);
709 #endif
710
711 /* Fire hardclock at hz. */
712 la->la_hard_ticks += hz;
713 if (la->la_hard_ticks >= lapic_timer_hz) {
714 la->la_hard_ticks -= lapic_timer_hz;
715 if (PCPU_GET(cpuid) == 0)
716 hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
717 else
718 hardclock_cpu(TRAPF_USERMODE(frame));
719 }
720
721 /* Fire statclock at stathz. */
722 la->la_stat_ticks += stathz;
723 if (la->la_stat_ticks >= lapic_timer_hz) {
724 la->la_stat_ticks -= lapic_timer_hz;
725 statclock(TRAPF_USERMODE(frame));
726 }
727
728 /* Fire profclock at profhz, but only when needed. */
729 la->la_prof_ticks += profhz;
730 if (la->la_prof_ticks >= lapic_timer_hz) {
731 la->la_prof_ticks -= lapic_timer_hz;
732 if (profprocs != 0)
733 profclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
734 }
735 critical_exit();
736 }
737
738 static void
739 lapic_timer_set_divisor(u_int divisor)
740 {
741
742 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor));
743 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) /
744 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor));
745 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1];
746 }
747
748 static void
749 lapic_timer_oneshot(u_int count)
750 {
751 u_int32_t value;
752
753 value = lapic->lvt_timer;
754 value &= ~APIC_LVTT_TM;
755 value |= APIC_LVTT_TM_ONE_SHOT;
756 lapic->lvt_timer = value;
757 lapic->icr_timer = count;
758 }
759
760 static void
761 lapic_timer_periodic(u_int count)
762 {
763 u_int32_t value;
764
765 value = lapic->lvt_timer;
766 value &= ~APIC_LVTT_TM;
767 value |= APIC_LVTT_TM_PERIODIC;
768 lapic->lvt_timer = value;
769 lapic->icr_timer = count;
770 }
771
772 static void
773 lapic_timer_enable_intr(void)
774 {
775 u_int32_t value;
776
777 value = lapic->lvt_timer;
778 value &= ~APIC_LVT_M;
779 lapic->lvt_timer = value;
780 }
781
782 /* Request a free IDT vector to be used by the specified IRQ. */
783 u_int
784 apic_alloc_vector(u_int irq)
785 {
786 u_int vector;
787
788 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
789
790 /*
791 * Search for a free vector. Currently we just use a very simple
792 * algorithm to find the first free vector.
793 */
794 mtx_lock_spin(&icu_lock);
795 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
796 if (ioint_irqs[vector] != 0)
797 continue;
798 ioint_irqs[vector] = irq;
799 mtx_unlock_spin(&icu_lock);
800 return (vector + APIC_IO_INTS);
801 }
802 mtx_unlock_spin(&icu_lock);
803 panic("Couldn't find an APIC vector for IRQ %u", irq);
804 }
805
806 /*
807 * Request 'count' free contiguous IDT vectors to be used by 'count'
808 * IRQs. 'count' must be a power of two and the vectors will be
809 * aligned on a boundary of 'align'. If the request cannot be
810 * satisfied, 0 is returned.
811 */
812 u_int
813 apic_alloc_vectors(u_int *irqs, u_int count, u_int align)
814 {
815 u_int first, run, vector;
816
817 KASSERT(powerof2(count), ("bad count"));
818 KASSERT(powerof2(align), ("bad align"));
819 KASSERT(align >= count, ("align < count"));
820 #ifdef INVARIANTS
821 for (run = 0; run < count; run++)
822 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u",
823 irqs[run], run));
824 #endif
825
826 /*
827 * Search for 'count' free vectors. As with apic_alloc_vector(),
828 * this just uses a simple first fit algorithm.
829 */
830 run = 0;
831 first = 0;
832 mtx_lock_spin(&icu_lock);
833 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
834
835 /* Vector is in use, end run. */
836 if (ioint_irqs[vector] != 0) {
837 run = 0;
838 first = 0;
839 continue;
840 }
841
842 /* Start a new run if run == 0 and vector is aligned. */
843 if (run == 0) {
844 if ((vector & (align - 1)) != 0)
845 continue;
846 first = vector;
847 }
848 run++;
849
850 /* Keep looping if the run isn't long enough yet. */
851 if (run < count)
852 continue;
853
854 /* Found a run, assign IRQs and return the first vector. */
855 for (vector = 0; vector < count; vector++)
856 ioint_irqs[first + vector] = irqs[vector];
857 mtx_unlock_spin(&icu_lock);
858 return (first + APIC_IO_INTS);
859 }
860 mtx_unlock_spin(&icu_lock);
861 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count);
862 return (0);
863 }
864
865 void
866 apic_enable_vector(u_int vector)
867 {
868
869 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
870 KASSERT(ioint_handlers[vector / 32] != NULL,
871 ("No ISR handler for vector %u", vector));
872 setidt(vector, ioint_handlers[vector / 32], SDT_SYSIGT, SEL_KPL, 0);
873 }
874
875 void
876 apic_disable_vector(u_int vector)
877 {
878
879 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
880 KASSERT(ioint_handlers[vector / 32] != NULL,
881 ("No ISR handler for vector %u", vector));
882 setidt(vector, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
883 }
884
885 /* Release an APIC vector when it's no longer in use. */
886 void
887 apic_free_vector(u_int vector, u_int irq)
888 {
889 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
890 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
891 ("Vector %u does not map to an IRQ line", vector));
892 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
893 KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch"));
894 mtx_lock_spin(&icu_lock);
895 ioint_irqs[vector - APIC_IO_INTS] = 0;
896 mtx_unlock_spin(&icu_lock);
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