1 /*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /*
31 * Local APIC support on Pentium and later processors.
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD: releng/5.2/sys/amd64/amd64/local_apic.c 123177 2003-12-06 23:14:44Z peter $");
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/bus.h>
40 #include <sys/kernel.h>
41 #include <sys/pcpu.h>
42 #include <sys/proc.h>
43
44 #include <vm/vm.h>
45 #include <vm/pmap.h>
46
47 #include <machine/apicreg.h>
48 #include <machine/cputypes.h>
49 #include <machine/frame.h>
50 #include <machine/intr_machdep.h>
51 #include <machine/apicvar.h>
52 #include <machine/md_var.h>
53 #include <machine/smp.h>
54 #include <machine/specialreg.h>
55
56 /*
57 * We can handle up to 60 APICs via our logical cluster IDs, but currently
58 * the physical IDs on Intel processors up to the Pentium 4 are limited to
59 * 16.
60 */
61 #define MAX_APICID 16
62
63 /* Sanity checks on IDT vectors. */
64 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS <= APIC_LOCAL_INTS);
65 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
66
67 /*
68 * Support for local APICs. Local APICs manage interrupts on each
69 * individual processor as opposed to I/O APICs which receive interrupts
70 * from I/O devices and then forward them on to the local APICs.
71 *
72 * Local APICs can also send interrupts to each other thus providing the
73 * mechanism for IPIs.
74 */
75
76 struct lvt {
77 u_int lvt_edgetrigger:1;
78 u_int lvt_activehi:1;
79 u_int lvt_masked:1;
80 u_int lvt_active:1;
81 u_int lvt_mode:16;
82 u_int lvt_vector:8;
83 };
84
85 struct lapic {
86 struct lvt la_lvts[LVT_MAX + 1];
87 u_int la_id:8;
88 u_int la_cluster:4;
89 u_int la_cluster_id:2;
90 u_int la_present:1;
91 } static lapics[MAX_APICID];
92
93 /* XXX: should thermal be an NMI? */
94
95 /* Global defaults for local APIC LVT entries. */
96 static struct lvt lvts[LVT_MAX + 1] = {
97 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */
98 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */
99 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, 0 }, /* Timer: needs a vector */
100 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, 0 }, /* Error: needs a vector */
101 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, 0 }, /* PMC */
102 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, 0 }, /* Thermal: needs a vector */
103 };
104
105 static inthand_t *ioint_handlers[] = {
106 NULL, /* 0 - 31 */
107 IDTVEC(apic_isr1), /* 32 - 63 */
108 IDTVEC(apic_isr2), /* 64 - 95 */
109 IDTVEC(apic_isr3), /* 96 - 127 */
110 IDTVEC(apic_isr4), /* 128 - 159 */
111 IDTVEC(apic_isr5), /* 160 - 191 */
112 IDTVEC(apic_isr6), /* 192 - 223 */
113 IDTVEC(apic_isr7), /* 224 - 255 */
114 };
115
116 volatile lapic_t *lapic;
117
118 static uint32_t
119 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
120 {
121 struct lvt *lvt;
122
123 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin));
124 if (la->la_lvts[pin].lvt_active)
125 lvt = &la->la_lvts[pin];
126 else
127 lvt = &lvts[pin];
128
129 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
130 APIC_LVT_VECTOR);
131 if (lvt->lvt_edgetrigger == 0)
132 value |= APIC_LVT_TM;
133 if (lvt->lvt_activehi == 0)
134 value |= APIC_LVT_IIPP_INTALO;
135 if (lvt->lvt_masked)
136 value |= APIC_LVT_M;
137 value |= lvt->lvt_mode;
138 switch (lvt->lvt_mode) {
139 case APIC_LVT_DM_NMI:
140 case APIC_LVT_DM_SMI:
141 case APIC_LVT_DM_INIT:
142 case APIC_LVT_DM_EXTINT:
143 if (!lvt->lvt_edgetrigger) {
144 printf("lapic%u: Forcing LINT%u to edge trigger\n",
145 la->la_id, pin);
146 value |= APIC_LVT_TM;
147 }
148 /* Use a vector of 0. */
149 break;
150 case APIC_LVT_DM_FIXED:
151 #if 0
152 value |= lvt->lvt_vector;
153 #else
154 panic("Fixed LINT pins not supported");
155 #endif
156 break;
157 default:
158 panic("bad APIC LVT delivery mode: %#x\n", value);
159 }
160 return (value);
161 }
162
163 /*
164 * Map the local APIC and setup necessary interrupt vectors.
165 */
166 void
167 lapic_init(uintptr_t addr)
168 {
169 u_int32_t value;
170
171 /* Map the local APIC and setup the spurious interrupt handler. */
172 KASSERT(trunc_page(addr) == addr,
173 ("local APIC not aligned on a page boundary"));
174 lapic = (lapic_t *)pmap_mapdev(addr, sizeof(lapic_t));
175 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0);
176
177 /* Perform basic initialization of the BSP's local APIC. */
178 value = lapic->svr;
179 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
180 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
181 lapic->svr = value;
182
183 /* Set BSP's per-CPU local APIC ID. */
184 PCPU_SET(apic_id, lapic_id());
185
186 /* XXX: timer/error/thermal interrupts */
187 }
188
189 /*
190 * Create a local APIC instance.
191 */
192 void
193 lapic_create(u_int apic_id, int boot_cpu)
194 {
195 int i;
196
197 if (apic_id > MAX_APICID) {
198 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
199 if (boot_cpu)
200 panic("Can't ignore BSP");
201 return;
202 }
203 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
204 apic_id));
205
206 /*
207 * Assume no local LVT overrides and a cluster of 0 and
208 * intra-cluster ID of 0.
209 */
210 lapics[apic_id].la_present = 1;
211 lapics[apic_id].la_id = apic_id;
212 for (i = 0; i < LVT_MAX; i++) {
213 lapics[apic_id].la_lvts[i] = lvts[i];
214 lapics[apic_id].la_lvts[i].lvt_active = 0;
215 }
216
217 #ifdef SMP
218 cpu_add(apic_id, boot_cpu);
219 #endif
220 }
221
222 /*
223 * Dump contents of local APIC registers
224 */
225 void
226 lapic_dump(const char* str)
227 {
228
229 printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
230 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n",
231 lapic->id, lapic->version, lapic->ldr, lapic->dfr);
232 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
233 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
234 }
235
236 void
237 lapic_enable_intr(u_int irq)
238 {
239 u_int vector;
240
241 vector = apic_irq_to_idt(irq);
242 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
243 KASSERT(ioint_handlers[vector / 32] != NULL,
244 ("No ISR handler for IRQ %u", irq));
245 setidt(vector, ioint_handlers[vector / 32], SDT_SYSIGT, SEL_KPL, 0);
246 }
247
248 void
249 lapic_setup(void)
250 {
251 struct lapic *la;
252 u_int32_t value, maxlvt;
253 register_t eflags;
254
255 la = &lapics[lapic_id()];
256 KASSERT(la->la_present, ("missing APIC structure"));
257 eflags = intr_disable();
258 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
259
260 /* Program LINT[01] LVT entries. */
261 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
262 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
263
264 /* XXX: more LVT entries */
265
266 /* Clear the TPR. */
267 value = lapic->tpr;
268 value &= ~APIC_TPR_PRIO;
269 lapic->tpr = value;
270
271 /* Use the cluster model for logical IDs. */
272 value = lapic->dfr;
273 value &= ~APIC_DFR_MODEL_MASK;
274 value |= APIC_DFR_MODEL_CLUSTER;
275 lapic->dfr = value;
276
277 /* Set this APIC's logical ID. */
278 value = lapic->ldr;
279 value &= ~APIC_ID_MASK;
280 value |= (la->la_cluster << APIC_ID_CLUSTER_SHIFT |
281 1 << la->la_cluster_id) << APIC_ID_SHIFT;
282 lapic->ldr = value;
283
284 /* Setup spurious vector and enable the local APIC. */
285 value = lapic->svr;
286 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
287 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
288 lapic->svr = value;
289 intr_restore(eflags);
290 }
291
292 void
293 lapic_disable(void)
294 {
295 uint32_t value;
296
297 /* Software disable the local APIC. */
298 value = lapic->svr;
299 value &= ~APIC_SVR_SWEN;
300 lapic->svr = value;
301 }
302
303 int
304 lapic_id(void)
305 {
306
307 KASSERT(lapic != NULL, ("local APIC is not mapped"));
308 return (lapic->id >> APIC_ID_SHIFT);
309 }
310
311 int
312 lapic_intr_pending(u_int vector)
313 {
314 volatile u_int32_t *irr;
315
316 /*
317 * The IRR registers are an array of 128-bit registers each of
318 * which only describes 32 interrupts in the low 32 bits.. Thus,
319 * we divide the vector by 32 to get the 128-bit index. We then
320 * multiply that index by 4 to get the equivalent index from
321 * treating the IRR as an array of 32-bit registers. Finally, we
322 * modulus the vector by 32 to determine the individual bit to
323 * test.
324 */
325 irr = &lapic->irr0;
326 return (irr[(vector / 32) * 4] & 1 << (vector % 32));
327 }
328
329 void
330 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
331 {
332 struct lapic *la;
333
334 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
335 __func__, apic_id));
336 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
337 __func__, cluster));
338 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
339 ("%s: intra cluster id %u too big", __func__, cluster_id));
340 la = &lapics[apic_id];
341 la->la_cluster = cluster;
342 la->la_cluster_id = cluster_id;
343 }
344
345 int
346 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
347 {
348
349 if (pin > LVT_MAX)
350 return (EINVAL);
351 if (apic_id == APIC_ID_ALL) {
352 lvts[pin].lvt_masked = masked;
353 if (bootverbose)
354 printf("lapic:");
355 } else {
356 KASSERT(lapics[apic_id].la_present,
357 ("%s: missing APIC %u", __func__, apic_id));
358 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
359 lapics[apic_id].la_lvts[pin].lvt_active = 1;
360 if (bootverbose)
361 printf("lapic%u:", apic_id);
362 }
363 if (bootverbose)
364 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
365 return (0);
366 }
367
368 int
369 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
370 {
371 struct lvt *lvt;
372
373 if (pin > LVT_MAX)
374 return (EINVAL);
375 if (apic_id == APIC_ID_ALL) {
376 lvt = &lvts[pin];
377 if (bootverbose)
378 printf("lapic:");
379 } else {
380 KASSERT(lapics[apic_id].la_present,
381 ("%s: missing APIC %u", __func__, apic_id));
382 lvt = &lapics[apic_id].la_lvts[pin];
383 lvt->lvt_active = 1;
384 if (bootverbose)
385 printf("lapic%u:", apic_id);
386 }
387 lvt->lvt_mode = mode;
388 switch (mode) {
389 case APIC_LVT_DM_NMI:
390 case APIC_LVT_DM_SMI:
391 case APIC_LVT_DM_INIT:
392 case APIC_LVT_DM_EXTINT:
393 lvt->lvt_edgetrigger = 1;
394 lvt->lvt_activehi = 1;
395 if (mode == APIC_LVT_DM_EXTINT)
396 lvt->lvt_masked = 1;
397 else
398 lvt->lvt_masked = 0;
399 break;
400 default:
401 panic("Unsupported delivery mode: 0x%x\n", mode);
402 }
403 if (bootverbose) {
404 printf(" Routing ");
405 switch (mode) {
406 case APIC_LVT_DM_NMI:
407 printf("NMI");
408 break;
409 case APIC_LVT_DM_SMI:
410 printf("SMI");
411 break;
412 case APIC_LVT_DM_INIT:
413 printf("INIT");
414 break;
415 case APIC_LVT_DM_EXTINT:
416 printf("ExtINT");
417 break;
418 }
419 printf(" -> LINT%u\n", pin);
420 }
421 return (0);
422 }
423
424 int
425 lapic_set_lvt_polarity(u_int apic_id, u_int pin, u_char activehi)
426 {
427
428 if (pin > LVT_MAX)
429 return (EINVAL);
430 if (apic_id == APIC_ID_ALL) {
431 lvts[pin].lvt_activehi = activehi;
432 if (bootverbose)
433 printf("lapic:");
434 } else {
435 KASSERT(lapics[apic_id].la_present,
436 ("%s: missing APIC %u", __func__, apic_id));
437 lapics[apic_id].la_lvts[pin].lvt_active = 1;
438 lapics[apic_id].la_lvts[pin].lvt_activehi = activehi;
439 if (bootverbose)
440 printf("lapic%u:", apic_id);
441 }
442 if (bootverbose)
443 printf(" LINT%u polarity: active-%s\n", pin,
444 activehi ? "hi" : "lo");
445 return (0);
446 }
447
448 int
449 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, u_char edgetrigger)
450 {
451
452 if (pin > LVT_MAX)
453 return (EINVAL);
454 if (apic_id == APIC_ID_ALL) {
455 lvts[pin].lvt_edgetrigger = edgetrigger;
456 if (bootverbose)
457 printf("lapic:");
458 } else {
459 KASSERT(lapics[apic_id].la_present,
460 ("%s: missing APIC %u", __func__, apic_id));
461 lapics[apic_id].la_lvts[pin].lvt_edgetrigger = edgetrigger;
462 lapics[apic_id].la_lvts[pin].lvt_active = 1;
463 if (bootverbose)
464 printf("lapic%u:", apic_id);
465 }
466 if (bootverbose)
467 printf(" LINT%u trigger: %s\n", pin,
468 edgetrigger ? "edge" : "level");
469 return (0);
470 }
471
472 void
473 lapic_eoi(void)
474 {
475
476 lapic->eoi = 0;
477 }
478
479 void
480 lapic_handle_intr(void *cookie, struct intrframe frame)
481 {
482 struct intsrc *isrc;
483 int vec = (uintptr_t)cookie;
484
485 if (vec == -1)
486 panic("Couldn't get vector from ISR!");
487 isrc = intr_lookup_source(apic_idt_to_irq(vec));
488 intr_execute_handlers(isrc, &frame);
489 }
490
491 /* Translate between IDT vectors and IRQ vectors. */
492 u_int
493 apic_irq_to_idt(u_int irq)
494 {
495 u_int vector;
496
497 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
498 vector = irq + APIC_IO_INTS;
499 if (vector >= IDT_SYSCALL)
500 vector++;
501 return (vector);
502 }
503
504 u_int
505 apic_idt_to_irq(u_int vector)
506 {
507
508 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
509 vector <= APIC_IO_INTS + NUM_IO_INTS,
510 ("Vector %u does not map to an IRQ line", vector));
511 if (vector > IDT_SYSCALL)
512 vector--;
513 return (vector - APIC_IO_INTS);
514 }
515
516 /*
517 * APIC probing support code. This includes code to manage enumerators.
518 */
519
520 static SLIST_HEAD(, apic_enumerator) enumerators =
521 SLIST_HEAD_INITIALIZER(enumerators);
522 static struct apic_enumerator *best_enum;
523
524 void
525 apic_register_enumerator(struct apic_enumerator *enumerator)
526 {
527 #ifdef INVARIANTS
528 struct apic_enumerator *apic_enum;
529
530 SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
531 if (apic_enum == enumerator)
532 panic("%s: Duplicate register of %s", __func__,
533 enumerator->apic_name);
534 }
535 #endif
536 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
537 }
538
539 /*
540 * We have to look for CPU's very, very early because certain subsystems
541 * want to know how many CPU's we have extremely early on in the boot
542 * process.
543 */
544 static void
545 apic_init(void *dummy __unused)
546 {
547 struct apic_enumerator *enumerator;
548 int retval, best;
549
550 /* We only support built in local APICs. */
551 if (!(cpu_feature & CPUID_APIC))
552 return;
553
554 /* Don't probe if APIC mode is disabled. */
555 if (resource_disabled("apic", 0))
556 return;
557
558 /* First, probe all the enumerators to find the best match. */
559 best_enum = NULL;
560 best = 0;
561 SLIST_FOREACH(enumerator, &enumerators, apic_next) {
562 retval = enumerator->apic_probe();
563 if (retval > 0)
564 continue;
565 if (best_enum == NULL || best < retval) {
566 best_enum = enumerator;
567 best = retval;
568 }
569 }
570 if (best_enum == NULL) {
571 if (bootverbose)
572 printf("APIC: Could not find any APICs.\n");
573 return;
574 }
575
576 if (bootverbose)
577 printf("APIC: Using the %s enumerator.\n",
578 best_enum->apic_name);
579
580 /* Second, probe the CPU's in the system. */
581 retval = best_enum->apic_probe_cpus();
582 if (retval != 0)
583 printf("%s: Failed to probe CPUs: returned %d\n",
584 best_enum->apic_name, retval);
585 }
586 SYSINIT(apic_init, SI_SUB_TUNABLES - 1, SI_ORDER_SECOND, apic_init, NULL)
587
588 /*
589 * Setup the local APIC. We have to do this prior to starting up the APs
590 * in the SMP case.
591 */
592 static void
593 apic_setup_local(void *dummy __unused)
594 {
595 int retval;
596
597 if (best_enum == NULL)
598 return;
599 retval = best_enum->apic_setup_local();
600 if (retval != 0)
601 printf("%s: Failed to setup the local APIC: returned %d\n",
602 best_enum->apic_name, retval);
603 }
604 SYSINIT(apic_setup_local, SI_SUB_CPU, SI_ORDER_FIRST, apic_setup_local, NULL)
605
606 /*
607 * Setup the I/O APICs.
608 */
609 static void
610 apic_setup_io(void *dummy __unused)
611 {
612 int retval;
613
614 if (best_enum == NULL)
615 return;
616 retval = best_enum->apic_setup_io();
617 if (retval != 0)
618 printf("%s: Failed to setup I/O APICs: returned %d\n",
619 best_enum->apic_name, retval);
620
621 /*
622 * Finish setting up the local APIC on the BSP once we know how to
623 * properly program the LINT pins.
624 */
625 lapic_setup();
626 if (bootverbose)
627 lapic_dump("BSP");
628 }
629 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL)
630
631 #ifdef SMP
632 /*
633 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are
634 * private the sys/i386 code. The public interface for the rest of the
635 * kernel is defined in mp_machdep.c.
636 */
637 #define DETECT_DEADLOCK
638
639 int
640 lapic_ipi_wait(int delay)
641 {
642 int x, incr;
643
644 /*
645 * Wait delay loops for IPI to be sent. This is highly bogus
646 * since this is sensitive to CPU clock speed. If delay is
647 * -1, we wait forever.
648 */
649 if (delay == -1) {
650 incr = 0;
651 delay = 1;
652 } else
653 incr = 1;
654 for (x = 0; x < delay; x += incr) {
655 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE)
656 return (1);
657 ia32_pause();
658 }
659 return (0);
660 }
661
662 void
663 lapic_ipi_raw(register_t icrlo, u_int dest)
664 {
665 register_t value, eflags;
666
667 /* XXX: Need more sanity checking of icrlo? */
668 KASSERT(lapic != NULL, ("%s called too early", __func__));
669 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
670 ("%s: invalid dest field", __func__));
671 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
672 ("%s: reserved bits set in ICR LO register", __func__));
673
674 /* Set destination in ICR HI register if it is being used. */
675 eflags = intr_disable();
676 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
677 value = lapic->icr_hi;
678 value &= ~APIC_ID_MASK;
679 value |= dest << APIC_ID_SHIFT;
680 lapic->icr_hi = value;
681 }
682
683 /* Program the contents of the IPI and dispatch it. */
684 value = lapic->icr_lo;
685 value &= APIC_ICRLO_RESV_MASK;
686 value |= icrlo;
687 lapic->icr_lo = value;
688 intr_restore(eflags);
689 }
690
691 #ifdef DETECT_DEADLOCK
692 #define BEFORE_SPIN 1000000
693 #define AFTER_SPIN 1000
694 #endif
695
696 void
697 lapic_ipi_vectored(u_int vector, int dest)
698 {
699 register_t icrlo, destfield;
700
701 KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
702 ("%s: invalid vector %d", __func__, vector));
703
704 icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY |
705 APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE;
706 destfield = 0;
707 switch (dest) {
708 case APIC_IPI_DEST_SELF:
709 icrlo |= APIC_DEST_SELF;
710 break;
711 case APIC_IPI_DEST_ALL:
712 icrlo |= APIC_DEST_ALLISELF;
713 break;
714 case APIC_IPI_DEST_OTHERS:
715 icrlo |= APIC_DEST_ALLESELF;
716 break;
717 default:
718 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
719 ("%s: invalid destination 0x%x", __func__, dest));
720 destfield = dest;
721 }
722
723 #ifdef DETECT_DEADLOCK
724 /* Check for an earlier stuck IPI. */
725 if (!lapic_ipi_wait(BEFORE_SPIN))
726 panic("APIC: Previous IPI is stuck");
727 #endif
728
729 lapic_ipi_raw(icrlo, destfield);
730
731 #ifdef DETECT_DEADLOCK
732 /* Wait for IPI to be delivered. */
733 if (!lapic_ipi_wait(AFTER_SPIN)) {
734 #ifdef needsattention
735 /*
736 * XXX FIXME:
737 *
738 * The above function waits for the message to actually be
739 * delivered. It breaks out after an arbitrary timeout
740 * since the message should eventually be delivered (at
741 * least in theory) and that if it wasn't we would catch
742 * the failure with the check above when the next IPI is
743 * sent.
744 *
745 * We could skiip this wait entirely, EXCEPT it probably
746 * protects us from other routines that assume that the
747 * message was delivered and acted upon when this function
748 * returns.
749 */
750 printf("APIC: IPI might be stuck\n");
751 #else /* !needsattention */
752 /* Wait until mesage is sent without a timeout. */
753 while (lapic->icr_lo & APIC_DELSTAT_PEND)
754 ia32_pause();
755 #endif /* needsattention */
756 }
757 #endif /* DETECT_DEADLOCK */
758 }
759 #endif /* SMP */
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