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sys/amd64/amd64/local_apic.c
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1 /*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * Copyright (c) 1996, by Steve Passe 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Local APIC support on Pentium and later processors. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD: releng/6.1/sys/amd64/amd64/local_apic.c 158179 2006-04-30 16:44:43Z cvs2svn $"); 36 37 #include "opt_hwpmc_hooks.h" 38 39 #include "opt_ddb.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/lock.h> 46 #include <sys/mutex.h> 47 #include <sys/pcpu.h> 48 #include <sys/smp.h> 49 #include <sys/proc.h> 50 51 #include <vm/vm.h> 52 #include <vm/pmap.h> 53 54 #include <machine/apicreg.h> 55 #include <machine/cputypes.h> 56 #include <machine/frame.h> 57 #include <machine/intr_machdep.h> 58 #include <machine/apicvar.h> 59 #include <machine/md_var.h> 60 #include <machine/smp.h> 61 #include <machine/specialreg.h> 62 63 #ifdef DDB 64 #include <sys/interrupt.h> 65 #include <ddb/ddb.h> 66 #endif 67 68 /* 69 * We can handle up to 60 APICs via our logical cluster IDs, but currently 70 * the physical IDs on Intel processors up to the Pentium 4 are limited to 71 * 16. 72 */ 73 #define MAX_APICID 16 74 75 /* Sanity checks on IDT vectors. */ 76 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT); 77 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS); 78 CTASSERT(APIC_LOCAL_INTS == 240); 79 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT); 80 81 #define LAPIC_TIMER_HZ_DIVIDER 2 82 #define LAPIC_TIMER_STATHZ_DIVIDER 15 83 #define LAPIC_TIMER_PROFHZ_DIVIDER 3 84 85 /* Magic IRQ values for the timer and syscalls. */ 86 #define IRQ_TIMER (NUM_IO_INTS + 1) 87 #define IRQ_SYSCALL (NUM_IO_INTS + 2) 88 89 /* 90 * Support for local APICs. Local APICs manage interrupts on each 91 * individual processor as opposed to I/O APICs which receive interrupts 92 * from I/O devices and then forward them on to the local APICs. 93 * 94 * Local APICs can also send interrupts to each other thus providing the 95 * mechanism for IPIs. 96 */ 97 98 struct lvt { 99 u_int lvt_edgetrigger:1; 100 u_int lvt_activehi:1; 101 u_int lvt_masked:1; 102 u_int lvt_active:1; 103 u_int lvt_mode:16; 104 u_int lvt_vector:8; 105 }; 106 107 struct lapic { 108 struct lvt la_lvts[LVT_MAX + 1]; 109 u_int la_id:8; 110 u_int la_cluster:4; 111 u_int la_cluster_id:2; 112 u_int la_present:1; 113 u_long *la_timer_count; 114 u_long la_hard_ticks; 115 u_long la_stat_ticks; 116 u_long la_prof_ticks; 117 } static lapics[MAX_APICID]; 118 119 /* XXX: should thermal be an NMI? */ 120 121 /* Global defaults for local APIC LVT entries. */ 122 static struct lvt lvts[LVT_MAX + 1] = { 123 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */ 124 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */ 125 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */ 126 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */ 127 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */ 128 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */ 129 }; 130 131 static inthand_t *ioint_handlers[] = { 132 NULL, /* 0 - 31 */ 133 IDTVEC(apic_isr1), /* 32 - 63 */ 134 IDTVEC(apic_isr2), /* 64 - 95 */ 135 IDTVEC(apic_isr3), /* 96 - 127 */ 136 IDTVEC(apic_isr4), /* 128 - 159 */ 137 IDTVEC(apic_isr5), /* 160 - 191 */ 138 IDTVEC(apic_isr6), /* 192 - 223 */ 139 IDTVEC(apic_isr7), /* 224 - 255 */ 140 }; 141 142 /* Include IDT_SYSCALL to make indexing easier. */ 143 static u_int ioint_irqs[APIC_NUM_IOINTS + 1]; 144 145 static u_int32_t lapic_timer_divisors[] = { 146 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16, 147 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128 148 }; 149 150 volatile lapic_t *lapic; 151 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz; 152 153 static void lapic_enable(void); 154 static void lapic_timer_enable_intr(void); 155 static void lapic_timer_oneshot(u_int count); 156 static void lapic_timer_periodic(u_int count); 157 static void lapic_timer_set_divisor(u_int divisor); 158 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value); 159 160 static uint32_t 161 lvt_mode(struct lapic *la, u_int pin, uint32_t value) 162 { 163 struct lvt *lvt; 164 165 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin)); 166 if (la->la_lvts[pin].lvt_active) 167 lvt = &la->la_lvts[pin]; 168 else 169 lvt = &lvts[pin]; 170 171 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM | 172 APIC_LVT_VECTOR); 173 if (lvt->lvt_edgetrigger == 0) 174 value |= APIC_LVT_TM; 175 if (lvt->lvt_activehi == 0) 176 value |= APIC_LVT_IIPP_INTALO; 177 if (lvt->lvt_masked) 178 value |= APIC_LVT_M; 179 value |= lvt->lvt_mode; 180 switch (lvt->lvt_mode) { 181 case APIC_LVT_DM_NMI: 182 case APIC_LVT_DM_SMI: 183 case APIC_LVT_DM_INIT: 184 case APIC_LVT_DM_EXTINT: 185 if (!lvt->lvt_edgetrigger) { 186 printf("lapic%u: Forcing LINT%u to edge trigger\n", 187 la->la_id, pin); 188 value |= APIC_LVT_TM; 189 } 190 /* Use a vector of 0. */ 191 break; 192 case APIC_LVT_DM_FIXED: 193 value |= lvt->lvt_vector; 194 break; 195 default: 196 panic("bad APIC LVT delivery mode: %#x\n", value); 197 } 198 return (value); 199 } 200 201 /* 202 * Map the local APIC and setup necessary interrupt vectors. 203 */ 204 void 205 lapic_init(uintptr_t addr) 206 { 207 208 /* Map the local APIC and setup the spurious interrupt handler. */ 209 KASSERT(trunc_page(addr) == addr, 210 ("local APIC not aligned on a page boundary")); 211 lapic = (lapic_t *)pmap_mapdev(addr, sizeof(lapic_t)); 212 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 213 214 /* Perform basic initialization of the BSP's local APIC. */ 215 lapic_enable(); 216 ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL; 217 218 /* Set BSP's per-CPU local APIC ID. */ 219 PCPU_SET(apic_id, lapic_id()); 220 intr_add_cpu(PCPU_GET(apic_id)); 221 222 /* Local APIC timer interrupt. */ 223 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYSIGT, SEL_KPL, 0); 224 ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER; 225 226 /* XXX: error/thermal interrupts */ 227 } 228 229 /* 230 * Create a local APIC instance. 231 */ 232 void 233 lapic_create(u_int apic_id, int boot_cpu) 234 { 235 int i; 236 237 if (apic_id >= MAX_APICID) { 238 printf("APIC: Ignoring local APIC with ID %d\n", apic_id); 239 if (boot_cpu) 240 panic("Can't ignore BSP"); 241 return; 242 } 243 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u", 244 apic_id)); 245 246 /* 247 * Assume no local LVT overrides and a cluster of 0 and 248 * intra-cluster ID of 0. 249 */ 250 lapics[apic_id].la_present = 1; 251 lapics[apic_id].la_id = apic_id; 252 for (i = 0; i < LVT_MAX; i++) { 253 lapics[apic_id].la_lvts[i] = lvts[i]; 254 lapics[apic_id].la_lvts[i].lvt_active = 0; 255 } 256 257 #ifdef SMP 258 cpu_add(apic_id, boot_cpu); 259 #endif 260 } 261 262 /* 263 * Dump contents of local APIC registers 264 */ 265 void 266 lapic_dump(const char* str) 267 { 268 269 printf("cpu%d %s:\n", PCPU_GET(cpuid), str); 270 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n", 271 lapic->id, lapic->version, lapic->ldr, lapic->dfr); 272 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n", 273 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr); 274 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n", 275 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error, 276 lapic->lvt_pcint); 277 } 278 279 void 280 lapic_setup(void) 281 { 282 struct lapic *la; 283 u_int32_t maxlvt; 284 register_t eflags; 285 char buf[MAXCOMLEN + 1]; 286 287 la = &lapics[lapic_id()]; 288 KASSERT(la->la_present, ("missing APIC structure")); 289 eflags = intr_disable(); 290 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 291 292 /* Initialize the TPR to allow all interrupts. */ 293 lapic_set_tpr(0); 294 295 /* Setup spurious vector and enable the local APIC. */ 296 lapic_enable(); 297 298 /* Program LINT[01] LVT entries. */ 299 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0); 300 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1); 301 #ifdef HWPMC_HOOKS 302 /* Program the PMC LVT entry if present. */ 303 if (maxlvt >= LVT_PMC) 304 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 305 #endif 306 307 /* Program timer LVT and setup handler. */ 308 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer); 309 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid)); 310 intrcnt_add(buf, &la->la_timer_count); 311 if (PCPU_GET(cpuid) != 0) { 312 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor", 313 lapic_id())); 314 lapic_timer_set_divisor(lapic_timer_divisor); 315 lapic_timer_periodic(lapic_timer_period); 316 lapic_timer_enable_intr(); 317 } 318 319 /* XXX: Error and thermal LVTs */ 320 321 intr_restore(eflags); 322 } 323 324 /* 325 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so 326 * that it can drive hardclock, statclock, and profclock. This function 327 * returns true if it is able to use the local APIC timer to drive the 328 * clocks and false if it is not able. 329 */ 330 int 331 lapic_setup_clock(void) 332 { 333 u_long value; 334 335 /* Can't drive the timer without a local APIC. */ 336 if (lapic == NULL) 337 return (0); 338 339 /* Start off with a divisor of 2 (power on reset default). */ 340 lapic_timer_divisor = 2; 341 342 /* Try to calibrate the local APIC timer. */ 343 do { 344 lapic_timer_set_divisor(lapic_timer_divisor); 345 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT); 346 DELAY(2000000); 347 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer; 348 if (value != APIC_TIMER_MAX_COUNT) 349 break; 350 lapic_timer_divisor <<= 1; 351 } while (lapic_timer_divisor <= 128); 352 if (lapic_timer_divisor > 128) 353 panic("lapic: Divisor too big"); 354 value /= 2; 355 if (bootverbose) 356 printf("lapic: Divisor %lu, Frequency %lu hz\n", 357 lapic_timer_divisor, value); 358 359 /* 360 * We will drive the timer at a small multiple of hz and drive 361 * both of the other timers with similarly small but relatively 362 * prime divisors. 363 */ 364 lapic_timer_hz = hz * LAPIC_TIMER_HZ_DIVIDER; 365 stathz = lapic_timer_hz / LAPIC_TIMER_STATHZ_DIVIDER; 366 profhz = lapic_timer_hz / LAPIC_TIMER_PROFHZ_DIVIDER; 367 lapic_timer_period = value / lapic_timer_hz; 368 369 /* 370 * Start up the timer on the BSP. The APs will kick off their 371 * timer during lapic_setup(). 372 */ 373 lapic_timer_periodic(lapic_timer_period); 374 lapic_timer_enable_intr(); 375 return (1); 376 } 377 378 void 379 lapic_disable(void) 380 { 381 uint32_t value; 382 383 /* Software disable the local APIC. */ 384 value = lapic->svr; 385 value &= ~APIC_SVR_SWEN; 386 lapic->svr = value; 387 } 388 389 static void 390 lapic_enable(void) 391 { 392 u_int32_t value; 393 394 /* Program the spurious vector to enable the local APIC. */ 395 value = lapic->svr; 396 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS); 397 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT); 398 lapic->svr = value; 399 } 400 401 int 402 lapic_id(void) 403 { 404 405 KASSERT(lapic != NULL, ("local APIC is not mapped")); 406 return (lapic->id >> APIC_ID_SHIFT); 407 } 408 409 int 410 lapic_intr_pending(u_int vector) 411 { 412 volatile u_int32_t *irr; 413 414 /* 415 * The IRR registers are an array of 128-bit registers each of 416 * which only describes 32 interrupts in the low 32 bits.. Thus, 417 * we divide the vector by 32 to get the 128-bit index. We then 418 * multiply that index by 4 to get the equivalent index from 419 * treating the IRR as an array of 32-bit registers. Finally, we 420 * modulus the vector by 32 to determine the individual bit to 421 * test. 422 */ 423 irr = &lapic->irr0; 424 return (irr[(vector / 32) * 4] & 1 << (vector % 32)); 425 } 426 427 void 428 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 429 { 430 struct lapic *la; 431 432 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist", 433 __func__, apic_id)); 434 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big", 435 __func__, cluster)); 436 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID, 437 ("%s: intra cluster id %u too big", __func__, cluster_id)); 438 la = &lapics[apic_id]; 439 la->la_cluster = cluster; 440 la->la_cluster_id = cluster_id; 441 } 442 443 int 444 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked) 445 { 446 447 if (pin > LVT_MAX) 448 return (EINVAL); 449 if (apic_id == APIC_ID_ALL) { 450 lvts[pin].lvt_masked = masked; 451 if (bootverbose) 452 printf("lapic:"); 453 } else { 454 KASSERT(lapics[apic_id].la_present, 455 ("%s: missing APIC %u", __func__, apic_id)); 456 lapics[apic_id].la_lvts[pin].lvt_masked = masked; 457 lapics[apic_id].la_lvts[pin].lvt_active = 1; 458 if (bootverbose) 459 printf("lapic%u:", apic_id); 460 } 461 if (bootverbose) 462 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked"); 463 return (0); 464 } 465 466 int 467 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode) 468 { 469 struct lvt *lvt; 470 471 if (pin > LVT_MAX) 472 return (EINVAL); 473 if (apic_id == APIC_ID_ALL) { 474 lvt = &lvts[pin]; 475 if (bootverbose) 476 printf("lapic:"); 477 } else { 478 KASSERT(lapics[apic_id].la_present, 479 ("%s: missing APIC %u", __func__, apic_id)); 480 lvt = &lapics[apic_id].la_lvts[pin]; 481 lvt->lvt_active = 1; 482 if (bootverbose) 483 printf("lapic%u:", apic_id); 484 } 485 lvt->lvt_mode = mode; 486 switch (mode) { 487 case APIC_LVT_DM_NMI: 488 case APIC_LVT_DM_SMI: 489 case APIC_LVT_DM_INIT: 490 case APIC_LVT_DM_EXTINT: 491 lvt->lvt_edgetrigger = 1; 492 lvt->lvt_activehi = 1; 493 if (mode == APIC_LVT_DM_EXTINT) 494 lvt->lvt_masked = 1; 495 else 496 lvt->lvt_masked = 0; 497 break; 498 default: 499 panic("Unsupported delivery mode: 0x%x\n", mode); 500 } 501 if (bootverbose) { 502 printf(" Routing "); 503 switch (mode) { 504 case APIC_LVT_DM_NMI: 505 printf("NMI"); 506 break; 507 case APIC_LVT_DM_SMI: 508 printf("SMI"); 509 break; 510 case APIC_LVT_DM_INIT: 511 printf("INIT"); 512 break; 513 case APIC_LVT_DM_EXTINT: 514 printf("ExtINT"); 515 break; 516 } 517 printf(" -> LINT%u\n", pin); 518 } 519 return (0); 520 } 521 522 int 523 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol) 524 { 525 526 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM) 527 return (EINVAL); 528 if (apic_id == APIC_ID_ALL) { 529 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH); 530 if (bootverbose) 531 printf("lapic:"); 532 } else { 533 KASSERT(lapics[apic_id].la_present, 534 ("%s: missing APIC %u", __func__, apic_id)); 535 lapics[apic_id].la_lvts[pin].lvt_active = 1; 536 lapics[apic_id].la_lvts[pin].lvt_activehi = 537 (pol == INTR_POLARITY_HIGH); 538 if (bootverbose) 539 printf("lapic%u:", apic_id); 540 } 541 if (bootverbose) 542 printf(" LINT%u polarity: %s\n", pin, 543 pol == INTR_POLARITY_HIGH ? "high" : "low"); 544 return (0); 545 } 546 547 int 548 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger) 549 { 550 551 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM) 552 return (EINVAL); 553 if (apic_id == APIC_ID_ALL) { 554 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE); 555 if (bootverbose) 556 printf("lapic:"); 557 } else { 558 KASSERT(lapics[apic_id].la_present, 559 ("%s: missing APIC %u", __func__, apic_id)); 560 lapics[apic_id].la_lvts[pin].lvt_edgetrigger = 561 (trigger == INTR_TRIGGER_EDGE); 562 lapics[apic_id].la_lvts[pin].lvt_active = 1; 563 if (bootverbose) 564 printf("lapic%u:", apic_id); 565 } 566 if (bootverbose) 567 printf(" LINT%u trigger: %s\n", pin, 568 trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 569 return (0); 570 } 571 572 /* 573 * Adjust the TPR of the current CPU so that it blocks all interrupts below 574 * the passed in vector. 575 */ 576 void 577 lapic_set_tpr(u_int vector) 578 { 579 #ifdef CHEAP_TPR 580 lapic->tpr = vector; 581 #else 582 u_int32_t tpr; 583 584 tpr = lapic->tpr & ~APIC_TPR_PRIO; 585 tpr |= vector; 586 lapic->tpr = tpr; 587 #endif 588 } 589 590 void 591 lapic_eoi(void) 592 { 593 594 lapic->eoi = 0; 595 } 596 597 void 598 lapic_handle_intr(void *cookie, struct intrframe frame) 599 { 600 struct intsrc *isrc; 601 int vec = (uintptr_t)cookie; 602 603 if (vec == -1) 604 panic("Couldn't get vector from ISR!"); 605 isrc = intr_lookup_source(apic_idt_to_irq(vec)); 606 intr_execute_handlers(isrc, &frame); 607 } 608 609 void 610 lapic_handle_timer(struct clockframe frame) 611 { 612 struct lapic *la; 613 614 la = &lapics[PCPU_GET(apic_id)]; 615 (*la->la_timer_count)++; 616 critical_enter(); 617 618 /* Fire hardclock at hz. */ 619 la->la_hard_ticks += hz; 620 if (la->la_hard_ticks >= lapic_timer_hz) { 621 la->la_hard_ticks -= lapic_timer_hz; 622 if (PCPU_GET(cpuid) == 0) 623 hardclock(&frame); 624 else 625 hardclock_process(&frame); 626 } 627 628 /* Fire statclock at stathz. */ 629 la->la_stat_ticks += stathz; 630 if (la->la_stat_ticks >= lapic_timer_hz) { 631 la->la_stat_ticks -= lapic_timer_hz; 632 statclock(&frame); 633 } 634 635 /* Fire profclock at profhz, but only when needed. */ 636 la->la_prof_ticks += profhz; 637 if (la->la_prof_ticks >= lapic_timer_hz) { 638 la->la_prof_ticks -= lapic_timer_hz; 639 if (profprocs != 0) 640 profclock(&frame); 641 } 642 critical_exit(); 643 } 644 645 static void 646 lapic_timer_set_divisor(u_int divisor) 647 { 648 649 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor)); 650 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) / 651 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor)); 652 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1]; 653 } 654 655 static void 656 lapic_timer_oneshot(u_int count) 657 { 658 u_int32_t value; 659 660 value = lapic->lvt_timer; 661 value &= ~APIC_LVTT_TM; 662 value |= APIC_LVTT_TM_ONE_SHOT; 663 lapic->lvt_timer = value; 664 lapic->icr_timer = count; 665 } 666 667 static void 668 lapic_timer_periodic(u_int count) 669 { 670 u_int32_t value; 671 672 value = lapic->lvt_timer; 673 value &= ~APIC_LVTT_TM; 674 value |= APIC_LVTT_TM_PERIODIC; 675 lapic->lvt_timer = value; 676 lapic->icr_timer = count; 677 } 678 679 static void 680 lapic_timer_enable_intr(void) 681 { 682 u_int32_t value; 683 684 value = lapic->lvt_timer; 685 value &= ~APIC_LVT_M; 686 lapic->lvt_timer = value; 687 } 688 689 /* Request a free IDT vector to be used by the specified IRQ. */ 690 u_int 691 apic_alloc_vector(u_int irq) 692 { 693 u_int vector; 694 695 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 696 697 /* 698 * Search for a free vector. Currently we just use a very simple 699 * algorithm to find the first free vector. 700 */ 701 mtx_lock_spin(&icu_lock); 702 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 703 if (ioint_irqs[vector] != 0) 704 continue; 705 ioint_irqs[vector] = irq; 706 mtx_unlock_spin(&icu_lock); 707 return (vector + APIC_IO_INTS); 708 } 709 mtx_unlock_spin(&icu_lock); 710 panic("Couldn't find an APIC vector for IRQ %u", irq); 711 } 712 713 void 714 apic_enable_vector(u_int vector) 715 { 716 717 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 718 KASSERT(ioint_handlers[vector / 32] != NULL, 719 ("No ISR handler for vector %u", vector)); 720 setidt(vector, ioint_handlers[vector / 32], SDT_SYSIGT, SEL_KPL, 0); 721 } 722 723 /* Release an APIC vector when it's no longer in use. */ 724 void 725 apic_free_vector(u_int vector, u_int irq) 726 { 727 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 728 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 729 ("Vector %u does not map to an IRQ line", vector)); 730 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 731 KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch")); 732 mtx_lock_spin(&icu_lock); 733 ioint_irqs[vector - APIC_IO_INTS] = 0; 734 mtx_unlock_spin(&icu_lock); 735 } 736 737 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */ 738 u_int 739 apic_idt_to_irq(u_int vector) 740 { 741 742 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 743 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 744 ("Vector %u does not map to an IRQ line", vector)); 745 return (ioint_irqs[vector - APIC_IO_INTS]); 746 } 747 748 #ifdef DDB 749 /* 750 * Dump data about APIC IDT vector mappings. 751 */ 752 DB_SHOW_COMMAND(apic, db_show_apic) 753 { 754 struct intsrc *isrc; 755 int quit, i, verbose; 756 u_int irq; 757 758 quit = 0; 759 if (strcmp(modif, "vv") == 0) 760 verbose = 2; 761 else if (strcmp(modif, "v") == 0) 762 verbose = 1; 763 else 764 verbose = 0; 765 db_setup_paging(db_simple_pager, &quit, db_lines_per_page); 766 for (i = 0; i < APIC_NUM_IOINTS + 1 && !quit; i++) { 767 irq = ioint_irqs[i]; 768 if (irq != 0 && irq != IRQ_SYSCALL) { 769 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS); 770 if (irq == IRQ_TIMER) 771 db_printf("lapic timer\n"); 772 else if (irq < NUM_IO_INTS) { 773 isrc = intr_lookup_source(irq); 774 if (isrc == NULL || verbose == 0) 775 db_printf("IRQ %u\n", irq); 776 else 777 db_dump_intr_event(isrc->is_event, 778 verbose == 2); 779 } else 780 db_printf("IRQ %u ???\n", irq); 781 } 782 } 783 } 784 #endif 785 786 /* 787 * APIC probing support code. This includes code to manage enumerators. 788 */ 789 790 static SLIST_HEAD(, apic_enumerator) enumerators = 791 SLIST_HEAD_INITIALIZER(enumerators); 792 static struct apic_enumerator *best_enum; 793 794 void 795 apic_register_enumerator(struct apic_enumerator *enumerator) 796 { 797 #ifdef INVARIANTS 798 struct apic_enumerator *apic_enum; 799 800 SLIST_FOREACH(apic_enum, &enumerators, apic_next) { 801 if (apic_enum == enumerator) 802 panic("%s: Duplicate register of %s", __func__, 803 enumerator->apic_name); 804 } 805 #endif 806 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next); 807 } 808 809 /* 810 * We have to look for CPU's very, very early because certain subsystems 811 * want to know how many CPU's we have extremely early on in the boot 812 * process. 813 */ 814 static void 815 apic_init(void *dummy __unused) 816 { 817 struct apic_enumerator *enumerator; 818 int retval, best; 819 820 /* We only support built in local APICs. */ 821 if (!(cpu_feature & CPUID_APIC)) 822 return; 823 824 /* Don't probe if APIC mode is disabled. */ 825 if (resource_disabled("apic", 0)) 826 return; 827 828 /* First, probe all the enumerators to find the best match. */ 829 best_enum = NULL; 830 best = 0; 831 SLIST_FOREACH(enumerator, &enumerators, apic_next) { 832 retval = enumerator->apic_probe(); 833 if (retval > 0) 834 continue; 835 if (best_enum == NULL || best < retval) { 836 best_enum = enumerator; 837 best = retval; 838 } 839 } 840 if (best_enum == NULL) { 841 if (bootverbose) 842 printf("APIC: Could not find any APICs.\n"); 843 return; 844 } 845 846 if (bootverbose) 847 printf("APIC: Using the %s enumerator.\n", 848 best_enum->apic_name); 849 850 /* Second, probe the CPU's in the system. */ 851 retval = best_enum->apic_probe_cpus(); 852 if (retval != 0) 853 printf("%s: Failed to probe CPUs: returned %d\n", 854 best_enum->apic_name, retval); 855 } 856 SYSINIT(apic_init, SI_SUB_TUNABLES - 1, SI_ORDER_SECOND, apic_init, NULL) 857 858 /* 859 * Setup the local APIC. We have to do this prior to starting up the APs 860 * in the SMP case. 861 */ 862 static void 863 apic_setup_local(void *dummy __unused) 864 { 865 int retval; 866 867 if (best_enum == NULL) 868 return; 869 retval = best_enum->apic_setup_local(); 870 if (retval != 0) 871 printf("%s: Failed to setup the local APIC: returned %d\n", 872 best_enum->apic_name, retval); 873 #ifdef SMP 874 /* Last, setup the cpu topology now that we have probed CPUs */ 875 mp_topology(); 876 #endif 877 } 878 SYSINIT(apic_setup_local, SI_SUB_CPU, SI_ORDER_FIRST, apic_setup_local, NULL) 879 880 /* 881 * Setup the I/O APICs. 882 */ 883 static void 884 apic_setup_io(void *dummy __unused) 885 { 886 int retval; 887 888 if (best_enum == NULL) 889 return; 890 retval = best_enum->apic_setup_io(); 891 if (retval != 0) 892 printf("%s: Failed to setup I/O APICs: returned %d\n", 893 best_enum->apic_name, retval); 894 895 /* 896 * Finish setting up the local APIC on the BSP once we know how to 897 * properly program the LINT pins. 898 */ 899 lapic_setup(); 900 if (bootverbose) 901 lapic_dump("BSP"); 902 } 903 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL) 904 905 #ifdef SMP 906 /* 907 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are 908 * private to the sys/amd64 code. The public interface for the rest of the 909 * kernel is defined in mp_machdep.c. 910 */ 911 int 912 lapic_ipi_wait(int delay) 913 { 914 int x, incr; 915 916 /* 917 * Wait delay loops for IPI to be sent. This is highly bogus 918 * since this is sensitive to CPU clock speed. If delay is 919 * -1, we wait forever. 920 */ 921 if (delay == -1) { 922 incr = 0; 923 delay = 1; 924 } else 925 incr = 1; 926 for (x = 0; x < delay; x += incr) { 927 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE) 928 return (1); 929 ia32_pause(); 930 } 931 return (0); 932 } 933 934 void 935 lapic_ipi_raw(register_t icrlo, u_int dest) 936 { 937 register_t value, eflags; 938 939 /* XXX: Need more sanity checking of icrlo? */ 940 KASSERT(lapic != NULL, ("%s called too early", __func__)); 941 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 942 ("%s: invalid dest field", __func__)); 943 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0, 944 ("%s: reserved bits set in ICR LO register", __func__)); 945 946 /* Set destination in ICR HI register if it is being used. */ 947 eflags = intr_disable(); 948 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) { 949 value = lapic->icr_hi; 950 value &= ~APIC_ID_MASK; 951 value |= dest << APIC_ID_SHIFT; 952 lapic->icr_hi = value; 953 } 954 955 /* Program the contents of the IPI and dispatch it. */ 956 value = lapic->icr_lo; 957 value &= APIC_ICRLO_RESV_MASK; 958 value |= icrlo; 959 lapic->icr_lo = value; 960 intr_restore(eflags); 961 } 962 963 #define BEFORE_SPIN 1000000 964 #ifdef DETECT_DEADLOCK 965 #define AFTER_SPIN 1000 966 #endif 967 968 void 969 lapic_ipi_vectored(u_int vector, int dest) 970 { 971 register_t icrlo, destfield; 972 973 KASSERT((vector & ~APIC_VECTOR_MASK) == 0, 974 ("%s: invalid vector %d", __func__, vector)); 975 976 icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY | 977 APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE; 978 destfield = 0; 979 switch (dest) { 980 case APIC_IPI_DEST_SELF: 981 icrlo |= APIC_DEST_SELF; 982 break; 983 case APIC_IPI_DEST_ALL: 984 icrlo |= APIC_DEST_ALLISELF; 985 break; 986 case APIC_IPI_DEST_OTHERS: 987 icrlo |= APIC_DEST_ALLESELF; 988 break; 989 default: 990 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 991 ("%s: invalid destination 0x%x", __func__, dest)); 992 destfield = dest; 993 } 994 995 /* Wait for an earlier IPI to finish. */ 996 if (!lapic_ipi_wait(BEFORE_SPIN)) { 997 if (panicstr != NULL) 998 return; 999 else 1000 panic("APIC: Previous IPI is stuck"); 1001 } 1002 1003 lapic_ipi_raw(icrlo, destfield); 1004 1005 #ifdef DETECT_DEADLOCK 1006 /* Wait for IPI to be delivered. */ 1007 if (!lapic_ipi_wait(AFTER_SPIN)) { 1008 #ifdef needsattention 1009 /* 1010 * XXX FIXME: 1011 * 1012 * The above function waits for the message to actually be 1013 * delivered. It breaks out after an arbitrary timeout 1014 * since the message should eventually be delivered (at 1015 * least in theory) and that if it wasn't we would catch 1016 * the failure with the check above when the next IPI is 1017 * sent. 1018 * 1019 * We could skip this wait entirely, EXCEPT it probably 1020 * protects us from other routines that assume that the 1021 * message was delivered and acted upon when this function 1022 * returns. 1023 */ 1024 printf("APIC: IPI might be stuck\n"); 1025 #else /* !needsattention */ 1026 /* Wait until mesage is sent without a timeout. */ 1027 while (lapic->icr_lo & APIC_DELSTAT_PEND) 1028 ia32_pause(); 1029 #endif /* needsattention */ 1030 } 1031 #endif /* DETECT_DEADLOCK */ 1032 } 1033 #endif /* SMP */
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