1 /*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /*
31 * Local APIC support on Pentium and later processors.
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD: releng/6.2/sys/amd64/amd64/local_apic.c 163803 2006-10-30 18:03:04Z jhb $");
36
37 #include "opt_hwpmc_hooks.h"
38
39 #include "opt_ddb.h"
40
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/bus.h>
44 #include <sys/kernel.h>
45 #include <sys/lock.h>
46 #include <sys/mutex.h>
47 #include <sys/pcpu.h>
48 #include <sys/smp.h>
49 #include <sys/proc.h>
50
51 #include <vm/vm.h>
52 #include <vm/pmap.h>
53
54 #include <machine/apicreg.h>
55 #include <machine/cputypes.h>
56 #include <machine/frame.h>
57 #include <machine/intr_machdep.h>
58 #include <machine/apicvar.h>
59 #include <machine/md_var.h>
60 #include <machine/smp.h>
61 #include <machine/specialreg.h>
62
63 #ifdef DDB
64 #include <sys/interrupt.h>
65 #include <ddb/ddb.h>
66 #endif
67
68 /*
69 * We can handle up to 60 APICs via our logical cluster IDs, but currently
70 * the physical IDs on Intel processors up to the Pentium 4 are limited to
71 * 16.
72 */
73 #define MAX_APICID 16
74
75 /* Sanity checks on IDT vectors. */
76 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
77 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
78 CTASSERT(APIC_LOCAL_INTS == 240);
79 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
80
81 #define LAPIC_TIMER_HZ_DIVIDER 2
82 #define LAPIC_TIMER_STATHZ_DIVIDER 15
83 #define LAPIC_TIMER_PROFHZ_DIVIDER 3
84
85 /* Magic IRQ values for the timer and syscalls. */
86 #define IRQ_TIMER (NUM_IO_INTS + 1)
87 #define IRQ_SYSCALL (NUM_IO_INTS + 2)
88
89 /*
90 * Support for local APICs. Local APICs manage interrupts on each
91 * individual processor as opposed to I/O APICs which receive interrupts
92 * from I/O devices and then forward them on to the local APICs.
93 *
94 * Local APICs can also send interrupts to each other thus providing the
95 * mechanism for IPIs.
96 */
97
98 struct lvt {
99 u_int lvt_edgetrigger:1;
100 u_int lvt_activehi:1;
101 u_int lvt_masked:1;
102 u_int lvt_active:1;
103 u_int lvt_mode:16;
104 u_int lvt_vector:8;
105 };
106
107 struct lapic {
108 struct lvt la_lvts[LVT_MAX + 1];
109 u_int la_id:8;
110 u_int la_cluster:4;
111 u_int la_cluster_id:2;
112 u_int la_present:1;
113 u_long *la_timer_count;
114 u_long la_hard_ticks;
115 u_long la_stat_ticks;
116 u_long la_prof_ticks;
117 } static lapics[MAX_APICID];
118
119 /* XXX: should thermal be an NMI? */
120
121 /* Global defaults for local APIC LVT entries. */
122 static struct lvt lvts[LVT_MAX + 1] = {
123 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */
124 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */
125 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */
126 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */
127 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */
128 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */
129 };
130
131 static inthand_t *ioint_handlers[] = {
132 NULL, /* 0 - 31 */
133 IDTVEC(apic_isr1), /* 32 - 63 */
134 IDTVEC(apic_isr2), /* 64 - 95 */
135 IDTVEC(apic_isr3), /* 96 - 127 */
136 IDTVEC(apic_isr4), /* 128 - 159 */
137 IDTVEC(apic_isr5), /* 160 - 191 */
138 IDTVEC(apic_isr6), /* 192 - 223 */
139 IDTVEC(apic_isr7), /* 224 - 255 */
140 };
141
142 /* Include IDT_SYSCALL to make indexing easier. */
143 static u_int ioint_irqs[APIC_NUM_IOINTS + 1];
144
145 static u_int32_t lapic_timer_divisors[] = {
146 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
147 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
148 };
149
150 volatile lapic_t *lapic;
151 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz;
152
153 static void lapic_enable(void);
154 static void lapic_resume(struct pic *pic);
155 static void lapic_timer_enable_intr(void);
156 static void lapic_timer_oneshot(u_int count);
157 static void lapic_timer_periodic(u_int count);
158 static void lapic_timer_set_divisor(u_int divisor);
159 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
160
161 struct pic lapic_pic = { .pic_resume = lapic_resume };
162
163 static uint32_t
164 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
165 {
166 struct lvt *lvt;
167
168 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin));
169 if (la->la_lvts[pin].lvt_active)
170 lvt = &la->la_lvts[pin];
171 else
172 lvt = &lvts[pin];
173
174 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
175 APIC_LVT_VECTOR);
176 if (lvt->lvt_edgetrigger == 0)
177 value |= APIC_LVT_TM;
178 if (lvt->lvt_activehi == 0)
179 value |= APIC_LVT_IIPP_INTALO;
180 if (lvt->lvt_masked)
181 value |= APIC_LVT_M;
182 value |= lvt->lvt_mode;
183 switch (lvt->lvt_mode) {
184 case APIC_LVT_DM_NMI:
185 case APIC_LVT_DM_SMI:
186 case APIC_LVT_DM_INIT:
187 case APIC_LVT_DM_EXTINT:
188 if (!lvt->lvt_edgetrigger) {
189 printf("lapic%u: Forcing LINT%u to edge trigger\n",
190 la->la_id, pin);
191 value |= APIC_LVT_TM;
192 }
193 /* Use a vector of 0. */
194 break;
195 case APIC_LVT_DM_FIXED:
196 value |= lvt->lvt_vector;
197 break;
198 default:
199 panic("bad APIC LVT delivery mode: %#x\n", value);
200 }
201 return (value);
202 }
203
204 /*
205 * Map the local APIC and setup necessary interrupt vectors.
206 */
207 void
208 lapic_init(uintptr_t addr)
209 {
210
211 /* Map the local APIC and setup the spurious interrupt handler. */
212 KASSERT(trunc_page(addr) == addr,
213 ("local APIC not aligned on a page boundary"));
214 lapic = (lapic_t *)pmap_mapdev(addr, sizeof(lapic_t));
215 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0);
216
217 /* Perform basic initialization of the BSP's local APIC. */
218 lapic_enable();
219 ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
220
221 /* Set BSP's per-CPU local APIC ID. */
222 PCPU_SET(apic_id, lapic_id());
223 intr_add_cpu(PCPU_GET(apic_id));
224
225 /* Local APIC timer interrupt. */
226 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYSIGT, SEL_KPL, 0);
227 ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER;
228
229 /* XXX: error/thermal interrupts */
230 }
231
232 /*
233 * Create a local APIC instance.
234 */
235 void
236 lapic_create(u_int apic_id, int boot_cpu)
237 {
238 int i;
239
240 if (apic_id >= MAX_APICID) {
241 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
242 if (boot_cpu)
243 panic("Can't ignore BSP");
244 return;
245 }
246 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
247 apic_id));
248
249 /*
250 * Assume no local LVT overrides and a cluster of 0 and
251 * intra-cluster ID of 0.
252 */
253 lapics[apic_id].la_present = 1;
254 lapics[apic_id].la_id = apic_id;
255 for (i = 0; i < LVT_MAX; i++) {
256 lapics[apic_id].la_lvts[i] = lvts[i];
257 lapics[apic_id].la_lvts[i].lvt_active = 0;
258 }
259
260 #ifdef SMP
261 cpu_add(apic_id, boot_cpu);
262 #endif
263 }
264
265 /*
266 * Dump contents of local APIC registers
267 */
268 void
269 lapic_dump(const char* str)
270 {
271
272 printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
273 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n",
274 lapic->id, lapic->version, lapic->ldr, lapic->dfr);
275 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
276 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
277 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n",
278 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error,
279 lapic->lvt_pcint);
280 }
281
282 void
283 lapic_setup(int boot)
284 {
285 struct lapic *la;
286 u_int32_t maxlvt;
287 register_t eflags;
288 char buf[MAXCOMLEN + 1];
289
290 la = &lapics[lapic_id()];
291 KASSERT(la->la_present, ("missing APIC structure"));
292 eflags = intr_disable();
293 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
294
295 /* Initialize the TPR to allow all interrupts. */
296 lapic_set_tpr(0);
297
298 /* Setup spurious vector and enable the local APIC. */
299 lapic_enable();
300
301 /* Program LINT[01] LVT entries. */
302 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
303 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
304 #ifdef HWPMC_HOOKS
305 /* Program the PMC LVT entry if present. */
306 if (maxlvt >= LVT_PMC)
307 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
308 #endif
309
310 /* Program timer LVT and setup handler. */
311 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer);
312 if (boot) {
313 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid));
314 intrcnt_add(buf, &la->la_timer_count);
315 }
316
317 /* We don't setup the timer during boot on the BSP until later. */
318 if (!(boot && PCPU_GET(cpuid) == 0)) {
319 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor",
320 lapic_id()));
321 lapic_timer_set_divisor(lapic_timer_divisor);
322 lapic_timer_periodic(lapic_timer_period);
323 lapic_timer_enable_intr();
324 }
325
326 /* XXX: Error and thermal LVTs */
327
328 intr_restore(eflags);
329 }
330
331 /*
332 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so
333 * that it can drive hardclock, statclock, and profclock. This function
334 * returns true if it is able to use the local APIC timer to drive the
335 * clocks and false if it is not able.
336 */
337 int
338 lapic_setup_clock(void)
339 {
340 u_long value;
341
342 /* Can't drive the timer without a local APIC. */
343 if (lapic == NULL)
344 return (0);
345
346 /* Start off with a divisor of 2 (power on reset default). */
347 lapic_timer_divisor = 2;
348
349 /* Try to calibrate the local APIC timer. */
350 do {
351 lapic_timer_set_divisor(lapic_timer_divisor);
352 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
353 DELAY(2000000);
354 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
355 if (value != APIC_TIMER_MAX_COUNT)
356 break;
357 lapic_timer_divisor <<= 1;
358 } while (lapic_timer_divisor <= 128);
359 if (lapic_timer_divisor > 128)
360 panic("lapic: Divisor too big");
361 value /= 2;
362 if (bootverbose)
363 printf("lapic: Divisor %lu, Frequency %lu hz\n",
364 lapic_timer_divisor, value);
365
366 /*
367 * We will drive the timer at a small multiple of hz and drive
368 * both of the other timers with similarly small but relatively
369 * prime divisors.
370 */
371 lapic_timer_hz = hz * LAPIC_TIMER_HZ_DIVIDER;
372 stathz = lapic_timer_hz / LAPIC_TIMER_STATHZ_DIVIDER;
373 profhz = lapic_timer_hz / LAPIC_TIMER_PROFHZ_DIVIDER;
374 lapic_timer_period = value / lapic_timer_hz;
375
376 /*
377 * Start up the timer on the BSP. The APs will kick off their
378 * timer during lapic_setup().
379 */
380 lapic_timer_periodic(lapic_timer_period);
381 lapic_timer_enable_intr();
382 return (1);
383 }
384
385 void
386 lapic_disable(void)
387 {
388 uint32_t value;
389
390 /* Software disable the local APIC. */
391 value = lapic->svr;
392 value &= ~APIC_SVR_SWEN;
393 lapic->svr = value;
394 }
395
396 static void
397 lapic_enable(void)
398 {
399 u_int32_t value;
400
401 /* Program the spurious vector to enable the local APIC. */
402 value = lapic->svr;
403 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
404 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
405 lapic->svr = value;
406 }
407
408 /* Reset the local APIC on the BSP during resume. */
409 static void
410 lapic_resume(struct pic *pic)
411 {
412
413 lapic_setup(0);
414 }
415
416 int
417 lapic_id(void)
418 {
419
420 KASSERT(lapic != NULL, ("local APIC is not mapped"));
421 return (lapic->id >> APIC_ID_SHIFT);
422 }
423
424 int
425 lapic_intr_pending(u_int vector)
426 {
427 volatile u_int32_t *irr;
428
429 /*
430 * The IRR registers are an array of 128-bit registers each of
431 * which only describes 32 interrupts in the low 32 bits.. Thus,
432 * we divide the vector by 32 to get the 128-bit index. We then
433 * multiply that index by 4 to get the equivalent index from
434 * treating the IRR as an array of 32-bit registers. Finally, we
435 * modulus the vector by 32 to determine the individual bit to
436 * test.
437 */
438 irr = &lapic->irr0;
439 return (irr[(vector / 32) * 4] & 1 << (vector % 32));
440 }
441
442 void
443 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
444 {
445 struct lapic *la;
446
447 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
448 __func__, apic_id));
449 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
450 __func__, cluster));
451 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
452 ("%s: intra cluster id %u too big", __func__, cluster_id));
453 la = &lapics[apic_id];
454 la->la_cluster = cluster;
455 la->la_cluster_id = cluster_id;
456 }
457
458 int
459 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
460 {
461
462 if (pin > LVT_MAX)
463 return (EINVAL);
464 if (apic_id == APIC_ID_ALL) {
465 lvts[pin].lvt_masked = masked;
466 if (bootverbose)
467 printf("lapic:");
468 } else {
469 KASSERT(lapics[apic_id].la_present,
470 ("%s: missing APIC %u", __func__, apic_id));
471 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
472 lapics[apic_id].la_lvts[pin].lvt_active = 1;
473 if (bootverbose)
474 printf("lapic%u:", apic_id);
475 }
476 if (bootverbose)
477 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
478 return (0);
479 }
480
481 int
482 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
483 {
484 struct lvt *lvt;
485
486 if (pin > LVT_MAX)
487 return (EINVAL);
488 if (apic_id == APIC_ID_ALL) {
489 lvt = &lvts[pin];
490 if (bootverbose)
491 printf("lapic:");
492 } else {
493 KASSERT(lapics[apic_id].la_present,
494 ("%s: missing APIC %u", __func__, apic_id));
495 lvt = &lapics[apic_id].la_lvts[pin];
496 lvt->lvt_active = 1;
497 if (bootverbose)
498 printf("lapic%u:", apic_id);
499 }
500 lvt->lvt_mode = mode;
501 switch (mode) {
502 case APIC_LVT_DM_NMI:
503 case APIC_LVT_DM_SMI:
504 case APIC_LVT_DM_INIT:
505 case APIC_LVT_DM_EXTINT:
506 lvt->lvt_edgetrigger = 1;
507 lvt->lvt_activehi = 1;
508 if (mode == APIC_LVT_DM_EXTINT)
509 lvt->lvt_masked = 1;
510 else
511 lvt->lvt_masked = 0;
512 break;
513 default:
514 panic("Unsupported delivery mode: 0x%x\n", mode);
515 }
516 if (bootverbose) {
517 printf(" Routing ");
518 switch (mode) {
519 case APIC_LVT_DM_NMI:
520 printf("NMI");
521 break;
522 case APIC_LVT_DM_SMI:
523 printf("SMI");
524 break;
525 case APIC_LVT_DM_INIT:
526 printf("INIT");
527 break;
528 case APIC_LVT_DM_EXTINT:
529 printf("ExtINT");
530 break;
531 }
532 printf(" -> LINT%u\n", pin);
533 }
534 return (0);
535 }
536
537 int
538 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
539 {
540
541 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM)
542 return (EINVAL);
543 if (apic_id == APIC_ID_ALL) {
544 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
545 if (bootverbose)
546 printf("lapic:");
547 } else {
548 KASSERT(lapics[apic_id].la_present,
549 ("%s: missing APIC %u", __func__, apic_id));
550 lapics[apic_id].la_lvts[pin].lvt_active = 1;
551 lapics[apic_id].la_lvts[pin].lvt_activehi =
552 (pol == INTR_POLARITY_HIGH);
553 if (bootverbose)
554 printf("lapic%u:", apic_id);
555 }
556 if (bootverbose)
557 printf(" LINT%u polarity: %s\n", pin,
558 pol == INTR_POLARITY_HIGH ? "high" : "low");
559 return (0);
560 }
561
562 int
563 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger)
564 {
565
566 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
567 return (EINVAL);
568 if (apic_id == APIC_ID_ALL) {
569 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
570 if (bootverbose)
571 printf("lapic:");
572 } else {
573 KASSERT(lapics[apic_id].la_present,
574 ("%s: missing APIC %u", __func__, apic_id));
575 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
576 (trigger == INTR_TRIGGER_EDGE);
577 lapics[apic_id].la_lvts[pin].lvt_active = 1;
578 if (bootverbose)
579 printf("lapic%u:", apic_id);
580 }
581 if (bootverbose)
582 printf(" LINT%u trigger: %s\n", pin,
583 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
584 return (0);
585 }
586
587 /*
588 * Adjust the TPR of the current CPU so that it blocks all interrupts below
589 * the passed in vector.
590 */
591 void
592 lapic_set_tpr(u_int vector)
593 {
594 #ifdef CHEAP_TPR
595 lapic->tpr = vector;
596 #else
597 u_int32_t tpr;
598
599 tpr = lapic->tpr & ~APIC_TPR_PRIO;
600 tpr |= vector;
601 lapic->tpr = tpr;
602 #endif
603 }
604
605 void
606 lapic_eoi(void)
607 {
608
609 lapic->eoi = 0;
610 }
611
612 void
613 lapic_handle_intr(void *cookie, struct intrframe frame)
614 {
615 struct intsrc *isrc;
616 int vec = (uintptr_t)cookie;
617
618 if (vec == -1)
619 panic("Couldn't get vector from ISR!");
620 isrc = intr_lookup_source(apic_idt_to_irq(vec));
621 intr_execute_handlers(isrc, &frame);
622 }
623
624 void
625 lapic_handle_timer(struct clockframe frame)
626 {
627 struct lapic *la;
628
629 la = &lapics[PCPU_GET(apic_id)];
630 (*la->la_timer_count)++;
631 critical_enter();
632
633 /* Fire hardclock at hz. */
634 la->la_hard_ticks += hz;
635 if (la->la_hard_ticks >= lapic_timer_hz) {
636 la->la_hard_ticks -= lapic_timer_hz;
637 if (PCPU_GET(cpuid) == 0)
638 hardclock(&frame);
639 else
640 hardclock_process(&frame);
641 }
642
643 /* Fire statclock at stathz. */
644 la->la_stat_ticks += stathz;
645 if (la->la_stat_ticks >= lapic_timer_hz) {
646 la->la_stat_ticks -= lapic_timer_hz;
647 statclock(&frame);
648 }
649
650 /* Fire profclock at profhz, but only when needed. */
651 la->la_prof_ticks += profhz;
652 if (la->la_prof_ticks >= lapic_timer_hz) {
653 la->la_prof_ticks -= lapic_timer_hz;
654 if (profprocs != 0)
655 profclock(&frame);
656 }
657 critical_exit();
658 }
659
660 static void
661 lapic_timer_set_divisor(u_int divisor)
662 {
663
664 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor));
665 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) /
666 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor));
667 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1];
668 }
669
670 static void
671 lapic_timer_oneshot(u_int count)
672 {
673 u_int32_t value;
674
675 value = lapic->lvt_timer;
676 value &= ~APIC_LVTT_TM;
677 value |= APIC_LVTT_TM_ONE_SHOT;
678 lapic->lvt_timer = value;
679 lapic->icr_timer = count;
680 }
681
682 static void
683 lapic_timer_periodic(u_int count)
684 {
685 u_int32_t value;
686
687 value = lapic->lvt_timer;
688 value &= ~APIC_LVTT_TM;
689 value |= APIC_LVTT_TM_PERIODIC;
690 lapic->lvt_timer = value;
691 lapic->icr_timer = count;
692 }
693
694 static void
695 lapic_timer_enable_intr(void)
696 {
697 u_int32_t value;
698
699 value = lapic->lvt_timer;
700 value &= ~APIC_LVT_M;
701 lapic->lvt_timer = value;
702 }
703
704 /* Request a free IDT vector to be used by the specified IRQ. */
705 u_int
706 apic_alloc_vector(u_int irq)
707 {
708 u_int vector;
709
710 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
711
712 /*
713 * Search for a free vector. Currently we just use a very simple
714 * algorithm to find the first free vector.
715 */
716 mtx_lock_spin(&icu_lock);
717 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
718 if (ioint_irqs[vector] != 0)
719 continue;
720 ioint_irqs[vector] = irq;
721 mtx_unlock_spin(&icu_lock);
722 return (vector + APIC_IO_INTS);
723 }
724 mtx_unlock_spin(&icu_lock);
725 panic("Couldn't find an APIC vector for IRQ %u", irq);
726 }
727
728 void
729 apic_enable_vector(u_int vector)
730 {
731
732 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
733 KASSERT(ioint_handlers[vector / 32] != NULL,
734 ("No ISR handler for vector %u", vector));
735 setidt(vector, ioint_handlers[vector / 32], SDT_SYSIGT, SEL_KPL, 0);
736 }
737
738 /* Release an APIC vector when it's no longer in use. */
739 void
740 apic_free_vector(u_int vector, u_int irq)
741 {
742 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
743 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
744 ("Vector %u does not map to an IRQ line", vector));
745 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
746 KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch"));
747 mtx_lock_spin(&icu_lock);
748 ioint_irqs[vector - APIC_IO_INTS] = 0;
749 mtx_unlock_spin(&icu_lock);
750 }
751
752 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */
753 u_int
754 apic_idt_to_irq(u_int vector)
755 {
756
757 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
758 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
759 ("Vector %u does not map to an IRQ line", vector));
760 return (ioint_irqs[vector - APIC_IO_INTS]);
761 }
762
763 #ifdef DDB
764 /*
765 * Dump data about APIC IDT vector mappings.
766 */
767 DB_SHOW_COMMAND(apic, db_show_apic)
768 {
769 struct intsrc *isrc;
770 int quit, i, verbose;
771 u_int irq;
772
773 quit = 0;
774 if (strcmp(modif, "vv") == 0)
775 verbose = 2;
776 else if (strcmp(modif, "v") == 0)
777 verbose = 1;
778 else
779 verbose = 0;
780 db_setup_paging(db_simple_pager, &quit, db_lines_per_page);
781 for (i = 0; i < APIC_NUM_IOINTS + 1 && !quit; i++) {
782 irq = ioint_irqs[i];
783 if (irq != 0 && irq != IRQ_SYSCALL) {
784 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS);
785 if (irq == IRQ_TIMER)
786 db_printf("lapic timer\n");
787 else if (irq < NUM_IO_INTS) {
788 isrc = intr_lookup_source(irq);
789 if (isrc == NULL || verbose == 0)
790 db_printf("IRQ %u\n", irq);
791 else
792 db_dump_intr_event(isrc->is_event,
793 verbose == 2);
794 } else
795 db_printf("IRQ %u ???\n", irq);
796 }
797 }
798 }
799
800 static void
801 dump_mask(const char *prefix, uint32_t v, int base)
802 {
803 int i, first;
804
805 first = 1;
806 for (i = 0; i < 32; i++)
807 if (v & (1 << i)) {
808 if (first) {
809 db_printf("%s:", prefix);
810 first = 0;
811 }
812 db_printf(" %02x", base + i);
813 }
814 if (!first)
815 db_printf("\n");
816 }
817
818 /* Show info from the lapic regs for this CPU. */
819 DB_SHOW_COMMAND(lapic, db_show_lapic)
820 {
821 uint32_t v;
822
823 db_printf("lapic ID = %d\n", lapic_id());
824 v = lapic->version;
825 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4,
826 v & 0xf);
827 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT);
828 v = lapic->svr;
829 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR,
830 v & APIC_SVR_ENABLE ? "enabled" : "disabled");
831 db_printf("TPR = %02x\n", lapic->tpr);
832
833 #define dump_field(prefix, index) \
834 dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \
835 index * 32)
836
837 db_printf("In-service Interrupts:\n");
838 dump_field(isr, 0);
839 dump_field(isr, 1);
840 dump_field(isr, 2);
841 dump_field(isr, 3);
842 dump_field(isr, 4);
843 dump_field(isr, 5);
844 dump_field(isr, 6);
845 dump_field(isr, 7);
846
847 db_printf("TMR Interrupts:\n");
848 dump_field(tmr, 0);
849 dump_field(tmr, 1);
850 dump_field(tmr, 2);
851 dump_field(tmr, 3);
852 dump_field(tmr, 4);
853 dump_field(tmr, 5);
854 dump_field(tmr, 6);
855 dump_field(tmr, 7);
856
857 db_printf("IRR Interrupts:\n");
858 dump_field(irr, 0);
859 dump_field(irr, 1);
860 dump_field(irr, 2);
861 dump_field(irr, 3);
862 dump_field(irr, 4);
863 dump_field(irr, 5);
864 dump_field(irr, 6);
865 dump_field(irr, 7);
866
867 #undef dump_field
868 }
869 #endif
870
871 /*
872 * APIC probing support code. This includes code to manage enumerators.
873 */
874
875 static SLIST_HEAD(, apic_enumerator) enumerators =
876 SLIST_HEAD_INITIALIZER(enumerators);
877 static struct apic_enumerator *best_enum;
878
879 void
880 apic_register_enumerator(struct apic_enumerator *enumerator)
881 {
882 #ifdef INVARIANTS
883 struct apic_enumerator *apic_enum;
884
885 SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
886 if (apic_enum == enumerator)
887 panic("%s: Duplicate register of %s", __func__,
888 enumerator->apic_name);
889 }
890 #endif
891 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
892 }
893
894 /*
895 * We have to look for CPU's very, very early because certain subsystems
896 * want to know how many CPU's we have extremely early on in the boot
897 * process.
898 */
899 static void
900 apic_init(void *dummy __unused)
901 {
902 struct apic_enumerator *enumerator;
903 int retval, best;
904
905 /* We only support built in local APICs. */
906 if (!(cpu_feature & CPUID_APIC))
907 return;
908
909 /* Don't probe if APIC mode is disabled. */
910 if (resource_disabled("apic", 0))
911 return;
912
913 /* First, probe all the enumerators to find the best match. */
914 best_enum = NULL;
915 best = 0;
916 SLIST_FOREACH(enumerator, &enumerators, apic_next) {
917 retval = enumerator->apic_probe();
918 if (retval > 0)
919 continue;
920 if (best_enum == NULL || best < retval) {
921 best_enum = enumerator;
922 best = retval;
923 }
924 }
925 if (best_enum == NULL) {
926 if (bootverbose)
927 printf("APIC: Could not find any APICs.\n");
928 return;
929 }
930
931 if (bootverbose)
932 printf("APIC: Using the %s enumerator.\n",
933 best_enum->apic_name);
934
935 /* Second, probe the CPU's in the system. */
936 retval = best_enum->apic_probe_cpus();
937 if (retval != 0)
938 printf("%s: Failed to probe CPUs: returned %d\n",
939 best_enum->apic_name, retval);
940 }
941 SYSINIT(apic_init, SI_SUB_TUNABLES - 1, SI_ORDER_SECOND, apic_init, NULL)
942
943 /*
944 * Setup the local APIC. We have to do this prior to starting up the APs
945 * in the SMP case.
946 */
947 static void
948 apic_setup_local(void *dummy __unused)
949 {
950 int retval;
951
952 if (best_enum == NULL)
953 return;
954 retval = best_enum->apic_setup_local();
955 if (retval != 0)
956 printf("%s: Failed to setup the local APIC: returned %d\n",
957 best_enum->apic_name, retval);
958 #ifdef SMP
959 /* Last, setup the cpu topology now that we have probed CPUs */
960 mp_topology();
961 #endif
962 }
963 SYSINIT(apic_setup_local, SI_SUB_CPU, SI_ORDER_FIRST, apic_setup_local, NULL)
964
965 /*
966 * Setup the I/O APICs.
967 */
968 static void
969 apic_setup_io(void *dummy __unused)
970 {
971 int retval;
972
973 if (best_enum == NULL)
974 return;
975 retval = best_enum->apic_setup_io();
976 if (retval != 0)
977 printf("%s: Failed to setup I/O APICs: returned %d\n",
978 best_enum->apic_name, retval);
979
980 /*
981 * Finish setting up the local APIC on the BSP once we know how to
982 * properly program the LINT pins.
983 */
984 lapic_setup(1);
985 intr_register_pic(&lapic_pic);
986 if (bootverbose)
987 lapic_dump("BSP");
988 }
989 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL)
990
991 #ifdef SMP
992 /*
993 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are
994 * private to the sys/amd64 code. The public interface for the rest of the
995 * kernel is defined in mp_machdep.c.
996 */
997 int
998 lapic_ipi_wait(int delay)
999 {
1000 int x, incr;
1001
1002 /*
1003 * Wait delay loops for IPI to be sent. This is highly bogus
1004 * since this is sensitive to CPU clock speed. If delay is
1005 * -1, we wait forever.
1006 */
1007 if (delay == -1) {
1008 incr = 0;
1009 delay = 1;
1010 } else
1011 incr = 1;
1012 for (x = 0; x < delay; x += incr) {
1013 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE)
1014 return (1);
1015 ia32_pause();
1016 }
1017 return (0);
1018 }
1019
1020 void
1021 lapic_ipi_raw(register_t icrlo, u_int dest)
1022 {
1023 register_t value, eflags;
1024
1025 /* XXX: Need more sanity checking of icrlo? */
1026 KASSERT(lapic != NULL, ("%s called too early", __func__));
1027 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1028 ("%s: invalid dest field", __func__));
1029 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
1030 ("%s: reserved bits set in ICR LO register", __func__));
1031
1032 /* Set destination in ICR HI register if it is being used. */
1033 eflags = intr_disable();
1034 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
1035 value = lapic->icr_hi;
1036 value &= ~APIC_ID_MASK;
1037 value |= dest << APIC_ID_SHIFT;
1038 lapic->icr_hi = value;
1039 }
1040
1041 /* Program the contents of the IPI and dispatch it. */
1042 value = lapic->icr_lo;
1043 value &= APIC_ICRLO_RESV_MASK;
1044 value |= icrlo;
1045 lapic->icr_lo = value;
1046 intr_restore(eflags);
1047 }
1048
1049 #define BEFORE_SPIN 1000000
1050 #ifdef DETECT_DEADLOCK
1051 #define AFTER_SPIN 1000
1052 #endif
1053
1054 void
1055 lapic_ipi_vectored(u_int vector, int dest)
1056 {
1057 register_t icrlo, destfield;
1058
1059 KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
1060 ("%s: invalid vector %d", __func__, vector));
1061
1062 icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY |
1063 APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE;
1064 destfield = 0;
1065 switch (dest) {
1066 case APIC_IPI_DEST_SELF:
1067 icrlo |= APIC_DEST_SELF;
1068 break;
1069 case APIC_IPI_DEST_ALL:
1070 icrlo |= APIC_DEST_ALLISELF;
1071 break;
1072 case APIC_IPI_DEST_OTHERS:
1073 icrlo |= APIC_DEST_ALLESELF;
1074 break;
1075 default:
1076 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1077 ("%s: invalid destination 0x%x", __func__, dest));
1078 destfield = dest;
1079 }
1080
1081 /* Wait for an earlier IPI to finish. */
1082 if (!lapic_ipi_wait(BEFORE_SPIN)) {
1083 if (panicstr != NULL)
1084 return;
1085 else
1086 panic("APIC: Previous IPI is stuck");
1087 }
1088
1089 lapic_ipi_raw(icrlo, destfield);
1090
1091 #ifdef DETECT_DEADLOCK
1092 /* Wait for IPI to be delivered. */
1093 if (!lapic_ipi_wait(AFTER_SPIN)) {
1094 #ifdef needsattention
1095 /*
1096 * XXX FIXME:
1097 *
1098 * The above function waits for the message to actually be
1099 * delivered. It breaks out after an arbitrary timeout
1100 * since the message should eventually be delivered (at
1101 * least in theory) and that if it wasn't we would catch
1102 * the failure with the check above when the next IPI is
1103 * sent.
1104 *
1105 * We could skip this wait entirely, EXCEPT it probably
1106 * protects us from other routines that assume that the
1107 * message was delivered and acted upon when this function
1108 * returns.
1109 */
1110 printf("APIC: IPI might be stuck\n");
1111 #else /* !needsattention */
1112 /* Wait until mesage is sent without a timeout. */
1113 while (lapic->icr_lo & APIC_DELSTAT_PEND)
1114 ia32_pause();
1115 #endif /* needsattention */
1116 }
1117 #endif /* DETECT_DEADLOCK */
1118 }
1119 #endif /* SMP */
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