1 /*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /*
31 * Local APIC support on Pentium and later processors.
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD: releng/6.3/sys/amd64/amd64/local_apic.c 173886 2007-11-24 19:45:58Z cvs2svn $");
36
37 #include "opt_hwpmc_hooks.h"
38
39 #include "opt_ddb.h"
40
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/bus.h>
44 #include <sys/kernel.h>
45 #include <sys/lock.h>
46 #include <sys/mutex.h>
47 #include <sys/pcpu.h>
48 #include <sys/smp.h>
49 #include <sys/proc.h>
50
51 #include <vm/vm.h>
52 #include <vm/pmap.h>
53
54 #include <machine/apicreg.h>
55 #include <machine/cputypes.h>
56 #include <machine/frame.h>
57 #include <machine/intr_machdep.h>
58 #include <machine/apicvar.h>
59 #include <machine/md_var.h>
60 #include <machine/smp.h>
61 #include <machine/specialreg.h>
62
63 #ifdef DDB
64 #include <sys/interrupt.h>
65 #include <ddb/ddb.h>
66 #endif
67
68 /* Sanity checks on IDT vectors. */
69 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
70 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
71 CTASSERT(APIC_LOCAL_INTS == 240);
72 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
73
74 #define LAPIC_TIMER_HZ_DIVIDER 2
75 #define LAPIC_TIMER_STATHZ_DIVIDER 15
76 #define LAPIC_TIMER_PROFHZ_DIVIDER 3
77
78 /* Magic IRQ values for the timer and syscalls. */
79 #define IRQ_TIMER (NUM_IO_INTS + 1)
80 #define IRQ_SYSCALL (NUM_IO_INTS + 2)
81
82 /*
83 * Support for local APICs. Local APICs manage interrupts on each
84 * individual processor as opposed to I/O APICs which receive interrupts
85 * from I/O devices and then forward them on to the local APICs.
86 *
87 * Local APICs can also send interrupts to each other thus providing the
88 * mechanism for IPIs.
89 */
90
91 struct lvt {
92 u_int lvt_edgetrigger:1;
93 u_int lvt_activehi:1;
94 u_int lvt_masked:1;
95 u_int lvt_active:1;
96 u_int lvt_mode:16;
97 u_int lvt_vector:8;
98 };
99
100 struct lapic {
101 struct lvt la_lvts[LVT_MAX + 1];
102 u_int la_id:8;
103 u_int la_cluster:4;
104 u_int la_cluster_id:2;
105 u_int la_present:1;
106 u_long *la_timer_count;
107 u_long la_hard_ticks;
108 u_long la_stat_ticks;
109 u_long la_prof_ticks;
110 } static lapics[MAX_APIC_ID + 1];
111
112 /* XXX: should thermal be an NMI? */
113
114 /* Global defaults for local APIC LVT entries. */
115 static struct lvt lvts[LVT_MAX + 1] = {
116 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */
117 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */
118 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */
119 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */
120 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */
121 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */
122 };
123
124 static inthand_t *ioint_handlers[] = {
125 NULL, /* 0 - 31 */
126 IDTVEC(apic_isr1), /* 32 - 63 */
127 IDTVEC(apic_isr2), /* 64 - 95 */
128 IDTVEC(apic_isr3), /* 96 - 127 */
129 IDTVEC(apic_isr4), /* 128 - 159 */
130 IDTVEC(apic_isr5), /* 160 - 191 */
131 IDTVEC(apic_isr6), /* 192 - 223 */
132 IDTVEC(apic_isr7), /* 224 - 255 */
133 };
134
135 /* Include IDT_SYSCALL to make indexing easier. */
136 static u_int ioint_irqs[APIC_NUM_IOINTS + 1];
137
138 static u_int32_t lapic_timer_divisors[] = {
139 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
140 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
141 };
142
143 volatile lapic_t *lapic;
144 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz;
145
146 static void lapic_enable(void);
147 static void lapic_resume(struct pic *pic);
148 static void lapic_timer_enable_intr(void);
149 static void lapic_timer_oneshot(u_int count);
150 static void lapic_timer_periodic(u_int count);
151 static void lapic_timer_set_divisor(u_int divisor);
152 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
153
154 struct pic lapic_pic = { .pic_resume = lapic_resume };
155
156 static uint32_t
157 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
158 {
159 struct lvt *lvt;
160
161 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin));
162 if (la->la_lvts[pin].lvt_active)
163 lvt = &la->la_lvts[pin];
164 else
165 lvt = &lvts[pin];
166
167 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
168 APIC_LVT_VECTOR);
169 if (lvt->lvt_edgetrigger == 0)
170 value |= APIC_LVT_TM;
171 if (lvt->lvt_activehi == 0)
172 value |= APIC_LVT_IIPP_INTALO;
173 if (lvt->lvt_masked)
174 value |= APIC_LVT_M;
175 value |= lvt->lvt_mode;
176 switch (lvt->lvt_mode) {
177 case APIC_LVT_DM_NMI:
178 case APIC_LVT_DM_SMI:
179 case APIC_LVT_DM_INIT:
180 case APIC_LVT_DM_EXTINT:
181 if (!lvt->lvt_edgetrigger) {
182 printf("lapic%u: Forcing LINT%u to edge trigger\n",
183 la->la_id, pin);
184 value |= APIC_LVT_TM;
185 }
186 /* Use a vector of 0. */
187 break;
188 case APIC_LVT_DM_FIXED:
189 value |= lvt->lvt_vector;
190 break;
191 default:
192 panic("bad APIC LVT delivery mode: %#x\n", value);
193 }
194 return (value);
195 }
196
197 /*
198 * Map the local APIC and setup necessary interrupt vectors.
199 */
200 void
201 lapic_init(uintptr_t addr)
202 {
203
204 /* Map the local APIC and setup the spurious interrupt handler. */
205 KASSERT(trunc_page(addr) == addr,
206 ("local APIC not aligned on a page boundary"));
207 lapic = (lapic_t *)pmap_mapdev(addr, sizeof(lapic_t));
208 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0);
209
210 /* Perform basic initialization of the BSP's local APIC. */
211 lapic_enable();
212 ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
213
214 /* Set BSP's per-CPU local APIC ID. */
215 PCPU_SET(apic_id, lapic_id());
216 intr_add_cpu(PCPU_GET(apic_id));
217
218 /* Local APIC timer interrupt. */
219 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYSIGT, SEL_KPL, 0);
220 ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER;
221
222 /* XXX: error/thermal interrupts */
223 }
224
225 /*
226 * Create a local APIC instance.
227 */
228 void
229 lapic_create(u_int apic_id, int boot_cpu)
230 {
231 int i;
232
233 if (apic_id > MAX_APIC_ID) {
234 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
235 if (boot_cpu)
236 panic("Can't ignore BSP");
237 return;
238 }
239 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
240 apic_id));
241
242 /*
243 * Assume no local LVT overrides and a cluster of 0 and
244 * intra-cluster ID of 0.
245 */
246 lapics[apic_id].la_present = 1;
247 lapics[apic_id].la_id = apic_id;
248 for (i = 0; i < LVT_MAX; i++) {
249 lapics[apic_id].la_lvts[i] = lvts[i];
250 lapics[apic_id].la_lvts[i].lvt_active = 0;
251 }
252
253 #ifdef SMP
254 cpu_add(apic_id, boot_cpu);
255 #endif
256 }
257
258 /*
259 * Dump contents of local APIC registers
260 */
261 void
262 lapic_dump(const char* str)
263 {
264
265 printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
266 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n",
267 lapic->id, lapic->version, lapic->ldr, lapic->dfr);
268 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
269 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
270 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n",
271 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error,
272 lapic->lvt_pcint);
273 }
274
275 void
276 lapic_setup(int boot)
277 {
278 struct lapic *la;
279 u_int32_t maxlvt;
280 register_t eflags;
281 char buf[MAXCOMLEN + 1];
282
283 la = &lapics[lapic_id()];
284 KASSERT(la->la_present, ("missing APIC structure"));
285 eflags = intr_disable();
286 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
287
288 /* Initialize the TPR to allow all interrupts. */
289 lapic_set_tpr(0);
290
291 /* Setup spurious vector and enable the local APIC. */
292 lapic_enable();
293
294 /* Program LINT[01] LVT entries. */
295 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
296 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
297 #ifdef HWPMC_HOOKS
298 /* Program the PMC LVT entry if present. */
299 if (maxlvt >= LVT_PMC)
300 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
301 #endif
302
303 /* Program timer LVT and setup handler. */
304 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer);
305 if (boot) {
306 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid));
307 intrcnt_add(buf, &la->la_timer_count);
308 }
309
310 /* We don't setup the timer during boot on the BSP until later. */
311 if (!(boot && PCPU_GET(cpuid) == 0)) {
312 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor",
313 lapic_id()));
314 lapic_timer_set_divisor(lapic_timer_divisor);
315 lapic_timer_periodic(lapic_timer_period);
316 lapic_timer_enable_intr();
317 }
318
319 /* XXX: Error and thermal LVTs */
320
321 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
322 /*
323 * Detect the presence of C1E capability mostly on latest
324 * dual-cores (or future) k8 family. This feature renders
325 * the local APIC timer dead, so we disable it by reading
326 * the Interrupt Pending Message register and clearing both
327 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
328 *
329 * Reference:
330 * "BIOS and Kernel Developer's Guide for AMD NPT
331 * Family 0Fh Processors"
332 * #32559 revision 3.00
333 */
334 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
335 (cpu_id & 0x0fff0000) >= 0x00040000) {
336 uint64_t msr;
337
338 msr = rdmsr(0xc0010055);
339 if (msr & 0x18000000)
340 wrmsr(0xc0010055, msr & ~0x18000000ULL);
341 }
342 }
343
344 intr_restore(eflags);
345 }
346
347 /*
348 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so
349 * that it can drive hardclock, statclock, and profclock. This function
350 * returns true if it is able to use the local APIC timer to drive the
351 * clocks and false if it is not able.
352 */
353 int
354 lapic_setup_clock(void)
355 {
356 u_long value;
357
358 /* Can't drive the timer without a local APIC. */
359 if (lapic == NULL)
360 return (0);
361
362 /* Start off with a divisor of 2 (power on reset default). */
363 lapic_timer_divisor = 2;
364
365 /* Try to calibrate the local APIC timer. */
366 do {
367 lapic_timer_set_divisor(lapic_timer_divisor);
368 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
369 DELAY(2000000);
370 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
371 if (value != APIC_TIMER_MAX_COUNT)
372 break;
373 lapic_timer_divisor <<= 1;
374 } while (lapic_timer_divisor <= 128);
375 if (lapic_timer_divisor > 128)
376 panic("lapic: Divisor too big");
377 value /= 2;
378 if (bootverbose)
379 printf("lapic: Divisor %lu, Frequency %lu hz\n",
380 lapic_timer_divisor, value);
381
382 /*
383 * We will drive the timer at a small multiple of hz and drive
384 * both of the other timers with similarly small but relatively
385 * prime divisors.
386 */
387 lapic_timer_hz = hz * LAPIC_TIMER_HZ_DIVIDER;
388 stathz = lapic_timer_hz / LAPIC_TIMER_STATHZ_DIVIDER;
389 profhz = lapic_timer_hz / LAPIC_TIMER_PROFHZ_DIVIDER;
390 lapic_timer_period = value / lapic_timer_hz;
391
392 /*
393 * Start up the timer on the BSP. The APs will kick off their
394 * timer during lapic_setup().
395 */
396 lapic_timer_periodic(lapic_timer_period);
397 lapic_timer_enable_intr();
398 return (1);
399 }
400
401 void
402 lapic_disable(void)
403 {
404 uint32_t value;
405
406 /* Software disable the local APIC. */
407 value = lapic->svr;
408 value &= ~APIC_SVR_SWEN;
409 lapic->svr = value;
410 }
411
412 static void
413 lapic_enable(void)
414 {
415 u_int32_t value;
416
417 /* Program the spurious vector to enable the local APIC. */
418 value = lapic->svr;
419 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
420 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
421 lapic->svr = value;
422 }
423
424 /* Reset the local APIC on the BSP during resume. */
425 static void
426 lapic_resume(struct pic *pic)
427 {
428
429 lapic_setup(0);
430 }
431
432 int
433 lapic_id(void)
434 {
435
436 KASSERT(lapic != NULL, ("local APIC is not mapped"));
437 return (lapic->id >> APIC_ID_SHIFT);
438 }
439
440 int
441 lapic_intr_pending(u_int vector)
442 {
443 volatile u_int32_t *irr;
444
445 /*
446 * The IRR registers are an array of 128-bit registers each of
447 * which only describes 32 interrupts in the low 32 bits.. Thus,
448 * we divide the vector by 32 to get the 128-bit index. We then
449 * multiply that index by 4 to get the equivalent index from
450 * treating the IRR as an array of 32-bit registers. Finally, we
451 * modulus the vector by 32 to determine the individual bit to
452 * test.
453 */
454 irr = &lapic->irr0;
455 return (irr[(vector / 32) * 4] & 1 << (vector % 32));
456 }
457
458 void
459 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
460 {
461 struct lapic *la;
462
463 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
464 __func__, apic_id));
465 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
466 __func__, cluster));
467 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
468 ("%s: intra cluster id %u too big", __func__, cluster_id));
469 la = &lapics[apic_id];
470 la->la_cluster = cluster;
471 la->la_cluster_id = cluster_id;
472 }
473
474 int
475 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
476 {
477
478 if (pin > LVT_MAX)
479 return (EINVAL);
480 if (apic_id == APIC_ID_ALL) {
481 lvts[pin].lvt_masked = masked;
482 if (bootverbose)
483 printf("lapic:");
484 } else {
485 KASSERT(lapics[apic_id].la_present,
486 ("%s: missing APIC %u", __func__, apic_id));
487 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
488 lapics[apic_id].la_lvts[pin].lvt_active = 1;
489 if (bootverbose)
490 printf("lapic%u:", apic_id);
491 }
492 if (bootverbose)
493 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
494 return (0);
495 }
496
497 int
498 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
499 {
500 struct lvt *lvt;
501
502 if (pin > LVT_MAX)
503 return (EINVAL);
504 if (apic_id == APIC_ID_ALL) {
505 lvt = &lvts[pin];
506 if (bootverbose)
507 printf("lapic:");
508 } else {
509 KASSERT(lapics[apic_id].la_present,
510 ("%s: missing APIC %u", __func__, apic_id));
511 lvt = &lapics[apic_id].la_lvts[pin];
512 lvt->lvt_active = 1;
513 if (bootverbose)
514 printf("lapic%u:", apic_id);
515 }
516 lvt->lvt_mode = mode;
517 switch (mode) {
518 case APIC_LVT_DM_NMI:
519 case APIC_LVT_DM_SMI:
520 case APIC_LVT_DM_INIT:
521 case APIC_LVT_DM_EXTINT:
522 lvt->lvt_edgetrigger = 1;
523 lvt->lvt_activehi = 1;
524 if (mode == APIC_LVT_DM_EXTINT)
525 lvt->lvt_masked = 1;
526 else
527 lvt->lvt_masked = 0;
528 break;
529 default:
530 panic("Unsupported delivery mode: 0x%x\n", mode);
531 }
532 if (bootverbose) {
533 printf(" Routing ");
534 switch (mode) {
535 case APIC_LVT_DM_NMI:
536 printf("NMI");
537 break;
538 case APIC_LVT_DM_SMI:
539 printf("SMI");
540 break;
541 case APIC_LVT_DM_INIT:
542 printf("INIT");
543 break;
544 case APIC_LVT_DM_EXTINT:
545 printf("ExtINT");
546 break;
547 }
548 printf(" -> LINT%u\n", pin);
549 }
550 return (0);
551 }
552
553 int
554 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
555 {
556
557 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM)
558 return (EINVAL);
559 if (apic_id == APIC_ID_ALL) {
560 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
561 if (bootverbose)
562 printf("lapic:");
563 } else {
564 KASSERT(lapics[apic_id].la_present,
565 ("%s: missing APIC %u", __func__, apic_id));
566 lapics[apic_id].la_lvts[pin].lvt_active = 1;
567 lapics[apic_id].la_lvts[pin].lvt_activehi =
568 (pol == INTR_POLARITY_HIGH);
569 if (bootverbose)
570 printf("lapic%u:", apic_id);
571 }
572 if (bootverbose)
573 printf(" LINT%u polarity: %s\n", pin,
574 pol == INTR_POLARITY_HIGH ? "high" : "low");
575 return (0);
576 }
577
578 int
579 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger)
580 {
581
582 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
583 return (EINVAL);
584 if (apic_id == APIC_ID_ALL) {
585 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
586 if (bootverbose)
587 printf("lapic:");
588 } else {
589 KASSERT(lapics[apic_id].la_present,
590 ("%s: missing APIC %u", __func__, apic_id));
591 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
592 (trigger == INTR_TRIGGER_EDGE);
593 lapics[apic_id].la_lvts[pin].lvt_active = 1;
594 if (bootverbose)
595 printf("lapic%u:", apic_id);
596 }
597 if (bootverbose)
598 printf(" LINT%u trigger: %s\n", pin,
599 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
600 return (0);
601 }
602
603 /*
604 * Adjust the TPR of the current CPU so that it blocks all interrupts below
605 * the passed in vector.
606 */
607 void
608 lapic_set_tpr(u_int vector)
609 {
610 #ifdef CHEAP_TPR
611 lapic->tpr = vector;
612 #else
613 u_int32_t tpr;
614
615 tpr = lapic->tpr & ~APIC_TPR_PRIO;
616 tpr |= vector;
617 lapic->tpr = tpr;
618 #endif
619 }
620
621 void
622 lapic_eoi(void)
623 {
624
625 lapic->eoi = 0;
626 }
627
628 void
629 lapic_handle_intr(void *cookie, struct intrframe frame)
630 {
631 struct intsrc *isrc;
632 int vec = (uintptr_t)cookie;
633
634 if (vec == -1)
635 panic("Couldn't get vector from ISR!");
636 isrc = intr_lookup_source(apic_idt_to_irq(vec));
637 intr_execute_handlers(isrc, &frame);
638 }
639
640 void
641 lapic_handle_timer(struct clockframe frame)
642 {
643 struct lapic *la;
644
645 #if defined(SMP) && !defined(SCHED_ULE)
646 /*
647 * Don't do any accounting for the disabled HTT cores, since it
648 * will provide misleading numbers for the userland.
649 *
650 * No locking is necessary here, since even if we loose the race
651 * when hlt_cpus_mask changes it is not a big deal, really.
652 *
653 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask
654 * and unlike other schedulers it actually schedules threads to
655 * those CPUs.
656 */
657 if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0)
658 return;
659 #endif
660
661 la = &lapics[PCPU_GET(apic_id)];
662 (*la->la_timer_count)++;
663 critical_enter();
664
665 /* Fire hardclock at hz. */
666 la->la_hard_ticks += hz;
667 if (la->la_hard_ticks >= lapic_timer_hz) {
668 la->la_hard_ticks -= lapic_timer_hz;
669 if (PCPU_GET(cpuid) == 0)
670 hardclock(&frame);
671 else
672 hardclock_process(&frame);
673 }
674
675 /* Fire statclock at stathz. */
676 la->la_stat_ticks += stathz;
677 if (la->la_stat_ticks >= lapic_timer_hz) {
678 la->la_stat_ticks -= lapic_timer_hz;
679 statclock(&frame);
680 }
681
682 /* Fire profclock at profhz, but only when needed. */
683 la->la_prof_ticks += profhz;
684 if (la->la_prof_ticks >= lapic_timer_hz) {
685 la->la_prof_ticks -= lapic_timer_hz;
686 if (profprocs != 0)
687 profclock(&frame);
688 }
689 critical_exit();
690 }
691
692 static void
693 lapic_timer_set_divisor(u_int divisor)
694 {
695
696 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor));
697 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) /
698 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor));
699 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1];
700 }
701
702 static void
703 lapic_timer_oneshot(u_int count)
704 {
705 u_int32_t value;
706
707 value = lapic->lvt_timer;
708 value &= ~APIC_LVTT_TM;
709 value |= APIC_LVTT_TM_ONE_SHOT;
710 lapic->lvt_timer = value;
711 lapic->icr_timer = count;
712 }
713
714 static void
715 lapic_timer_periodic(u_int count)
716 {
717 u_int32_t value;
718
719 value = lapic->lvt_timer;
720 value &= ~APIC_LVTT_TM;
721 value |= APIC_LVTT_TM_PERIODIC;
722 lapic->lvt_timer = value;
723 lapic->icr_timer = count;
724 }
725
726 static void
727 lapic_timer_enable_intr(void)
728 {
729 u_int32_t value;
730
731 value = lapic->lvt_timer;
732 value &= ~APIC_LVT_M;
733 lapic->lvt_timer = value;
734 }
735
736 /* Request a free IDT vector to be used by the specified IRQ. */
737 u_int
738 apic_alloc_vector(u_int irq)
739 {
740 u_int vector;
741
742 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
743
744 /*
745 * Search for a free vector. Currently we just use a very simple
746 * algorithm to find the first free vector.
747 */
748 mtx_lock_spin(&icu_lock);
749 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
750 if (ioint_irqs[vector] != 0)
751 continue;
752 ioint_irqs[vector] = irq;
753 mtx_unlock_spin(&icu_lock);
754 return (vector + APIC_IO_INTS);
755 }
756 mtx_unlock_spin(&icu_lock);
757 panic("Couldn't find an APIC vector for IRQ %u", irq);
758 }
759
760 /*
761 * Request 'count' free contiguous IDT vectors to be used by 'count'
762 * IRQs. 'count' must be a power of two and the vectors will be
763 * aligned on a boundary of 'align'. If the request cannot be
764 * satisfied, 0 is returned.
765 */
766 u_int
767 apic_alloc_vectors(u_int *irqs, u_int count, u_int align)
768 {
769 u_int first, run, vector;
770
771 KASSERT(powerof2(count), ("bad count"));
772 KASSERT(powerof2(align), ("bad align"));
773 KASSERT(align >= count, ("align < count"));
774 #ifdef INVARIANTS
775 for (run = 0; run < count; run++)
776 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u",
777 irqs[run], run));
778 #endif
779
780 /*
781 * Search for 'count' free vectors. As with apic_alloc_vector(),
782 * this just uses a simple first fit algorithm.
783 */
784 run = 0;
785 first = 0;
786 mtx_lock_spin(&icu_lock);
787 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
788
789 /* Vector is in use, end run. */
790 if (ioint_irqs[vector] != 0) {
791 run = 0;
792 first = 0;
793 continue;
794 }
795
796 /* Start a new run if run == 0 and vector is aligned. */
797 if (run == 0) {
798 if ((vector & (align - 1)) != 0)
799 continue;
800 first = vector;
801 }
802 run++;
803
804 /* Keep looping if the run isn't long enough yet. */
805 if (run < count)
806 continue;
807
808 /* Found a run, assign IRQs and return the first vector. */
809 for (vector = 0; vector < count; vector++)
810 ioint_irqs[first + vector] = irqs[vector];
811 mtx_unlock_spin(&icu_lock);
812 return (first + APIC_IO_INTS);
813 }
814 mtx_unlock_spin(&icu_lock);
815 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count);
816 return (0);
817 }
818
819 void
820 apic_enable_vector(u_int vector)
821 {
822
823 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
824 KASSERT(ioint_handlers[vector / 32] != NULL,
825 ("No ISR handler for vector %u", vector));
826 setidt(vector, ioint_handlers[vector / 32], SDT_SYSIGT, SEL_KPL, 0);
827 }
828
829 /* Release an APIC vector when it's no longer in use. */
830 void
831 apic_free_vector(u_int vector, u_int irq)
832 {
833 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
834 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
835 ("Vector %u does not map to an IRQ line", vector));
836 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
837 KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch"));
838 mtx_lock_spin(&icu_lock);
839 ioint_irqs[vector - APIC_IO_INTS] = 0;
840 mtx_unlock_spin(&icu_lock);
841 }
842
843 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */
844 u_int
845 apic_idt_to_irq(u_int vector)
846 {
847
848 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
849 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
850 ("Vector %u does not map to an IRQ line", vector));
851 return (ioint_irqs[vector - APIC_IO_INTS]);
852 }
853
854 #ifdef DDB
855 /*
856 * Dump data about APIC IDT vector mappings.
857 */
858 DB_SHOW_COMMAND(apic, db_show_apic)
859 {
860 struct intsrc *isrc;
861 int quit, i, verbose;
862 u_int irq;
863
864 quit = 0;
865 if (strcmp(modif, "vv") == 0)
866 verbose = 2;
867 else if (strcmp(modif, "v") == 0)
868 verbose = 1;
869 else
870 verbose = 0;
871 db_setup_paging(db_simple_pager, &quit, db_lines_per_page);
872 for (i = 0; i < APIC_NUM_IOINTS + 1 && !quit; i++) {
873 irq = ioint_irqs[i];
874 if (irq != 0 && irq != IRQ_SYSCALL) {
875 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS);
876 if (irq == IRQ_TIMER)
877 db_printf("lapic timer\n");
878 else if (irq < NUM_IO_INTS) {
879 isrc = intr_lookup_source(irq);
880 if (isrc == NULL || verbose == 0)
881 db_printf("IRQ %u\n", irq);
882 else
883 db_dump_intr_event(isrc->is_event,
884 verbose == 2);
885 } else
886 db_printf("IRQ %u ???\n", irq);
887 }
888 }
889 }
890
891 static void
892 dump_mask(const char *prefix, uint32_t v, int base)
893 {
894 int i, first;
895
896 first = 1;
897 for (i = 0; i < 32; i++)
898 if (v & (1 << i)) {
899 if (first) {
900 db_printf("%s:", prefix);
901 first = 0;
902 }
903 db_printf(" %02x", base + i);
904 }
905 if (!first)
906 db_printf("\n");
907 }
908
909 /* Show info from the lapic regs for this CPU. */
910 DB_SHOW_COMMAND(lapic, db_show_lapic)
911 {
912 uint32_t v;
913
914 db_printf("lapic ID = %d\n", lapic_id());
915 v = lapic->version;
916 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4,
917 v & 0xf);
918 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT);
919 v = lapic->svr;
920 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR,
921 v & APIC_SVR_ENABLE ? "enabled" : "disabled");
922 db_printf("TPR = %02x\n", lapic->tpr);
923
924 #define dump_field(prefix, index) \
925 dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \
926 index * 32)
927
928 db_printf("In-service Interrupts:\n");
929 dump_field(isr, 0);
930 dump_field(isr, 1);
931 dump_field(isr, 2);
932 dump_field(isr, 3);
933 dump_field(isr, 4);
934 dump_field(isr, 5);
935 dump_field(isr, 6);
936 dump_field(isr, 7);
937
938 db_printf("TMR Interrupts:\n");
939 dump_field(tmr, 0);
940 dump_field(tmr, 1);
941 dump_field(tmr, 2);
942 dump_field(tmr, 3);
943 dump_field(tmr, 4);
944 dump_field(tmr, 5);
945 dump_field(tmr, 6);
946 dump_field(tmr, 7);
947
948 db_printf("IRR Interrupts:\n");
949 dump_field(irr, 0);
950 dump_field(irr, 1);
951 dump_field(irr, 2);
952 dump_field(irr, 3);
953 dump_field(irr, 4);
954 dump_field(irr, 5);
955 dump_field(irr, 6);
956 dump_field(irr, 7);
957
958 #undef dump_field
959 }
960 #endif
961
962 /*
963 * APIC probing support code. This includes code to manage enumerators.
964 */
965
966 static SLIST_HEAD(, apic_enumerator) enumerators =
967 SLIST_HEAD_INITIALIZER(enumerators);
968 static struct apic_enumerator *best_enum;
969
970 void
971 apic_register_enumerator(struct apic_enumerator *enumerator)
972 {
973 #ifdef INVARIANTS
974 struct apic_enumerator *apic_enum;
975
976 SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
977 if (apic_enum == enumerator)
978 panic("%s: Duplicate register of %s", __func__,
979 enumerator->apic_name);
980 }
981 #endif
982 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
983 }
984
985 /*
986 * We have to look for CPU's very, very early because certain subsystems
987 * want to know how many CPU's we have extremely early on in the boot
988 * process.
989 */
990 static void
991 apic_init(void *dummy __unused)
992 {
993 struct apic_enumerator *enumerator;
994 int retval, best;
995
996 /* Don't probe if APIC mode is disabled. */
997 if (resource_disabled("apic", 0))
998 return;
999
1000 /* First, probe all the enumerators to find the best match. */
1001 best_enum = NULL;
1002 best = 0;
1003 SLIST_FOREACH(enumerator, &enumerators, apic_next) {
1004 retval = enumerator->apic_probe();
1005 if (retval > 0)
1006 continue;
1007 if (best_enum == NULL || best < retval) {
1008 best_enum = enumerator;
1009 best = retval;
1010 }
1011 }
1012 if (best_enum == NULL) {
1013 if (bootverbose)
1014 printf("APIC: Could not find any APICs.\n");
1015 return;
1016 }
1017
1018 if (bootverbose)
1019 printf("APIC: Using the %s enumerator.\n",
1020 best_enum->apic_name);
1021
1022 /* Second, probe the CPU's in the system. */
1023 retval = best_enum->apic_probe_cpus();
1024 if (retval != 0)
1025 printf("%s: Failed to probe CPUs: returned %d\n",
1026 best_enum->apic_name, retval);
1027 }
1028 SYSINIT(apic_init, SI_SUB_TUNABLES - 1, SI_ORDER_SECOND, apic_init, NULL)
1029
1030 /*
1031 * Setup the local APIC. We have to do this prior to starting up the APs
1032 * in the SMP case.
1033 */
1034 static void
1035 apic_setup_local(void *dummy __unused)
1036 {
1037 int retval;
1038
1039 if (best_enum == NULL)
1040 return;
1041 retval = best_enum->apic_setup_local();
1042 if (retval != 0)
1043 printf("%s: Failed to setup the local APIC: returned %d\n",
1044 best_enum->apic_name, retval);
1045 #ifdef SMP
1046 /* Last, setup the cpu topology now that we have probed CPUs */
1047 mp_topology();
1048 #endif
1049 }
1050 SYSINIT(apic_setup_local, SI_SUB_CPU, SI_ORDER_FIRST, apic_setup_local, NULL)
1051
1052 /*
1053 * Setup the I/O APICs.
1054 */
1055 static void
1056 apic_setup_io(void *dummy __unused)
1057 {
1058 int retval;
1059
1060 if (best_enum == NULL)
1061 return;
1062 retval = best_enum->apic_setup_io();
1063 if (retval != 0)
1064 printf("%s: Failed to setup I/O APICs: returned %d\n",
1065 best_enum->apic_name, retval);
1066
1067 /*
1068 * Finish setting up the local APIC on the BSP once we know how to
1069 * properly program the LINT pins.
1070 */
1071 lapic_setup(1);
1072 intr_register_pic(&lapic_pic);
1073 if (bootverbose)
1074 lapic_dump("BSP");
1075
1076 /* Enable the MSI "pic". */
1077 msi_init();
1078 }
1079 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL)
1080
1081 #ifdef SMP
1082 /*
1083 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are
1084 * private to the sys/amd64 code. The public interface for the rest of the
1085 * kernel is defined in mp_machdep.c.
1086 */
1087 int
1088 lapic_ipi_wait(int delay)
1089 {
1090 int x, incr;
1091
1092 /*
1093 * Wait delay loops for IPI to be sent. This is highly bogus
1094 * since this is sensitive to CPU clock speed. If delay is
1095 * -1, we wait forever.
1096 */
1097 if (delay == -1) {
1098 incr = 0;
1099 delay = 1;
1100 } else
1101 incr = 1;
1102 for (x = 0; x < delay; x += incr) {
1103 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE)
1104 return (1);
1105 ia32_pause();
1106 }
1107 return (0);
1108 }
1109
1110 void
1111 lapic_ipi_raw(register_t icrlo, u_int dest)
1112 {
1113 register_t value, eflags;
1114
1115 /* XXX: Need more sanity checking of icrlo? */
1116 KASSERT(lapic != NULL, ("%s called too early", __func__));
1117 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1118 ("%s: invalid dest field", __func__));
1119 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
1120 ("%s: reserved bits set in ICR LO register", __func__));
1121
1122 /* Set destination in ICR HI register if it is being used. */
1123 eflags = intr_disable();
1124 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
1125 value = lapic->icr_hi;
1126 value &= ~APIC_ID_MASK;
1127 value |= dest << APIC_ID_SHIFT;
1128 lapic->icr_hi = value;
1129 }
1130
1131 /* Program the contents of the IPI and dispatch it. */
1132 value = lapic->icr_lo;
1133 value &= APIC_ICRLO_RESV_MASK;
1134 value |= icrlo;
1135 lapic->icr_lo = value;
1136 intr_restore(eflags);
1137 }
1138
1139 #define BEFORE_SPIN 1000000
1140 #ifdef DETECT_DEADLOCK
1141 #define AFTER_SPIN 1000
1142 #endif
1143
1144 void
1145 lapic_ipi_vectored(u_int vector, int dest)
1146 {
1147 register_t icrlo, destfield;
1148
1149 KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
1150 ("%s: invalid vector %d", __func__, vector));
1151
1152 icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY |
1153 APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE;
1154 destfield = 0;
1155 switch (dest) {
1156 case APIC_IPI_DEST_SELF:
1157 icrlo |= APIC_DEST_SELF;
1158 break;
1159 case APIC_IPI_DEST_ALL:
1160 icrlo |= APIC_DEST_ALLISELF;
1161 break;
1162 case APIC_IPI_DEST_OTHERS:
1163 icrlo |= APIC_DEST_ALLESELF;
1164 break;
1165 default:
1166 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1167 ("%s: invalid destination 0x%x", __func__, dest));
1168 destfield = dest;
1169 }
1170
1171 /* Wait for an earlier IPI to finish. */
1172 if (!lapic_ipi_wait(BEFORE_SPIN)) {
1173 if (panicstr != NULL)
1174 return;
1175 else
1176 panic("APIC: Previous IPI is stuck");
1177 }
1178
1179 lapic_ipi_raw(icrlo, destfield);
1180
1181 #ifdef DETECT_DEADLOCK
1182 /* Wait for IPI to be delivered. */
1183 if (!lapic_ipi_wait(AFTER_SPIN)) {
1184 #ifdef needsattention
1185 /*
1186 * XXX FIXME:
1187 *
1188 * The above function waits for the message to actually be
1189 * delivered. It breaks out after an arbitrary timeout
1190 * since the message should eventually be delivered (at
1191 * least in theory) and that if it wasn't we would catch
1192 * the failure with the check above when the next IPI is
1193 * sent.
1194 *
1195 * We could skip this wait entirely, EXCEPT it probably
1196 * protects us from other routines that assume that the
1197 * message was delivered and acted upon when this function
1198 * returns.
1199 */
1200 printf("APIC: IPI might be stuck\n");
1201 #else /* !needsattention */
1202 /* Wait until mesage is sent without a timeout. */
1203 while (lapic->icr_lo & APIC_DELSTAT_PEND)
1204 ia32_pause();
1205 #endif /* needsattention */
1206 }
1207 #endif /* DETECT_DEADLOCK */
1208 }
1209 #endif /* SMP */
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