The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/local_apic.c

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    1 /*-
    2  * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
    3  * Copyright (c) 1996, by Steve Passe
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. The name of the developer may NOT be used to endorse or promote products
   12  *    derived from this software without specific prior written permission.
   13  * 3. Neither the name of the author nor the names of any co-contributors
   14  *    may be used to endorse or promote products derived from this software
   15  *    without specific prior written permission.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  */
   29 
   30 /*
   31  * Local APIC support on Pentium and later processors.
   32  */
   33 
   34 #include <sys/cdefs.h>
   35 __FBSDID("$FreeBSD: releng/6.4/sys/amd64/amd64/local_apic.c 184456 2008-10-29 21:31:01Z sobomax $");
   36 
   37 #include "opt_hwpmc_hooks.h"
   38 
   39 #include "opt_ddb.h"
   40 
   41 #include <sys/param.h>
   42 #include <sys/systm.h>
   43 #include <sys/bus.h>
   44 #include <sys/kernel.h>
   45 #include <sys/lock.h>
   46 #include <sys/mutex.h>
   47 #include <sys/pcpu.h>
   48 #include <sys/smp.h>
   49 #include <sys/proc.h>
   50 
   51 #include <vm/vm.h>
   52 #include <vm/pmap.h>
   53 
   54 #include <machine/apicreg.h>
   55 #include <machine/cputypes.h>
   56 #include <machine/frame.h>
   57 #include <machine/intr_machdep.h>
   58 #include <machine/apicvar.h>
   59 #include <machine/md_var.h>
   60 #include <machine/smp.h>
   61 #include <machine/specialreg.h>
   62 
   63 #ifdef DDB
   64 #include <sys/interrupt.h>
   65 #include <ddb/ddb.h>
   66 #endif
   67 
   68 /* Sanity checks on IDT vectors. */
   69 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
   70 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
   71 CTASSERT(APIC_LOCAL_INTS == 240);
   72 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
   73 
   74 /* Magic IRQ values for the timer and syscalls. */
   75 #define IRQ_TIMER       (NUM_IO_INTS + 1)
   76 #define IRQ_SYSCALL     (NUM_IO_INTS + 2)
   77 
   78 /*
   79  * Support for local APICs.  Local APICs manage interrupts on each
   80  * individual processor as opposed to I/O APICs which receive interrupts
   81  * from I/O devices and then forward them on to the local APICs.
   82  *
   83  * Local APICs can also send interrupts to each other thus providing the
   84  * mechanism for IPIs.
   85  */
   86 
   87 struct lvt {
   88         u_int lvt_edgetrigger:1;
   89         u_int lvt_activehi:1;
   90         u_int lvt_masked:1;
   91         u_int lvt_active:1;
   92         u_int lvt_mode:16;
   93         u_int lvt_vector:8;
   94 };
   95 
   96 struct lapic {
   97         struct lvt la_lvts[LVT_MAX + 1];
   98         u_int la_id:8;
   99         u_int la_cluster:4;
  100         u_int la_cluster_id:2;
  101         u_int la_present:1;
  102         u_long *la_timer_count;
  103         u_long la_hard_ticks;
  104         u_long la_stat_ticks;
  105         u_long la_prof_ticks;
  106 } static lapics[MAX_APIC_ID + 1];
  107 
  108 /* XXX: should thermal be an NMI? */
  109 
  110 /* Global defaults for local APIC LVT entries. */
  111 static struct lvt lvts[LVT_MAX + 1] = {
  112         { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 },  /* LINT0: masked ExtINT */
  113         { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 },     /* LINT1: NMI */
  114         { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT },      /* Timer */
  115         { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT },      /* Error */
  116         { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 },     /* PMC */
  117         { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT },    /* Thermal */
  118 };
  119 
  120 static inthand_t *ioint_handlers[] = {
  121         NULL,                   /* 0 - 31 */
  122         IDTVEC(apic_isr1),      /* 32 - 63 */
  123         IDTVEC(apic_isr2),      /* 64 - 95 */
  124         IDTVEC(apic_isr3),      /* 96 - 127 */
  125         IDTVEC(apic_isr4),      /* 128 - 159 */
  126         IDTVEC(apic_isr5),      /* 160 - 191 */
  127         IDTVEC(apic_isr6),      /* 192 - 223 */
  128         IDTVEC(apic_isr7),      /* 224 - 255 */
  129 };
  130 
  131 /* Include IDT_SYSCALL to make indexing easier. */
  132 static u_int ioint_irqs[APIC_NUM_IOINTS + 1];
  133 
  134 static u_int32_t lapic_timer_divisors[] = { 
  135         APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
  136         APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
  137 };
  138 
  139 volatile lapic_t *lapic;
  140 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz;
  141 
  142 static void     lapic_enable(void);
  143 static void     lapic_resume(struct pic *pic);
  144 static void     lapic_timer_enable_intr(void);
  145 static void     lapic_timer_oneshot(u_int count);
  146 static void     lapic_timer_periodic(u_int count);
  147 static void     lapic_timer_set_divisor(u_int divisor);
  148 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
  149 
  150 struct pic lapic_pic = { .pic_resume = lapic_resume };
  151 
  152 static uint32_t
  153 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
  154 {
  155         struct lvt *lvt;
  156 
  157         KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin));
  158         if (la->la_lvts[pin].lvt_active)
  159                 lvt = &la->la_lvts[pin];
  160         else
  161                 lvt = &lvts[pin];
  162 
  163         value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
  164             APIC_LVT_VECTOR);
  165         if (lvt->lvt_edgetrigger == 0)
  166                 value |= APIC_LVT_TM;
  167         if (lvt->lvt_activehi == 0)
  168                 value |= APIC_LVT_IIPP_INTALO;
  169         if (lvt->lvt_masked)
  170                 value |= APIC_LVT_M;
  171         value |= lvt->lvt_mode;
  172         switch (lvt->lvt_mode) {
  173         case APIC_LVT_DM_NMI:
  174         case APIC_LVT_DM_SMI:
  175         case APIC_LVT_DM_INIT:
  176         case APIC_LVT_DM_EXTINT:
  177                 if (!lvt->lvt_edgetrigger) {
  178                         printf("lapic%u: Forcing LINT%u to edge trigger\n",
  179                             la->la_id, pin);
  180                         value |= APIC_LVT_TM;
  181                 }
  182                 /* Use a vector of 0. */
  183                 break;
  184         case APIC_LVT_DM_FIXED:
  185                 value |= lvt->lvt_vector;
  186                 break;
  187         default:
  188                 panic("bad APIC LVT delivery mode: %#x\n", value);
  189         }
  190         return (value);
  191 }
  192 
  193 /*
  194  * Map the local APIC and setup necessary interrupt vectors.
  195  */
  196 void
  197 lapic_init(uintptr_t addr)
  198 {
  199 
  200         /* Map the local APIC and setup the spurious interrupt handler. */
  201         KASSERT(trunc_page(addr) == addr,
  202             ("local APIC not aligned on a page boundary"));
  203         lapic = (lapic_t *)pmap_mapdev(addr, sizeof(lapic_t));
  204         setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0);
  205 
  206         /* Perform basic initialization of the BSP's local APIC. */
  207         lapic_enable();
  208         ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
  209 
  210         /* Set BSP's per-CPU local APIC ID. */
  211         PCPU_SET(apic_id, lapic_id());
  212         intr_add_cpu(PCPU_GET(apic_id));
  213 
  214         /* Local APIC timer interrupt. */
  215         setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYSIGT, SEL_KPL, 0);
  216         ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER;
  217 
  218         /* XXX: error/thermal interrupts */
  219 }
  220 
  221 /*
  222  * Create a local APIC instance.
  223  */
  224 void
  225 lapic_create(u_int apic_id, int boot_cpu)
  226 {
  227         int i;
  228 
  229         if (apic_id > MAX_APIC_ID) {
  230                 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
  231                 if (boot_cpu)
  232                         panic("Can't ignore BSP");
  233                 return;
  234         }
  235         KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
  236             apic_id));
  237 
  238         /*
  239          * Assume no local LVT overrides and a cluster of 0 and
  240          * intra-cluster ID of 0.
  241          */
  242         lapics[apic_id].la_present = 1;
  243         lapics[apic_id].la_id = apic_id;
  244         for (i = 0; i < LVT_MAX; i++) {
  245                 lapics[apic_id].la_lvts[i] = lvts[i];
  246                 lapics[apic_id].la_lvts[i].lvt_active = 0;
  247         }
  248 
  249 #ifdef SMP
  250         cpu_add(apic_id, boot_cpu);
  251 #endif
  252 }
  253 
  254 /*
  255  * Dump contents of local APIC registers
  256  */
  257 void
  258 lapic_dump(const char* str)
  259 {
  260 
  261         printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
  262         printf("     ID: 0x%08x   VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n",
  263             lapic->id, lapic->version, lapic->ldr, lapic->dfr);
  264         printf("  lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
  265             lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
  266         printf("  timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n",
  267             lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error,
  268             lapic->lvt_pcint);
  269 }
  270 
  271 void
  272 lapic_setup(int boot)
  273 {
  274         struct lapic *la;
  275         u_int32_t maxlvt;
  276         register_t eflags;
  277         char buf[MAXCOMLEN + 1];
  278 
  279         la = &lapics[lapic_id()];
  280         KASSERT(la->la_present, ("missing APIC structure"));
  281         eflags = intr_disable();
  282         maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
  283 
  284         /* Initialize the TPR to allow all interrupts. */
  285         lapic_set_tpr(0);
  286 
  287         /* Setup spurious vector and enable the local APIC. */
  288         lapic_enable();
  289 
  290         /* Program LINT[01] LVT entries. */
  291         lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
  292         lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
  293 #ifdef  HWPMC_HOOKS
  294         /* Program the PMC LVT entry if present. */
  295         if (maxlvt >= LVT_PMC)
  296                 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
  297 #endif
  298 
  299         /* Program timer LVT and setup handler. */
  300         lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer);
  301         if (boot) {
  302                 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid));
  303                 intrcnt_add(buf, &la->la_timer_count);
  304         }
  305 
  306         /* We don't setup the timer during boot on the BSP until later. */
  307         if (!(boot && PCPU_GET(cpuid) == 0)) {
  308                 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor",
  309                     lapic_id()));
  310                 lapic_timer_set_divisor(lapic_timer_divisor);
  311                 lapic_timer_periodic(lapic_timer_period);
  312                 lapic_timer_enable_intr();
  313         }
  314 
  315         /* XXX: Error and thermal LVTs */
  316 
  317         if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
  318                 /*
  319                  * Detect the presence of C1E capability mostly on latest
  320                  * dual-cores (or future) k8 family.  This feature renders
  321                  * the local APIC timer dead, so we disable it by reading
  322                  * the Interrupt Pending Message register and clearing both
  323                  * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
  324                  * 
  325                  * Reference:
  326                  *   "BIOS and Kernel Developer's Guide for AMD NPT
  327                  *    Family 0Fh Processors"
  328                  *   #32559 revision 3.00
  329                  */
  330                 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
  331                     (cpu_id & 0x0fff0000) >=  0x00040000) {
  332                         uint64_t msr;
  333 
  334                         msr = rdmsr(0xc0010055);
  335                         if (msr & 0x18000000)
  336                                 wrmsr(0xc0010055, msr & ~0x18000000ULL);
  337                 }
  338         }
  339 
  340         intr_restore(eflags);
  341 }
  342 
  343 /*
  344  * Called by cpu_initclocks() on the BSP to setup the local APIC timer so
  345  * that it can drive hardclock, statclock, and profclock.  This function
  346  * returns true if it is able to use the local APIC timer to drive the
  347  * clocks and false if it is not able.
  348  */
  349 int
  350 lapic_setup_clock(void)
  351 {
  352         u_long value;
  353 
  354         /* Can't drive the timer without a local APIC. */
  355         if (lapic == NULL)
  356                 return (0);
  357 
  358         /* Start off with a divisor of 2 (power on reset default). */
  359         lapic_timer_divisor = 2;
  360 
  361         /* Try to calibrate the local APIC timer. */
  362         do {
  363                 lapic_timer_set_divisor(lapic_timer_divisor);
  364                 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
  365                 DELAY(2000000);
  366                 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
  367                 if (value != APIC_TIMER_MAX_COUNT)
  368                         break;
  369                 lapic_timer_divisor <<= 1;
  370         } while (lapic_timer_divisor <= 128);
  371         if (lapic_timer_divisor > 128)
  372                 panic("lapic: Divisor too big");
  373         value /= 2;
  374         if (bootverbose)
  375                 printf("lapic: Divisor %lu, Frequency %lu hz\n",
  376                     lapic_timer_divisor, value);
  377 
  378         /*
  379          * We want to run stathz in the neighborhood of 128hz.  We would
  380          * like profhz to run as often as possible, so we let it run on
  381          * each clock tick.  We try to honor the requested 'hz' value as
  382          * much as possible.
  383          *
  384          * If 'hz' is above 1500, then we just let the lapic timer
  385          * (and profhz) run at hz.  If 'hz' is below 1500 but above
  386          * 750, then we let the lapic timer run at 2 * 'hz'.  If 'hz'
  387          * is below 750 then we let the lapic timer run at 4 * 'hz'.
  388          */
  389         if (hz >= 1500)
  390                 lapic_timer_hz = hz;
  391         else if (hz >= 750)
  392                 lapic_timer_hz = hz * 2;
  393         else
  394                 lapic_timer_hz = hz * 4;
  395         if (lapic_timer_hz < 128)
  396                 stathz = lapic_timer_hz;
  397         else
  398                 stathz = lapic_timer_hz / (lapic_timer_hz / 128);
  399         profhz = lapic_timer_hz;
  400         lapic_timer_period = value / lapic_timer_hz;
  401 
  402         /*
  403          * Start up the timer on the BSP.  The APs will kick off their
  404          * timer during lapic_setup().
  405          */
  406         lapic_timer_periodic(lapic_timer_period);
  407         lapic_timer_enable_intr();
  408         return (1);
  409 }
  410 
  411 void
  412 lapic_disable(void)
  413 {
  414         uint32_t value;
  415 
  416         /* Software disable the local APIC. */
  417         value = lapic->svr;
  418         value &= ~APIC_SVR_SWEN;
  419         lapic->svr = value;
  420 }
  421 
  422 static void
  423 lapic_enable(void)
  424 {
  425         u_int32_t value;
  426 
  427         /* Program the spurious vector to enable the local APIC. */
  428         value = lapic->svr;
  429         value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
  430         value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
  431         lapic->svr = value;
  432 }
  433 
  434 /* Reset the local APIC on the BSP during resume. */
  435 static void
  436 lapic_resume(struct pic *pic)
  437 {
  438 
  439         lapic_setup(0);
  440 }
  441 
  442 int
  443 lapic_id(void)
  444 {
  445 
  446         KASSERT(lapic != NULL, ("local APIC is not mapped"));
  447         return (lapic->id >> APIC_ID_SHIFT);
  448 }
  449 
  450 int
  451 lapic_intr_pending(u_int vector)
  452 {
  453         volatile u_int32_t *irr;
  454 
  455         /*
  456          * The IRR registers are an array of 128-bit registers each of
  457          * which only describes 32 interrupts in the low 32 bits..  Thus,
  458          * we divide the vector by 32 to get the 128-bit index.  We then
  459          * multiply that index by 4 to get the equivalent index from
  460          * treating the IRR as an array of 32-bit registers.  Finally, we
  461          * modulus the vector by 32 to determine the individual bit to
  462          * test.
  463          */
  464         irr = &lapic->irr0;
  465         return (irr[(vector / 32) * 4] & 1 << (vector % 32));
  466 }
  467 
  468 void
  469 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
  470 {
  471         struct lapic *la;
  472 
  473         KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
  474             __func__, apic_id));
  475         KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
  476             __func__, cluster));
  477         KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
  478             ("%s: intra cluster id %u too big", __func__, cluster_id));
  479         la = &lapics[apic_id];
  480         la->la_cluster = cluster;
  481         la->la_cluster_id = cluster_id;
  482 }
  483 
  484 int
  485 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
  486 {
  487 
  488         if (pin > LVT_MAX)
  489                 return (EINVAL);
  490         if (apic_id == APIC_ID_ALL) {
  491                 lvts[pin].lvt_masked = masked;
  492                 if (bootverbose)
  493                         printf("lapic:");
  494         } else {
  495                 KASSERT(lapics[apic_id].la_present,
  496                     ("%s: missing APIC %u", __func__, apic_id));
  497                 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
  498                 lapics[apic_id].la_lvts[pin].lvt_active = 1;
  499                 if (bootverbose)
  500                         printf("lapic%u:", apic_id);
  501         }
  502         if (bootverbose)
  503                 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
  504         return (0);
  505 }
  506 
  507 int
  508 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
  509 {
  510         struct lvt *lvt;
  511 
  512         if (pin > LVT_MAX)
  513                 return (EINVAL);
  514         if (apic_id == APIC_ID_ALL) {
  515                 lvt = &lvts[pin];
  516                 if (bootverbose)
  517                         printf("lapic:");
  518         } else {
  519                 KASSERT(lapics[apic_id].la_present,
  520                     ("%s: missing APIC %u", __func__, apic_id));
  521                 lvt = &lapics[apic_id].la_lvts[pin];
  522                 lvt->lvt_active = 1;
  523                 if (bootverbose)
  524                         printf("lapic%u:", apic_id);
  525         }
  526         lvt->lvt_mode = mode;
  527         switch (mode) {
  528         case APIC_LVT_DM_NMI:
  529         case APIC_LVT_DM_SMI:
  530         case APIC_LVT_DM_INIT:
  531         case APIC_LVT_DM_EXTINT:
  532                 lvt->lvt_edgetrigger = 1;
  533                 lvt->lvt_activehi = 1;
  534                 if (mode == APIC_LVT_DM_EXTINT)
  535                         lvt->lvt_masked = 1;
  536                 else
  537                         lvt->lvt_masked = 0;
  538                 break;
  539         default:
  540                 panic("Unsupported delivery mode: 0x%x\n", mode);
  541         }
  542         if (bootverbose) {
  543                 printf(" Routing ");
  544                 switch (mode) {
  545                 case APIC_LVT_DM_NMI:
  546                         printf("NMI");
  547                         break;
  548                 case APIC_LVT_DM_SMI:
  549                         printf("SMI");
  550                         break;
  551                 case APIC_LVT_DM_INIT:
  552                         printf("INIT");
  553                         break;
  554                 case APIC_LVT_DM_EXTINT:
  555                         printf("ExtINT");
  556                         break;
  557                 }
  558                 printf(" -> LINT%u\n", pin);
  559         }
  560         return (0);
  561 }
  562 
  563 int
  564 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
  565 {
  566 
  567         if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM)
  568                 return (EINVAL);
  569         if (apic_id == APIC_ID_ALL) {
  570                 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
  571                 if (bootverbose)
  572                         printf("lapic:");
  573         } else {
  574                 KASSERT(lapics[apic_id].la_present,
  575                     ("%s: missing APIC %u", __func__, apic_id));
  576                 lapics[apic_id].la_lvts[pin].lvt_active = 1;
  577                 lapics[apic_id].la_lvts[pin].lvt_activehi =
  578                     (pol == INTR_POLARITY_HIGH);
  579                 if (bootverbose)
  580                         printf("lapic%u:", apic_id);
  581         }
  582         if (bootverbose)
  583                 printf(" LINT%u polarity: %s\n", pin,
  584                     pol == INTR_POLARITY_HIGH ? "high" : "low");
  585         return (0);
  586 }
  587 
  588 int
  589 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger)
  590 {
  591 
  592         if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
  593                 return (EINVAL);
  594         if (apic_id == APIC_ID_ALL) {
  595                 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
  596                 if (bootverbose)
  597                         printf("lapic:");
  598         } else {
  599                 KASSERT(lapics[apic_id].la_present,
  600                     ("%s: missing APIC %u", __func__, apic_id));
  601                 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
  602                     (trigger == INTR_TRIGGER_EDGE);
  603                 lapics[apic_id].la_lvts[pin].lvt_active = 1;
  604                 if (bootverbose)
  605                         printf("lapic%u:", apic_id);
  606         }
  607         if (bootverbose)
  608                 printf(" LINT%u trigger: %s\n", pin,
  609                     trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
  610         return (0);
  611 }
  612 
  613 /*
  614  * Adjust the TPR of the current CPU so that it blocks all interrupts below
  615  * the passed in vector.
  616  */
  617 void
  618 lapic_set_tpr(u_int vector)
  619 {
  620 #ifdef CHEAP_TPR
  621         lapic->tpr = vector;
  622 #else
  623         u_int32_t tpr;
  624 
  625         tpr = lapic->tpr & ~APIC_TPR_PRIO;
  626         tpr |= vector;
  627         lapic->tpr = tpr;
  628 #endif
  629 }
  630 
  631 void
  632 lapic_eoi(void)
  633 {
  634 
  635         lapic->eoi = 0;
  636 }
  637 
  638 void
  639 lapic_handle_intr(void *cookie, struct intrframe frame)
  640 {
  641         struct intsrc *isrc;
  642         int vec = (uintptr_t)cookie;
  643 
  644         if (vec == -1)
  645                 panic("Couldn't get vector from ISR!");
  646         isrc = intr_lookup_source(apic_idt_to_irq(vec));
  647         intr_execute_handlers(isrc, &frame);
  648 }
  649 
  650 void
  651 lapic_handle_timer(struct clockframe frame)
  652 {
  653         struct lapic *la;
  654 
  655 #if defined(SMP) && !defined(SCHED_ULE)
  656         /*
  657          * Don't do any accounting for the disabled HTT cores, since it
  658          * will provide misleading numbers for the userland.
  659          *
  660          * No locking is necessary here, since even if we loose the race
  661          * when hlt_cpus_mask changes it is not a big deal, really.
  662          *
  663          * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask
  664          * and unlike other schedulers it actually schedules threads to
  665          * those CPUs.
  666          */
  667         if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0)
  668                 return;
  669 #endif
  670 
  671         la = &lapics[PCPU_GET(apic_id)];
  672         (*la->la_timer_count)++;
  673         critical_enter();
  674 
  675         /* Fire hardclock at hz. */
  676         la->la_hard_ticks += hz;
  677         if (la->la_hard_ticks >= lapic_timer_hz) {
  678                 la->la_hard_ticks -= lapic_timer_hz;
  679                 if (PCPU_GET(cpuid) == 0)
  680                         hardclock(&frame);
  681                 else
  682                         hardclock_process(&frame);
  683         }
  684 
  685         /* Fire statclock at stathz. */
  686         la->la_stat_ticks += stathz;
  687         if (la->la_stat_ticks >= lapic_timer_hz) {
  688                 la->la_stat_ticks -= lapic_timer_hz;
  689                 statclock(&frame);
  690         }
  691 
  692         /* Fire profclock at profhz, but only when needed. */
  693         la->la_prof_ticks += profhz;
  694         if (la->la_prof_ticks >= lapic_timer_hz) {
  695                 la->la_prof_ticks -= lapic_timer_hz;
  696                 if (profprocs != 0)
  697                         profclock(&frame);
  698         }
  699         critical_exit();
  700 }
  701 
  702 static void
  703 lapic_timer_set_divisor(u_int divisor)
  704 {
  705 
  706         KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor));
  707         KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) /
  708             sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor));
  709         lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1];
  710 }
  711 
  712 static void
  713 lapic_timer_oneshot(u_int count)
  714 {
  715         u_int32_t value;
  716 
  717         value = lapic->lvt_timer;
  718         value &= ~APIC_LVTT_TM;
  719         value |= APIC_LVTT_TM_ONE_SHOT;
  720         lapic->lvt_timer = value;
  721         lapic->icr_timer = count;
  722 }
  723 
  724 static void
  725 lapic_timer_periodic(u_int count)
  726 {
  727         u_int32_t value;
  728 
  729         value = lapic->lvt_timer;
  730         value &= ~APIC_LVTT_TM;
  731         value |= APIC_LVTT_TM_PERIODIC;
  732         lapic->lvt_timer = value;
  733         lapic->icr_timer = count;
  734 }
  735 
  736 static void
  737 lapic_timer_enable_intr(void)
  738 {
  739         u_int32_t value;
  740 
  741         value = lapic->lvt_timer;
  742         value &= ~APIC_LVT_M;
  743         lapic->lvt_timer = value;
  744 }
  745 
  746 /* Request a free IDT vector to be used by the specified IRQ. */
  747 u_int
  748 apic_alloc_vector(u_int irq)
  749 {
  750         u_int vector;
  751 
  752         KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
  753 
  754         /*
  755          * Search for a free vector.  Currently we just use a very simple
  756          * algorithm to find the first free vector.
  757          */
  758         mtx_lock_spin(&icu_lock);
  759         for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
  760                 if (ioint_irqs[vector] != 0)
  761                         continue;
  762                 ioint_irqs[vector] = irq;
  763                 mtx_unlock_spin(&icu_lock);
  764                 return (vector + APIC_IO_INTS);
  765         }
  766         mtx_unlock_spin(&icu_lock);
  767         panic("Couldn't find an APIC vector for IRQ %u", irq);
  768 }
  769 
  770 /*
  771  * Request 'count' free contiguous IDT vectors to be used by 'count'
  772  * IRQs.  'count' must be a power of two and the vectors will be
  773  * aligned on a boundary of 'align'.  If the request cannot be
  774  * satisfied, 0 is returned.
  775  */
  776 u_int
  777 apic_alloc_vectors(u_int *irqs, u_int count, u_int align)
  778 {
  779         u_int first, run, vector;
  780 
  781         KASSERT(powerof2(count), ("bad count"));
  782         KASSERT(powerof2(align), ("bad align"));
  783         KASSERT(align >= count, ("align < count"));
  784 #ifdef INVARIANTS
  785         for (run = 0; run < count; run++)
  786                 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u",
  787                     irqs[run], run));
  788 #endif
  789 
  790         /*
  791          * Search for 'count' free vectors.  As with apic_alloc_vector(),
  792          * this just uses a simple first fit algorithm.
  793          */
  794         run = 0;
  795         first = 0;
  796         mtx_lock_spin(&icu_lock);
  797         for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
  798 
  799                 /* Vector is in use, end run. */
  800                 if (ioint_irqs[vector] != 0) {
  801                         run = 0;
  802                         first = 0;
  803                         continue;
  804                 }
  805 
  806                 /* Start a new run if run == 0 and vector is aligned. */
  807                 if (run == 0) {
  808                         if ((vector & (align - 1)) != 0)
  809                                 continue;
  810                         first = vector;
  811                 }
  812                 run++;
  813 
  814                 /* Keep looping if the run isn't long enough yet. */
  815                 if (run < count)
  816                         continue;
  817 
  818                 /* Found a run, assign IRQs and return the first vector. */
  819                 for (vector = 0; vector < count; vector++)
  820                         ioint_irqs[first + vector] = irqs[vector];
  821                 mtx_unlock_spin(&icu_lock);
  822                 return (first + APIC_IO_INTS);
  823         }
  824         mtx_unlock_spin(&icu_lock);
  825         printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count);
  826         return (0);
  827 }
  828 
  829 void
  830 apic_enable_vector(u_int vector)
  831 {
  832 
  833         KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
  834         KASSERT(ioint_handlers[vector / 32] != NULL,
  835             ("No ISR handler for vector %u", vector));
  836         setidt(vector, ioint_handlers[vector / 32], SDT_SYSIGT, SEL_KPL, 0);
  837 }
  838 
  839 /* Release an APIC vector when it's no longer in use. */
  840 void
  841 apic_free_vector(u_int vector, u_int irq)
  842 {
  843         KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
  844             vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
  845             ("Vector %u does not map to an IRQ line", vector));
  846         KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
  847         KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch"));
  848         mtx_lock_spin(&icu_lock);
  849         ioint_irqs[vector - APIC_IO_INTS] = 0;
  850         mtx_unlock_spin(&icu_lock);
  851 }
  852 
  853 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */
  854 u_int
  855 apic_idt_to_irq(u_int vector)
  856 {
  857 
  858         KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
  859             vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
  860             ("Vector %u does not map to an IRQ line", vector));
  861         return (ioint_irqs[vector - APIC_IO_INTS]);
  862 }
  863 
  864 #ifdef DDB
  865 /*
  866  * Dump data about APIC IDT vector mappings.
  867  */
  868 DB_SHOW_COMMAND(apic, db_show_apic)
  869 {
  870         struct intsrc *isrc;
  871         int quit, i, verbose;
  872         u_int irq;
  873 
  874         quit = 0;
  875         if (strcmp(modif, "vv") == 0)
  876                 verbose = 2;
  877         else if (strcmp(modif, "v") == 0)
  878                 verbose = 1;
  879         else
  880                 verbose = 0;
  881         db_setup_paging(db_simple_pager, &quit, db_lines_per_page);
  882         for (i = 0; i < APIC_NUM_IOINTS + 1 && !quit; i++) {
  883                 irq = ioint_irqs[i];
  884                 if (irq != 0 && irq != IRQ_SYSCALL) {
  885                         db_printf("vec 0x%2x -> ", i + APIC_IO_INTS);
  886                         if (irq == IRQ_TIMER)
  887                                 db_printf("lapic timer\n");
  888                         else if (irq < NUM_IO_INTS) {
  889                                 isrc = intr_lookup_source(irq);
  890                                 if (isrc == NULL || verbose == 0)
  891                                         db_printf("IRQ %u\n", irq);
  892                                 else
  893                                         db_dump_intr_event(isrc->is_event,
  894                                             verbose == 2);
  895                         } else
  896                                 db_printf("IRQ %u ???\n", irq);
  897                 }
  898         }
  899 }
  900 
  901 static void
  902 dump_mask(const char *prefix, uint32_t v, int base)
  903 {
  904         int i, first;
  905 
  906         first = 1;
  907         for (i = 0; i < 32; i++)
  908                 if (v & (1 << i)) {
  909                         if (first) {
  910                                 db_printf("%s:", prefix);
  911                                 first = 0;
  912                         }
  913                         db_printf(" %02x", base + i);
  914                 }
  915         if (!first)
  916                 db_printf("\n");
  917 }
  918 
  919 /* Show info from the lapic regs for this CPU. */
  920 DB_SHOW_COMMAND(lapic, db_show_lapic)
  921 {
  922         uint32_t v;
  923 
  924         db_printf("lapic ID = %d\n", lapic_id());
  925         v = lapic->version;
  926         db_printf("version  = %d.%d\n", (v & APIC_VER_VERSION) >> 4,
  927             v & 0xf);
  928         db_printf("max LVT  = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT);
  929         v = lapic->svr;
  930         db_printf("SVR      = %02x (%s)\n", v & APIC_SVR_VECTOR,
  931             v & APIC_SVR_ENABLE ? "enabled" : "disabled");
  932         db_printf("TPR      = %02x\n", lapic->tpr);
  933 
  934 #define dump_field(prefix, index)                                       \
  935         dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index,   \
  936             index * 32)
  937 
  938         db_printf("In-service Interrupts:\n");
  939         dump_field(isr, 0);
  940         dump_field(isr, 1);
  941         dump_field(isr, 2);
  942         dump_field(isr, 3);
  943         dump_field(isr, 4);
  944         dump_field(isr, 5);
  945         dump_field(isr, 6);
  946         dump_field(isr, 7);
  947 
  948         db_printf("TMR Interrupts:\n");
  949         dump_field(tmr, 0);
  950         dump_field(tmr, 1);
  951         dump_field(tmr, 2);
  952         dump_field(tmr, 3);
  953         dump_field(tmr, 4);
  954         dump_field(tmr, 5);
  955         dump_field(tmr, 6);
  956         dump_field(tmr, 7);
  957 
  958         db_printf("IRR Interrupts:\n");
  959         dump_field(irr, 0);
  960         dump_field(irr, 1);
  961         dump_field(irr, 2);
  962         dump_field(irr, 3);
  963         dump_field(irr, 4);
  964         dump_field(irr, 5);
  965         dump_field(irr, 6);
  966         dump_field(irr, 7);
  967 
  968 #undef dump_field
  969 }
  970 #endif
  971 
  972 /*
  973  * APIC probing support code.  This includes code to manage enumerators.
  974  */
  975 
  976 static SLIST_HEAD(, apic_enumerator) enumerators =
  977         SLIST_HEAD_INITIALIZER(enumerators);
  978 static struct apic_enumerator *best_enum;
  979         
  980 void
  981 apic_register_enumerator(struct apic_enumerator *enumerator)
  982 {
  983 #ifdef INVARIANTS
  984         struct apic_enumerator *apic_enum;
  985 
  986         SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
  987                 if (apic_enum == enumerator)
  988                         panic("%s: Duplicate register of %s", __func__,
  989                             enumerator->apic_name);
  990         }
  991 #endif
  992         SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
  993 }
  994 
  995 /*
  996  * We have to look for CPU's very, very early because certain subsystems
  997  * want to know how many CPU's we have extremely early on in the boot
  998  * process.
  999  */
 1000 static void
 1001 apic_init(void *dummy __unused)
 1002 {
 1003         struct apic_enumerator *enumerator;
 1004         int retval, best;
 1005 
 1006         /* Don't probe if APIC mode is disabled. */
 1007         if (resource_disabled("apic", 0))
 1008                 return;
 1009 
 1010         /* First, probe all the enumerators to find the best match. */
 1011         best_enum = NULL;
 1012         best = 0;
 1013         SLIST_FOREACH(enumerator, &enumerators, apic_next) {
 1014                 retval = enumerator->apic_probe();
 1015                 if (retval > 0)
 1016                         continue;
 1017                 if (best_enum == NULL || best < retval) {
 1018                         best_enum = enumerator;
 1019                         best = retval;
 1020                 }
 1021         }
 1022         if (best_enum == NULL) {
 1023                 if (bootverbose)
 1024                         printf("APIC: Could not find any APICs.\n");
 1025                 return;
 1026         }
 1027 
 1028         if (bootverbose)
 1029                 printf("APIC: Using the %s enumerator.\n",
 1030                     best_enum->apic_name);
 1031 
 1032         /* Second, probe the CPU's in the system. */
 1033         retval = best_enum->apic_probe_cpus();
 1034         if (retval != 0)
 1035                 printf("%s: Failed to probe CPUs: returned %d\n",
 1036                     best_enum->apic_name, retval);
 1037 }
 1038 SYSINIT(apic_init, SI_SUB_TUNABLES - 1, SI_ORDER_SECOND, apic_init, NULL)
 1039 
 1040 /*
 1041  * Setup the local APIC.  We have to do this prior to starting up the APs
 1042  * in the SMP case.
 1043  */
 1044 static void
 1045 apic_setup_local(void *dummy __unused)
 1046 {
 1047         int retval;
 1048 
 1049         if (best_enum == NULL)
 1050                 return;
 1051         retval = best_enum->apic_setup_local();
 1052         if (retval != 0)
 1053                 printf("%s: Failed to setup the local APIC: returned %d\n",
 1054                     best_enum->apic_name, retval);
 1055 #ifdef SMP
 1056         /* Last, setup the cpu topology now that we have probed CPUs */
 1057         mp_topology();
 1058 #endif
 1059 }
 1060 SYSINIT(apic_setup_local, SI_SUB_CPU, SI_ORDER_FIRST, apic_setup_local, NULL)
 1061 
 1062 /*
 1063  * Setup the I/O APICs.
 1064  */
 1065 static void
 1066 apic_setup_io(void *dummy __unused)
 1067 {
 1068         int retval;
 1069 
 1070         if (best_enum == NULL)
 1071                 return;
 1072         retval = best_enum->apic_setup_io();
 1073         if (retval != 0)
 1074                 printf("%s: Failed to setup I/O APICs: returned %d\n",
 1075                     best_enum->apic_name, retval);
 1076 
 1077         /*
 1078          * Finish setting up the local APIC on the BSP once we know how to
 1079          * properly program the LINT pins.
 1080          */
 1081         lapic_setup(1);
 1082         intr_register_pic(&lapic_pic);
 1083         if (bootverbose)
 1084                 lapic_dump("BSP");
 1085 
 1086         /* Enable the MSI "pic". */
 1087         msi_init();
 1088 }
 1089 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL)
 1090 
 1091 #ifdef SMP
 1092 /*
 1093  * Inter Processor Interrupt functions.  The lapic_ipi_*() functions are
 1094  * private to the sys/amd64 code.  The public interface for the rest of the
 1095  * kernel is defined in mp_machdep.c.
 1096  */
 1097 int
 1098 lapic_ipi_wait(int delay)
 1099 {
 1100         int x, incr;
 1101 
 1102         /*
 1103          * Wait delay loops for IPI to be sent.  This is highly bogus
 1104          * since this is sensitive to CPU clock speed.  If delay is
 1105          * -1, we wait forever.
 1106          */
 1107         if (delay == -1) {
 1108                 incr = 0;
 1109                 delay = 1;
 1110         } else
 1111                 incr = 1;
 1112         for (x = 0; x < delay; x += incr) {
 1113                 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE)
 1114                         return (1);
 1115                 ia32_pause();
 1116         }
 1117         return (0);
 1118 }
 1119 
 1120 void
 1121 lapic_ipi_raw(register_t icrlo, u_int dest)
 1122 {
 1123         register_t value, eflags;
 1124 
 1125         /* XXX: Need more sanity checking of icrlo? */
 1126         KASSERT(lapic != NULL, ("%s called too early", __func__));
 1127         KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
 1128             ("%s: invalid dest field", __func__));
 1129         KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
 1130             ("%s: reserved bits set in ICR LO register", __func__));
 1131 
 1132         /* Set destination in ICR HI register if it is being used. */
 1133         eflags = intr_disable();
 1134         if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
 1135                 value = lapic->icr_hi;
 1136                 value &= ~APIC_ID_MASK;
 1137                 value |= dest << APIC_ID_SHIFT;
 1138                 lapic->icr_hi = value;
 1139         }
 1140 
 1141         /* Program the contents of the IPI and dispatch it. */
 1142         value = lapic->icr_lo;
 1143         value &= APIC_ICRLO_RESV_MASK;
 1144         value |= icrlo;
 1145         lapic->icr_lo = value;
 1146         intr_restore(eflags);
 1147 }
 1148 
 1149 #define BEFORE_SPIN     1000000
 1150 #ifdef DETECT_DEADLOCK
 1151 #define AFTER_SPIN      1000
 1152 #endif
 1153 
 1154 void
 1155 lapic_ipi_vectored(u_int vector, int dest)
 1156 {
 1157         register_t icrlo, destfield;
 1158 
 1159         KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
 1160             ("%s: invalid vector %d", __func__, vector));
 1161 
 1162         icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY |
 1163             APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE;
 1164         destfield = 0;
 1165         switch (dest) {
 1166         case APIC_IPI_DEST_SELF:
 1167                 icrlo |= APIC_DEST_SELF;
 1168                 break;
 1169         case APIC_IPI_DEST_ALL:
 1170                 icrlo |= APIC_DEST_ALLISELF;
 1171                 break;
 1172         case APIC_IPI_DEST_OTHERS:
 1173                 icrlo |= APIC_DEST_ALLESELF;
 1174                 break;
 1175         default:
 1176                 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
 1177                     ("%s: invalid destination 0x%x", __func__, dest));
 1178                 destfield = dest;
 1179         }
 1180 
 1181         /* Wait for an earlier IPI to finish. */
 1182         if (!lapic_ipi_wait(BEFORE_SPIN)) {
 1183                 if (panicstr != NULL)
 1184                         return;
 1185                 else
 1186                         panic("APIC: Previous IPI is stuck");
 1187         }
 1188 
 1189         lapic_ipi_raw(icrlo, destfield);
 1190 
 1191 #ifdef DETECT_DEADLOCK
 1192         /* Wait for IPI to be delivered. */
 1193         if (!lapic_ipi_wait(AFTER_SPIN)) {
 1194 #ifdef needsattention
 1195                 /*
 1196                  * XXX FIXME:
 1197                  *
 1198                  * The above function waits for the message to actually be
 1199                  * delivered.  It breaks out after an arbitrary timeout
 1200                  * since the message should eventually be delivered (at
 1201                  * least in theory) and that if it wasn't we would catch
 1202                  * the failure with the check above when the next IPI is
 1203                  * sent.
 1204                  *
 1205                  * We could skip this wait entirely, EXCEPT it probably
 1206                  * protects us from other routines that assume that the
 1207                  * message was delivered and acted upon when this function
 1208                  * returns.
 1209                  */
 1210                 printf("APIC: IPI might be stuck\n");
 1211 #else /* !needsattention */
 1212                 /* Wait until mesage is sent without a timeout. */
 1213                 while (lapic->icr_lo & APIC_DELSTAT_PEND)
 1214                         ia32_pause();
 1215 #endif /* needsattention */
 1216         }
 1217 #endif /* DETECT_DEADLOCK */
 1218 }
 1219 #endif /* SMP */

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