The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/local_apic.c

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    1 /*-
    2  * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
    3  * Copyright (c) 1996, by Steve Passe
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. The name of the developer may NOT be used to endorse or promote products
   12  *    derived from this software without specific prior written permission.
   13  * 3. Neither the name of the author nor the names of any co-contributors
   14  *    may be used to endorse or promote products derived from this software
   15  *    without specific prior written permission.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  */
   29 
   30 /*
   31  * Local APIC support on Pentium and later processors.
   32  */
   33 
   34 #include <sys/cdefs.h>
   35 __FBSDID("$FreeBSD$");
   36 
   37 #include "opt_hwpmc_hooks.h"
   38 #include "opt_kdtrace.h"
   39 
   40 #include "opt_ddb.h"
   41 
   42 #include <sys/param.h>
   43 #include <sys/systm.h>
   44 #include <sys/bus.h>
   45 #include <sys/kernel.h>
   46 #include <sys/lock.h>
   47 #include <sys/mutex.h>
   48 #include <sys/pcpu.h>
   49 #include <sys/smp.h>
   50 
   51 #include <vm/vm.h>
   52 #include <vm/pmap.h>
   53 
   54 #include <machine/apicreg.h>
   55 #include <machine/cpu.h>
   56 #include <machine/cputypes.h>
   57 #include <machine/frame.h>
   58 #include <machine/intr_machdep.h>
   59 #include <machine/apicvar.h>
   60 #include <machine/md_var.h>
   61 #include <machine/smp.h>
   62 #include <machine/specialreg.h>
   63 
   64 #ifdef DDB
   65 #include <sys/interrupt.h>
   66 #include <ddb/ddb.h>
   67 #endif
   68 
   69 #ifdef KDTRACE_HOOKS
   70 #include <sys/dtrace_bsd.h>
   71 cyclic_clock_func_t     lapic_cyclic_clock_func[MAXCPU];
   72 #endif
   73 
   74 /* Sanity checks on IDT vectors. */
   75 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
   76 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
   77 CTASSERT(APIC_LOCAL_INTS == 240);
   78 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
   79 
   80 /* Magic IRQ values for the timer and syscalls. */
   81 #define IRQ_TIMER       (NUM_IO_INTS + 1)
   82 #define IRQ_SYSCALL     (NUM_IO_INTS + 2)
   83 
   84 /*
   85  * Support for local APICs.  Local APICs manage interrupts on each
   86  * individual processor as opposed to I/O APICs which receive interrupts
   87  * from I/O devices and then forward them on to the local APICs.
   88  *
   89  * Local APICs can also send interrupts to each other thus providing the
   90  * mechanism for IPIs.
   91  */
   92 
   93 struct lvt {
   94         u_int lvt_edgetrigger:1;
   95         u_int lvt_activehi:1;
   96         u_int lvt_masked:1;
   97         u_int lvt_active:1;
   98         u_int lvt_mode:16;
   99         u_int lvt_vector:8;
  100 };
  101 
  102 struct lapic {
  103         struct lvt la_lvts[LVT_MAX + 1];
  104         u_int la_id:8;
  105         u_int la_cluster:4;
  106         u_int la_cluster_id:2;
  107         u_int la_present:1;
  108         u_long *la_timer_count;
  109         u_long la_hard_ticks;
  110         u_long la_stat_ticks;
  111         u_long la_prof_ticks;
  112 } static lapics[MAX_APIC_ID + 1];
  113 
  114 /* XXX: should thermal be an NMI? */
  115 
  116 /* Global defaults for local APIC LVT entries. */
  117 static struct lvt lvts[LVT_MAX + 1] = {
  118         { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 },  /* LINT0: masked ExtINT */
  119         { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 },     /* LINT1: NMI */
  120         { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT },      /* Timer */
  121         { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT },      /* Error */
  122         { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 },     /* PMC */
  123         { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT },    /* Thermal */
  124 };
  125 
  126 static inthand_t *ioint_handlers[] = {
  127         NULL,                   /* 0 - 31 */
  128         IDTVEC(apic_isr1),      /* 32 - 63 */
  129         IDTVEC(apic_isr2),      /* 64 - 95 */
  130         IDTVEC(apic_isr3),      /* 96 - 127 */
  131         IDTVEC(apic_isr4),      /* 128 - 159 */
  132         IDTVEC(apic_isr5),      /* 160 - 191 */
  133         IDTVEC(apic_isr6),      /* 192 - 223 */
  134         IDTVEC(apic_isr7),      /* 224 - 255 */
  135 };
  136 
  137 /* Include IDT_SYSCALL to make indexing easier. */
  138 static u_int ioint_irqs[APIC_NUM_IOINTS + 1];
  139 
  140 static u_int32_t lapic_timer_divisors[] = { 
  141         APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
  142         APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
  143 };
  144 
  145 extern inthand_t IDTVEC(rsvd);
  146 
  147 volatile lapic_t *lapic;
  148 vm_paddr_t lapic_paddr;
  149 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz;
  150 
  151 static void     lapic_enable(void);
  152 static void     lapic_resume(struct pic *pic);
  153 static void     lapic_timer_enable_intr(void);
  154 static void     lapic_timer_oneshot(u_int count);
  155 static void     lapic_timer_periodic(u_int count);
  156 static void     lapic_timer_set_divisor(u_int divisor);
  157 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
  158 
  159 struct pic lapic_pic = { .pic_resume = lapic_resume };
  160 
  161 static uint32_t
  162 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
  163 {
  164         struct lvt *lvt;
  165 
  166         KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin));
  167         if (la->la_lvts[pin].lvt_active)
  168                 lvt = &la->la_lvts[pin];
  169         else
  170                 lvt = &lvts[pin];
  171 
  172         value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
  173             APIC_LVT_VECTOR);
  174         if (lvt->lvt_edgetrigger == 0)
  175                 value |= APIC_LVT_TM;
  176         if (lvt->lvt_activehi == 0)
  177                 value |= APIC_LVT_IIPP_INTALO;
  178         if (lvt->lvt_masked)
  179                 value |= APIC_LVT_M;
  180         value |= lvt->lvt_mode;
  181         switch (lvt->lvt_mode) {
  182         case APIC_LVT_DM_NMI:
  183         case APIC_LVT_DM_SMI:
  184         case APIC_LVT_DM_INIT:
  185         case APIC_LVT_DM_EXTINT:
  186                 if (!lvt->lvt_edgetrigger) {
  187                         printf("lapic%u: Forcing LINT%u to edge trigger\n",
  188                             la->la_id, pin);
  189                         value |= APIC_LVT_TM;
  190                 }
  191                 /* Use a vector of 0. */
  192                 break;
  193         case APIC_LVT_DM_FIXED:
  194                 value |= lvt->lvt_vector;
  195                 break;
  196         default:
  197                 panic("bad APIC LVT delivery mode: %#x\n", value);
  198         }
  199         return (value);
  200 }
  201 
  202 /*
  203  * Map the local APIC and setup necessary interrupt vectors.
  204  */
  205 void
  206 lapic_init(vm_paddr_t addr)
  207 {
  208 
  209         /* Map the local APIC and setup the spurious interrupt handler. */
  210         KASSERT(trunc_page(addr) == addr,
  211             ("local APIC not aligned on a page boundary"));
  212         lapic = pmap_mapdev(addr, sizeof(lapic_t));
  213         lapic_paddr = addr;
  214         setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0);
  215 
  216         /* Perform basic initialization of the BSP's local APIC. */
  217         lapic_enable();
  218         ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
  219 
  220         /* Set BSP's per-CPU local APIC ID. */
  221         PCPU_SET(apic_id, lapic_id());
  222 
  223         /* Local APIC timer interrupt. */
  224         setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYSIGT, SEL_KPL, 0);
  225         ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER;
  226 
  227         /* XXX: error/thermal interrupts */
  228 }
  229 
  230 /*
  231  * Create a local APIC instance.
  232  */
  233 void
  234 lapic_create(u_int apic_id, int boot_cpu)
  235 {
  236         int i;
  237 
  238         if (apic_id > MAX_APIC_ID) {
  239                 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
  240                 if (boot_cpu)
  241                         panic("Can't ignore BSP");
  242                 return;
  243         }
  244         KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
  245             apic_id));
  246 
  247         /*
  248          * Assume no local LVT overrides and a cluster of 0 and
  249          * intra-cluster ID of 0.
  250          */
  251         lapics[apic_id].la_present = 1;
  252         lapics[apic_id].la_id = apic_id;
  253         for (i = 0; i < LVT_MAX; i++) {
  254                 lapics[apic_id].la_lvts[i] = lvts[i];
  255                 lapics[apic_id].la_lvts[i].lvt_active = 0;
  256         }
  257 
  258 #ifdef SMP
  259         cpu_add(apic_id, boot_cpu);
  260 #endif
  261 }
  262 
  263 /*
  264  * Dump contents of local APIC registers
  265  */
  266 void
  267 lapic_dump(const char* str)
  268 {
  269 
  270         printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
  271         printf("     ID: 0x%08x   VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n",
  272             lapic->id, lapic->version, lapic->ldr, lapic->dfr);
  273         printf("  lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
  274             lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
  275         printf("  timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n",
  276             lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error,
  277             lapic->lvt_pcint);
  278 }
  279 
  280 void
  281 lapic_setup(int boot)
  282 {
  283         struct lapic *la;
  284         u_int32_t maxlvt;
  285         register_t eflags;
  286         char buf[MAXCOMLEN + 1];
  287 
  288         la = &lapics[lapic_id()];
  289         KASSERT(la->la_present, ("missing APIC structure"));
  290         eflags = intr_disable();
  291         maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
  292 
  293         /* Initialize the TPR to allow all interrupts. */
  294         lapic_set_tpr(0);
  295 
  296         /* Setup spurious vector and enable the local APIC. */
  297         lapic_enable();
  298 
  299         /* Program LINT[01] LVT entries. */
  300         lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
  301         lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
  302 #ifdef  HWPMC_HOOKS
  303         /* Program the PMC LVT entry if present. */
  304         if (maxlvt >= LVT_PMC)
  305                 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
  306 #endif
  307 
  308         /* Program timer LVT and setup handler. */
  309         lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer);
  310         if (boot) {
  311                 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid));
  312                 intrcnt_add(buf, &la->la_timer_count);
  313         }
  314 
  315         /* We don't setup the timer during boot on the BSP until later. */
  316         if (!(boot && PCPU_GET(cpuid) == 0)) {
  317                 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor",
  318                     lapic_id()));
  319                 lapic_timer_set_divisor(lapic_timer_divisor);
  320                 lapic_timer_periodic(lapic_timer_period);
  321                 lapic_timer_enable_intr();
  322         }
  323 
  324         /* XXX: Error and thermal LVTs */
  325 
  326         if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
  327                 /*
  328                  * Detect the presence of C1E capability mostly on latest
  329                  * dual-cores (or future) k8 family.  This feature renders
  330                  * the local APIC timer dead, so we disable it by reading
  331                  * the Interrupt Pending Message register and clearing both
  332                  * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
  333                  * 
  334                  * Reference:
  335                  *   "BIOS and Kernel Developer's Guide for AMD NPT
  336                  *    Family 0Fh Processors"
  337                  *   #32559 revision 3.00
  338                  */
  339                 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
  340                     (cpu_id & 0x0fff0000) >=  0x00040000) {
  341                         uint64_t msr;
  342 
  343                         msr = rdmsr(0xc0010055);
  344                         if (msr & 0x18000000)
  345                                 wrmsr(0xc0010055, msr & ~0x18000000ULL);
  346                 }
  347         }
  348 
  349         intr_restore(eflags);
  350 }
  351 
  352 /*
  353  * Called by cpu_initclocks() on the BSP to setup the local APIC timer so
  354  * that it can drive hardclock, statclock, and profclock.  This function
  355  * returns true if it is able to use the local APIC timer to drive the
  356  * clocks and false if it is not able.
  357  */
  358 int
  359 lapic_setup_clock(void)
  360 {
  361         u_long value;
  362 
  363         /* Can't drive the timer without a local APIC. */
  364         if (lapic == NULL)
  365                 return (0);
  366 
  367         /* Start off with a divisor of 2 (power on reset default). */
  368         lapic_timer_divisor = 2;
  369 
  370         /* Try to calibrate the local APIC timer. */
  371         do {
  372                 lapic_timer_set_divisor(lapic_timer_divisor);
  373                 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
  374                 DELAY(2000000);
  375                 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
  376                 if (value != APIC_TIMER_MAX_COUNT)
  377                         break;
  378                 lapic_timer_divisor <<= 1;
  379         } while (lapic_timer_divisor <= 128);
  380         if (lapic_timer_divisor > 128)
  381                 panic("lapic: Divisor too big");
  382         value /= 2;
  383         if (bootverbose)
  384                 printf("lapic: Divisor %lu, Frequency %lu hz\n",
  385                     lapic_timer_divisor, value);
  386 
  387         /*
  388          * We want to run stathz in the neighborhood of 128hz.  We would
  389          * like profhz to run as often as possible, so we let it run on
  390          * each clock tick.  We try to honor the requested 'hz' value as
  391          * much as possible.
  392          *
  393          * If 'hz' is above 1500, then we just let the lapic timer
  394          * (and profhz) run at hz.  If 'hz' is below 1500 but above
  395          * 750, then we let the lapic timer run at 2 * 'hz'.  If 'hz'
  396          * is below 750 then we let the lapic timer run at 4 * 'hz'.
  397          */
  398         if (hz >= 1500)
  399                 lapic_timer_hz = hz;
  400         else if (hz >= 750)
  401                 lapic_timer_hz = hz * 2;
  402         else
  403                 lapic_timer_hz = hz * 4;
  404         if (lapic_timer_hz < 128)
  405                 stathz = lapic_timer_hz;
  406         else
  407                 stathz = lapic_timer_hz / (lapic_timer_hz / 128);
  408         profhz = lapic_timer_hz;
  409         lapic_timer_period = value / lapic_timer_hz;
  410 
  411         /*
  412          * Start up the timer on the BSP.  The APs will kick off their
  413          * timer during lapic_setup().
  414          */
  415         lapic_timer_periodic(lapic_timer_period);
  416         lapic_timer_enable_intr();
  417         return (1);
  418 }
  419 
  420 void
  421 lapic_disable(void)
  422 {
  423         uint32_t value;
  424 
  425         /* Software disable the local APIC. */
  426         value = lapic->svr;
  427         value &= ~APIC_SVR_SWEN;
  428         lapic->svr = value;
  429 }
  430 
  431 static void
  432 lapic_enable(void)
  433 {
  434         u_int32_t value;
  435 
  436         /* Program the spurious vector to enable the local APIC. */
  437         value = lapic->svr;
  438         value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
  439         value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
  440         lapic->svr = value;
  441 }
  442 
  443 /* Reset the local APIC on the BSP during resume. */
  444 static void
  445 lapic_resume(struct pic *pic)
  446 {
  447 
  448         lapic_setup(0);
  449 }
  450 
  451 int
  452 lapic_id(void)
  453 {
  454 
  455         KASSERT(lapic != NULL, ("local APIC is not mapped"));
  456         return (lapic->id >> APIC_ID_SHIFT);
  457 }
  458 
  459 int
  460 lapic_intr_pending(u_int vector)
  461 {
  462         volatile u_int32_t *irr;
  463 
  464         /*
  465          * The IRR registers are an array of 128-bit registers each of
  466          * which only describes 32 interrupts in the low 32 bits..  Thus,
  467          * we divide the vector by 32 to get the 128-bit index.  We then
  468          * multiply that index by 4 to get the equivalent index from
  469          * treating the IRR as an array of 32-bit registers.  Finally, we
  470          * modulus the vector by 32 to determine the individual bit to
  471          * test.
  472          */
  473         irr = &lapic->irr0;
  474         return (irr[(vector / 32) * 4] & 1 << (vector % 32));
  475 }
  476 
  477 void
  478 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
  479 {
  480         struct lapic *la;
  481 
  482         KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
  483             __func__, apic_id));
  484         KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
  485             __func__, cluster));
  486         KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
  487             ("%s: intra cluster id %u too big", __func__, cluster_id));
  488         la = &lapics[apic_id];
  489         la->la_cluster = cluster;
  490         la->la_cluster_id = cluster_id;
  491 }
  492 
  493 int
  494 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
  495 {
  496 
  497         if (pin > LVT_MAX)
  498                 return (EINVAL);
  499         if (apic_id == APIC_ID_ALL) {
  500                 lvts[pin].lvt_masked = masked;
  501                 if (bootverbose)
  502                         printf("lapic:");
  503         } else {
  504                 KASSERT(lapics[apic_id].la_present,
  505                     ("%s: missing APIC %u", __func__, apic_id));
  506                 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
  507                 lapics[apic_id].la_lvts[pin].lvt_active = 1;
  508                 if (bootverbose)
  509                         printf("lapic%u:", apic_id);
  510         }
  511         if (bootverbose)
  512                 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
  513         return (0);
  514 }
  515 
  516 int
  517 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
  518 {
  519         struct lvt *lvt;
  520 
  521         if (pin > LVT_MAX)
  522                 return (EINVAL);
  523         if (apic_id == APIC_ID_ALL) {
  524                 lvt = &lvts[pin];
  525                 if (bootverbose)
  526                         printf("lapic:");
  527         } else {
  528                 KASSERT(lapics[apic_id].la_present,
  529                     ("%s: missing APIC %u", __func__, apic_id));
  530                 lvt = &lapics[apic_id].la_lvts[pin];
  531                 lvt->lvt_active = 1;
  532                 if (bootverbose)
  533                         printf("lapic%u:", apic_id);
  534         }
  535         lvt->lvt_mode = mode;
  536         switch (mode) {
  537         case APIC_LVT_DM_NMI:
  538         case APIC_LVT_DM_SMI:
  539         case APIC_LVT_DM_INIT:
  540         case APIC_LVT_DM_EXTINT:
  541                 lvt->lvt_edgetrigger = 1;
  542                 lvt->lvt_activehi = 1;
  543                 if (mode == APIC_LVT_DM_EXTINT)
  544                         lvt->lvt_masked = 1;
  545                 else
  546                         lvt->lvt_masked = 0;
  547                 break;
  548         default:
  549                 panic("Unsupported delivery mode: 0x%x\n", mode);
  550         }
  551         if (bootverbose) {
  552                 printf(" Routing ");
  553                 switch (mode) {
  554                 case APIC_LVT_DM_NMI:
  555                         printf("NMI");
  556                         break;
  557                 case APIC_LVT_DM_SMI:
  558                         printf("SMI");
  559                         break;
  560                 case APIC_LVT_DM_INIT:
  561                         printf("INIT");
  562                         break;
  563                 case APIC_LVT_DM_EXTINT:
  564                         printf("ExtINT");
  565                         break;
  566                 }
  567                 printf(" -> LINT%u\n", pin);
  568         }
  569         return (0);
  570 }
  571 
  572 int
  573 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
  574 {
  575 
  576         if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM)
  577                 return (EINVAL);
  578         if (apic_id == APIC_ID_ALL) {
  579                 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
  580                 if (bootverbose)
  581                         printf("lapic:");
  582         } else {
  583                 KASSERT(lapics[apic_id].la_present,
  584                     ("%s: missing APIC %u", __func__, apic_id));
  585                 lapics[apic_id].la_lvts[pin].lvt_active = 1;
  586                 lapics[apic_id].la_lvts[pin].lvt_activehi =
  587                     (pol == INTR_POLARITY_HIGH);
  588                 if (bootverbose)
  589                         printf("lapic%u:", apic_id);
  590         }
  591         if (bootverbose)
  592                 printf(" LINT%u polarity: %s\n", pin,
  593                     pol == INTR_POLARITY_HIGH ? "high" : "low");
  594         return (0);
  595 }
  596 
  597 int
  598 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger)
  599 {
  600 
  601         if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
  602                 return (EINVAL);
  603         if (apic_id == APIC_ID_ALL) {
  604                 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
  605                 if (bootverbose)
  606                         printf("lapic:");
  607         } else {
  608                 KASSERT(lapics[apic_id].la_present,
  609                     ("%s: missing APIC %u", __func__, apic_id));
  610                 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
  611                     (trigger == INTR_TRIGGER_EDGE);
  612                 lapics[apic_id].la_lvts[pin].lvt_active = 1;
  613                 if (bootverbose)
  614                         printf("lapic%u:", apic_id);
  615         }
  616         if (bootverbose)
  617                 printf(" LINT%u trigger: %s\n", pin,
  618                     trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
  619         return (0);
  620 }
  621 
  622 /*
  623  * Adjust the TPR of the current CPU so that it blocks all interrupts below
  624  * the passed in vector.
  625  */
  626 void
  627 lapic_set_tpr(u_int vector)
  628 {
  629 #ifdef CHEAP_TPR
  630         lapic->tpr = vector;
  631 #else
  632         u_int32_t tpr;
  633 
  634         tpr = lapic->tpr & ~APIC_TPR_PRIO;
  635         tpr |= vector;
  636         lapic->tpr = tpr;
  637 #endif
  638 }
  639 
  640 void
  641 lapic_eoi(void)
  642 {
  643 
  644         lapic->eoi = 0;
  645 }
  646 
  647 void
  648 lapic_handle_intr(int vector, struct trapframe *frame)
  649 {
  650         struct intsrc *isrc;
  651 
  652         if (vector == -1)
  653                 panic("Couldn't get vector from ISR!");
  654         isrc = intr_lookup_source(apic_idt_to_irq(vector));
  655         intr_execute_handlers(isrc, frame);
  656 }
  657 
  658 void
  659 lapic_handle_timer(struct trapframe *frame)
  660 {
  661         struct lapic *la;
  662 
  663         /* Send EOI first thing. */
  664         lapic_eoi();
  665 
  666 #if defined(SMP) && !defined(SCHED_ULE)
  667         /*
  668          * Don't do any accounting for the disabled HTT cores, since it
  669          * will provide misleading numbers for the userland.
  670          *
  671          * No locking is necessary here, since even if we loose the race
  672          * when hlt_cpus_mask changes it is not a big deal, really.
  673          *
  674          * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask
  675          * and unlike other schedulers it actually schedules threads to
  676          * those CPUs.
  677          */
  678         if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0)
  679                 return;
  680 #endif
  681 
  682         /* Look up our local APIC structure for the tick counters. */
  683         la = &lapics[PCPU_GET(apic_id)];
  684         (*la->la_timer_count)++;
  685         critical_enter();
  686 
  687 #ifdef KDTRACE_HOOKS
  688         /*
  689          * If the DTrace hooks are configured and a callback function
  690          * has been registered, then call it to process the high speed
  691          * timers.
  692          */
  693         int cpu = PCPU_GET(cpuid);
  694         if (lapic_cyclic_clock_func[cpu] != NULL)
  695                 (*lapic_cyclic_clock_func[cpu])(frame);
  696 #endif
  697 
  698         /* Fire hardclock at hz. */
  699         la->la_hard_ticks += hz;
  700         if (la->la_hard_ticks >= lapic_timer_hz) {
  701                 la->la_hard_ticks -= lapic_timer_hz;
  702                 if (PCPU_GET(cpuid) == 0)
  703                         hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
  704                 else
  705                         hardclock_cpu(TRAPF_USERMODE(frame));
  706         }
  707 
  708         /* Fire statclock at stathz. */
  709         la->la_stat_ticks += stathz;
  710         if (la->la_stat_ticks >= lapic_timer_hz) {
  711                 la->la_stat_ticks -= lapic_timer_hz;
  712                 statclock(TRAPF_USERMODE(frame));
  713         }
  714 
  715         /* Fire profclock at profhz, but only when needed. */
  716         la->la_prof_ticks += profhz;
  717         if (la->la_prof_ticks >= lapic_timer_hz) {
  718                 la->la_prof_ticks -= lapic_timer_hz;
  719                 if (profprocs != 0)
  720                         profclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
  721         }
  722         critical_exit();
  723 }
  724 
  725 static void
  726 lapic_timer_set_divisor(u_int divisor)
  727 {
  728 
  729         KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor));
  730         KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) /
  731             sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor));
  732         lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1];
  733 }
  734 
  735 static void
  736 lapic_timer_oneshot(u_int count)
  737 {
  738         u_int32_t value;
  739 
  740         value = lapic->lvt_timer;
  741         value &= ~APIC_LVTT_TM;
  742         value |= APIC_LVTT_TM_ONE_SHOT;
  743         lapic->lvt_timer = value;
  744         lapic->icr_timer = count;
  745 }
  746 
  747 static void
  748 lapic_timer_periodic(u_int count)
  749 {
  750         u_int32_t value;
  751 
  752         value = lapic->lvt_timer;
  753         value &= ~APIC_LVTT_TM;
  754         value |= APIC_LVTT_TM_PERIODIC;
  755         lapic->lvt_timer = value;
  756         lapic->icr_timer = count;
  757 }
  758 
  759 static void
  760 lapic_timer_enable_intr(void)
  761 {
  762         u_int32_t value;
  763 
  764         value = lapic->lvt_timer;
  765         value &= ~APIC_LVT_M;
  766         lapic->lvt_timer = value;
  767 }
  768 
  769 /* Request a free IDT vector to be used by the specified IRQ. */
  770 u_int
  771 apic_alloc_vector(u_int irq)
  772 {
  773         u_int vector;
  774 
  775         KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
  776 
  777         /*
  778          * Search for a free vector.  Currently we just use a very simple
  779          * algorithm to find the first free vector.
  780          */
  781         mtx_lock_spin(&icu_lock);
  782         for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
  783                 if (ioint_irqs[vector] != 0)
  784                         continue;
  785                 ioint_irqs[vector] = irq;
  786                 mtx_unlock_spin(&icu_lock);
  787                 return (vector + APIC_IO_INTS);
  788         }
  789         mtx_unlock_spin(&icu_lock);
  790         panic("Couldn't find an APIC vector for IRQ %u", irq);
  791 }
  792 
  793 /*
  794  * Request 'count' free contiguous IDT vectors to be used by 'count'
  795  * IRQs.  'count' must be a power of two and the vectors will be
  796  * aligned on a boundary of 'align'.  If the request cannot be
  797  * satisfied, 0 is returned.
  798  */
  799 u_int
  800 apic_alloc_vectors(u_int *irqs, u_int count, u_int align)
  801 {
  802         u_int first, run, vector;
  803 
  804         KASSERT(powerof2(count), ("bad count"));
  805         KASSERT(powerof2(align), ("bad align"));
  806         KASSERT(align >= count, ("align < count"));
  807 #ifdef INVARIANTS
  808         for (run = 0; run < count; run++)
  809                 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u",
  810                     irqs[run], run));
  811 #endif
  812 
  813         /*
  814          * Search for 'count' free vectors.  As with apic_alloc_vector(),
  815          * this just uses a simple first fit algorithm.
  816          */
  817         run = 0;
  818         first = 0;
  819         mtx_lock_spin(&icu_lock);
  820         for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
  821 
  822                 /* Vector is in use, end run. */
  823                 if (ioint_irqs[vector] != 0) {
  824                         run = 0;
  825                         first = 0;
  826                         continue;
  827                 }
  828 
  829                 /* Start a new run if run == 0 and vector is aligned. */
  830                 if (run == 0) {
  831                         if ((vector & (align - 1)) != 0)
  832                                 continue;
  833                         first = vector;
  834                 }
  835                 run++;
  836 
  837                 /* Keep looping if the run isn't long enough yet. */
  838                 if (run < count)
  839                         continue;
  840 
  841                 /* Found a run, assign IRQs and return the first vector. */
  842                 for (vector = 0; vector < count; vector++)
  843                         ioint_irqs[first + vector] = irqs[vector];
  844                 mtx_unlock_spin(&icu_lock);
  845                 return (first + APIC_IO_INTS);
  846         }
  847         mtx_unlock_spin(&icu_lock);
  848         printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count);
  849         return (0);
  850 }
  851 
  852 void
  853 apic_enable_vector(u_int vector)
  854 {
  855 
  856         KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
  857         KASSERT(ioint_handlers[vector / 32] != NULL,
  858             ("No ISR handler for vector %u", vector));
  859         setidt(vector, ioint_handlers[vector / 32], SDT_SYSIGT, SEL_KPL, 0);
  860 }
  861 
  862 void
  863 apic_disable_vector(u_int vector)
  864 {
  865 
  866         KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
  867         KASSERT(ioint_handlers[vector / 32] != NULL,
  868             ("No ISR handler for vector %u", vector));
  869         setidt(vector, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
  870 }
  871 
  872 /* Release an APIC vector when it's no longer in use. */
  873 void
  874 apic_free_vector(u_int vector, u_int irq)
  875 {
  876         KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
  877             vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
  878             ("Vector %u does not map to an IRQ line", vector));
  879         KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
  880         KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch"));
  881         mtx_lock_spin(&icu_lock);
  882         ioint_irqs[vector - APIC_IO_INTS] = 0;
  883         mtx_unlock_spin(&icu_lock);
  884 }
  885 
  886 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */
  887 u_int
  888 apic_idt_to_irq(u_int vector)
  889 {
  890 
  891         KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
  892             vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
  893             ("Vector %u does not map to an IRQ line", vector));
  894         return (ioint_irqs[vector - APIC_IO_INTS]);
  895 }
  896 
  897 #ifdef DDB
  898 /*
  899  * Dump data about APIC IDT vector mappings.
  900  */
  901 DB_SHOW_COMMAND(apic, db_show_apic)
  902 {
  903         struct intsrc *isrc;
  904         int i, verbose;
  905         u_int irq;
  906 
  907         if (strcmp(modif, "vv") == 0)
  908                 verbose = 2;
  909         else if (strcmp(modif, "v") == 0)
  910                 verbose = 1;
  911         else
  912                 verbose = 0;
  913         for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) {
  914                 irq = ioint_irqs[i];
  915                 if (irq != 0 && irq != IRQ_SYSCALL) {
  916                         db_printf("vec 0x%2x -> ", i + APIC_IO_INTS);
  917                         if (irq == IRQ_TIMER)
  918                                 db_printf("lapic timer\n");
  919                         else if (irq < NUM_IO_INTS) {
  920                                 isrc = intr_lookup_source(irq);
  921                                 if (isrc == NULL || verbose == 0)
  922                                         db_printf("IRQ %u\n", irq);
  923                                 else
  924                                         db_dump_intr_event(isrc->is_event,
  925                                             verbose == 2);
  926                         } else
  927                                 db_printf("IRQ %u ???\n", irq);
  928                 }
  929         }
  930 }
  931 
  932 static void
  933 dump_mask(const char *prefix, uint32_t v, int base)
  934 {
  935         int i, first;
  936 
  937         first = 1;
  938         for (i = 0; i < 32; i++)
  939                 if (v & (1 << i)) {
  940                         if (first) {
  941                                 db_printf("%s:", prefix);
  942                                 first = 0;
  943                         }
  944                         db_printf(" %02x", base + i);
  945                 }
  946         if (!first)
  947                 db_printf("\n");
  948 }
  949 
  950 /* Show info from the lapic regs for this CPU. */
  951 DB_SHOW_COMMAND(lapic, db_show_lapic)
  952 {
  953         uint32_t v;
  954 
  955         db_printf("lapic ID = %d\n", lapic_id());
  956         v = lapic->version;
  957         db_printf("version  = %d.%d\n", (v & APIC_VER_VERSION) >> 4,
  958             v & 0xf);
  959         db_printf("max LVT  = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT);
  960         v = lapic->svr;
  961         db_printf("SVR      = %02x (%s)\n", v & APIC_SVR_VECTOR,
  962             v & APIC_SVR_ENABLE ? "enabled" : "disabled");
  963         db_printf("TPR      = %02x\n", lapic->tpr);
  964 
  965 #define dump_field(prefix, index)                                       \
  966         dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index,   \
  967             index * 32)
  968 
  969         db_printf("In-service Interrupts:\n");
  970         dump_field(isr, 0);
  971         dump_field(isr, 1);
  972         dump_field(isr, 2);
  973         dump_field(isr, 3);
  974         dump_field(isr, 4);
  975         dump_field(isr, 5);
  976         dump_field(isr, 6);
  977         dump_field(isr, 7);
  978 
  979         db_printf("TMR Interrupts:\n");
  980         dump_field(tmr, 0);
  981         dump_field(tmr, 1);
  982         dump_field(tmr, 2);
  983         dump_field(tmr, 3);
  984         dump_field(tmr, 4);
  985         dump_field(tmr, 5);
  986         dump_field(tmr, 6);
  987         dump_field(tmr, 7);
  988 
  989         db_printf("IRR Interrupts:\n");
  990         dump_field(irr, 0);
  991         dump_field(irr, 1);
  992         dump_field(irr, 2);
  993         dump_field(irr, 3);
  994         dump_field(irr, 4);
  995         dump_field(irr, 5);
  996         dump_field(irr, 6);
  997         dump_field(irr, 7);
  998 
  999 #undef dump_field
 1000 }
 1001 #endif
 1002 
 1003 /*
 1004  * APIC probing support code.  This includes code to manage enumerators.
 1005  */
 1006 
 1007 static SLIST_HEAD(, apic_enumerator) enumerators =
 1008         SLIST_HEAD_INITIALIZER(enumerators);
 1009 static struct apic_enumerator *best_enum;
 1010         
 1011 void
 1012 apic_register_enumerator(struct apic_enumerator *enumerator)
 1013 {
 1014 #ifdef INVARIANTS
 1015         struct apic_enumerator *apic_enum;
 1016 
 1017         SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
 1018                 if (apic_enum == enumerator)
 1019                         panic("%s: Duplicate register of %s", __func__,
 1020                             enumerator->apic_name);
 1021         }
 1022 #endif
 1023         SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
 1024 }
 1025 
 1026 /*
 1027  * We have to look for CPU's very, very early because certain subsystems
 1028  * want to know how many CPU's we have extremely early on in the boot
 1029  * process.
 1030  */
 1031 static void
 1032 apic_init(void *dummy __unused)
 1033 {
 1034         struct apic_enumerator *enumerator;
 1035         int retval, best;
 1036 
 1037         /* Don't probe if APIC mode is disabled. */
 1038         if (resource_disabled("apic", 0))
 1039                 return;
 1040 
 1041         /* First, probe all the enumerators to find the best match. */
 1042         best_enum = NULL;
 1043         best = 0;
 1044         SLIST_FOREACH(enumerator, &enumerators, apic_next) {
 1045                 retval = enumerator->apic_probe();
 1046                 if (retval > 0)
 1047                         continue;
 1048                 if (best_enum == NULL || best < retval) {
 1049                         best_enum = enumerator;
 1050                         best = retval;
 1051                 }
 1052         }
 1053         if (best_enum == NULL) {
 1054                 if (bootverbose)
 1055                         printf("APIC: Could not find any APICs.\n");
 1056                 return;
 1057         }
 1058 
 1059         if (bootverbose)
 1060                 printf("APIC: Using the %s enumerator.\n",
 1061                     best_enum->apic_name);
 1062 
 1063         /* Second, probe the CPU's in the system. */
 1064         retval = best_enum->apic_probe_cpus();
 1065         if (retval != 0)
 1066                 printf("%s: Failed to probe CPUs: returned %d\n",
 1067                     best_enum->apic_name, retval);
 1068 }
 1069 SYSINIT(apic_init, SI_SUB_TUNABLES - 1, SI_ORDER_SECOND, apic_init, NULL);
 1070 
 1071 /*
 1072  * Setup the local APIC.  We have to do this prior to starting up the APs
 1073  * in the SMP case.
 1074  */
 1075 static void
 1076 apic_setup_local(void *dummy __unused)
 1077 {
 1078         int retval;
 1079 
 1080         if (best_enum == NULL)
 1081                 return;
 1082         retval = best_enum->apic_setup_local();
 1083         if (retval != 0)
 1084                 printf("%s: Failed to setup the local APIC: returned %d\n",
 1085                     best_enum->apic_name, retval);
 1086 }
 1087 SYSINIT(apic_setup_local, SI_SUB_CPU, SI_ORDER_SECOND, apic_setup_local,
 1088     NULL);
 1089 
 1090 /*
 1091  * Setup the I/O APICs.
 1092  */
 1093 static void
 1094 apic_setup_io(void *dummy __unused)
 1095 {
 1096         int retval;
 1097 
 1098         if (best_enum == NULL)
 1099                 return;
 1100         retval = best_enum->apic_setup_io();
 1101         if (retval != 0)
 1102                 printf("%s: Failed to setup I/O APICs: returned %d\n",
 1103                     best_enum->apic_name, retval);
 1104 
 1105         /*
 1106          * Finish setting up the local APIC on the BSP once we know how to
 1107          * properly program the LINT pins.
 1108          */
 1109         lapic_setup(1);
 1110         intr_register_pic(&lapic_pic);
 1111         if (bootverbose)
 1112                 lapic_dump("BSP");
 1113 
 1114         /* Enable the MSI "pic". */
 1115         msi_init();
 1116 }
 1117 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL);
 1118 
 1119 #ifdef SMP
 1120 /*
 1121  * Inter Processor Interrupt functions.  The lapic_ipi_*() functions are
 1122  * private to the sys/amd64 code.  The public interface for the rest of the
 1123  * kernel is defined in mp_machdep.c.
 1124  */
 1125 int
 1126 lapic_ipi_wait(int delay)
 1127 {
 1128         int x, incr;
 1129 
 1130         /*
 1131          * Wait delay loops for IPI to be sent.  This is highly bogus
 1132          * since this is sensitive to CPU clock speed.  If delay is
 1133          * -1, we wait forever.
 1134          */
 1135         if (delay == -1) {
 1136                 incr = 0;
 1137                 delay = 1;
 1138         } else
 1139                 incr = 1;
 1140         for (x = 0; x < delay; x += incr) {
 1141                 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE)
 1142                         return (1);
 1143                 ia32_pause();
 1144         }
 1145         return (0);
 1146 }
 1147 
 1148 void
 1149 lapic_ipi_raw(register_t icrlo, u_int dest)
 1150 {
 1151         register_t value, eflags;
 1152 
 1153         /* XXX: Need more sanity checking of icrlo? */
 1154         KASSERT(lapic != NULL, ("%s called too early", __func__));
 1155         KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
 1156             ("%s: invalid dest field", __func__));
 1157         KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
 1158             ("%s: reserved bits set in ICR LO register", __func__));
 1159 
 1160         /* Set destination in ICR HI register if it is being used. */
 1161         eflags = intr_disable();
 1162         if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
 1163                 value = lapic->icr_hi;
 1164                 value &= ~APIC_ID_MASK;
 1165                 value |= dest << APIC_ID_SHIFT;
 1166                 lapic->icr_hi = value;
 1167         }
 1168 
 1169         /* Program the contents of the IPI and dispatch it. */
 1170         value = lapic->icr_lo;
 1171         value &= APIC_ICRLO_RESV_MASK;
 1172         value |= icrlo;
 1173         lapic->icr_lo = value;
 1174         intr_restore(eflags);
 1175 }
 1176 
 1177 #define BEFORE_SPIN     1000000
 1178 #ifdef DETECT_DEADLOCK
 1179 #define AFTER_SPIN      1000
 1180 #endif
 1181 
 1182 void
 1183 lapic_ipi_vectored(u_int vector, int dest)
 1184 {
 1185         register_t icrlo, destfield;
 1186 
 1187         KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
 1188             ("%s: invalid vector %d", __func__, vector));
 1189 
 1190         icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY |
 1191             APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE;
 1192         destfield = 0;
 1193         switch (dest) {
 1194         case APIC_IPI_DEST_SELF:
 1195                 icrlo |= APIC_DEST_SELF;
 1196                 break;
 1197         case APIC_IPI_DEST_ALL:
 1198                 icrlo |= APIC_DEST_ALLISELF;
 1199                 break;
 1200         case APIC_IPI_DEST_OTHERS:
 1201                 icrlo |= APIC_DEST_ALLESELF;
 1202                 break;
 1203         default:
 1204                 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
 1205                     ("%s: invalid destination 0x%x", __func__, dest));
 1206                 destfield = dest;
 1207         }
 1208 
 1209         /* Wait for an earlier IPI to finish. */
 1210         if (!lapic_ipi_wait(BEFORE_SPIN)) {
 1211                 if (panicstr != NULL)
 1212                         return;
 1213                 else
 1214                         panic("APIC: Previous IPI is stuck");
 1215         }
 1216 
 1217         lapic_ipi_raw(icrlo, destfield);
 1218 
 1219 #ifdef DETECT_DEADLOCK
 1220         /* Wait for IPI to be delivered. */
 1221         if (!lapic_ipi_wait(AFTER_SPIN)) {
 1222 #ifdef needsattention
 1223                 /*
 1224                  * XXX FIXME:
 1225                  *
 1226                  * The above function waits for the message to actually be
 1227                  * delivered.  It breaks out after an arbitrary timeout
 1228                  * since the message should eventually be delivered (at
 1229                  * least in theory) and that if it wasn't we would catch
 1230                  * the failure with the check above when the next IPI is
 1231                  * sent.
 1232                  *
 1233                  * We could skip this wait entirely, EXCEPT it probably
 1234                  * protects us from other routines that assume that the
 1235                  * message was delivered and acted upon when this function
 1236                  * returns.
 1237                  */
 1238                 printf("APIC: IPI might be stuck\n");
 1239 #else /* !needsattention */
 1240                 /* Wait until mesage is sent without a timeout. */
 1241                 while (lapic->icr_lo & APIC_DELSTAT_PEND)
 1242                         ia32_pause();
 1243 #endif /* needsattention */
 1244         }
 1245 #endif /* DETECT_DEADLOCK */
 1246 }
 1247 #endif /* SMP */

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