1 /*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /*
31 * Local APIC support on Pentium and later processors.
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD: releng/7.3/sys/amd64/amd64/local_apic.c 196616 2009-08-28 14:22:01Z jhb $");
36
37 #include "opt_hwpmc_hooks.h"
38 #include "opt_kdtrace.h"
39
40 #include "opt_ddb.h"
41
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/bus.h>
45 #include <sys/kernel.h>
46 #include <sys/lock.h>
47 #include <sys/mutex.h>
48 #include <sys/pcpu.h>
49 #include <sys/smp.h>
50
51 #include <vm/vm.h>
52 #include <vm/pmap.h>
53
54 #include <machine/apicreg.h>
55 #include <machine/cpu.h>
56 #include <machine/cputypes.h>
57 #include <machine/frame.h>
58 #include <machine/intr_machdep.h>
59 #include <machine/apicvar.h>
60 #include <machine/md_var.h>
61 #include <machine/smp.h>
62 #include <machine/specialreg.h>
63
64 #ifdef DDB
65 #include <sys/interrupt.h>
66 #include <ddb/ddb.h>
67 #endif
68
69 #ifdef KDTRACE_HOOKS
70 #include <sys/dtrace_bsd.h>
71 cyclic_clock_func_t lapic_cyclic_clock_func[MAXCPU];
72 #endif
73
74 /* Sanity checks on IDT vectors. */
75 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
76 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
77 CTASSERT(APIC_LOCAL_INTS == 240);
78 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
79
80 /* Magic IRQ values for the timer and syscalls. */
81 #define IRQ_TIMER (NUM_IO_INTS + 1)
82 #define IRQ_SYSCALL (NUM_IO_INTS + 2)
83
84 /*
85 * Support for local APICs. Local APICs manage interrupts on each
86 * individual processor as opposed to I/O APICs which receive interrupts
87 * from I/O devices and then forward them on to the local APICs.
88 *
89 * Local APICs can also send interrupts to each other thus providing the
90 * mechanism for IPIs.
91 */
92
93 struct lvt {
94 u_int lvt_edgetrigger:1;
95 u_int lvt_activehi:1;
96 u_int lvt_masked:1;
97 u_int lvt_active:1;
98 u_int lvt_mode:16;
99 u_int lvt_vector:8;
100 };
101
102 struct lapic {
103 struct lvt la_lvts[LVT_MAX + 1];
104 u_int la_id:8;
105 u_int la_cluster:4;
106 u_int la_cluster_id:2;
107 u_int la_present:1;
108 u_long *la_timer_count;
109 u_long la_hard_ticks;
110 u_long la_stat_ticks;
111 u_long la_prof_ticks;
112 } static lapics[MAX_APIC_ID + 1];
113
114 /* XXX: should thermal be an NMI? */
115
116 /* Global defaults for local APIC LVT entries. */
117 static struct lvt lvts[LVT_MAX + 1] = {
118 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */
119 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */
120 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */
121 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */
122 { 1, 1, 1, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */
123 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */
124 };
125
126 static inthand_t *ioint_handlers[] = {
127 NULL, /* 0 - 31 */
128 IDTVEC(apic_isr1), /* 32 - 63 */
129 IDTVEC(apic_isr2), /* 64 - 95 */
130 IDTVEC(apic_isr3), /* 96 - 127 */
131 IDTVEC(apic_isr4), /* 128 - 159 */
132 IDTVEC(apic_isr5), /* 160 - 191 */
133 IDTVEC(apic_isr6), /* 192 - 223 */
134 IDTVEC(apic_isr7), /* 224 - 255 */
135 };
136
137 /* Include IDT_SYSCALL to make indexing easier. */
138 static u_int ioint_irqs[APIC_NUM_IOINTS + 1];
139
140 static u_int32_t lapic_timer_divisors[] = {
141 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
142 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
143 };
144
145 extern inthand_t IDTVEC(rsvd);
146
147 volatile lapic_t *lapic;
148 vm_paddr_t lapic_paddr;
149 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz;
150
151 static void lapic_enable(void);
152 static void lapic_resume(struct pic *pic);
153 static void lapic_timer_enable_intr(void);
154 static void lapic_timer_oneshot(u_int count);
155 static void lapic_timer_periodic(u_int count);
156 static void lapic_timer_set_divisor(u_int divisor);
157 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
158
159 struct pic lapic_pic = { .pic_resume = lapic_resume };
160
161 static uint32_t
162 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
163 {
164 struct lvt *lvt;
165
166 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin));
167 if (la->la_lvts[pin].lvt_active)
168 lvt = &la->la_lvts[pin];
169 else
170 lvt = &lvts[pin];
171
172 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
173 APIC_LVT_VECTOR);
174 if (lvt->lvt_edgetrigger == 0)
175 value |= APIC_LVT_TM;
176 if (lvt->lvt_activehi == 0)
177 value |= APIC_LVT_IIPP_INTALO;
178 if (lvt->lvt_masked)
179 value |= APIC_LVT_M;
180 value |= lvt->lvt_mode;
181 switch (lvt->lvt_mode) {
182 case APIC_LVT_DM_NMI:
183 case APIC_LVT_DM_SMI:
184 case APIC_LVT_DM_INIT:
185 case APIC_LVT_DM_EXTINT:
186 if (!lvt->lvt_edgetrigger) {
187 printf("lapic%u: Forcing LINT%u to edge trigger\n",
188 la->la_id, pin);
189 value |= APIC_LVT_TM;
190 }
191 /* Use a vector of 0. */
192 break;
193 case APIC_LVT_DM_FIXED:
194 value |= lvt->lvt_vector;
195 break;
196 default:
197 panic("bad APIC LVT delivery mode: %#x\n", value);
198 }
199 return (value);
200 }
201
202 /*
203 * Map the local APIC and setup necessary interrupt vectors.
204 */
205 void
206 lapic_init(vm_paddr_t addr)
207 {
208
209 /* Map the local APIC and setup the spurious interrupt handler. */
210 KASSERT(trunc_page(addr) == addr,
211 ("local APIC not aligned on a page boundary"));
212 lapic = pmap_mapdev(addr, sizeof(lapic_t));
213 lapic_paddr = addr;
214 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0);
215
216 /* Perform basic initialization of the BSP's local APIC. */
217 lapic_enable();
218 ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
219
220 /* Set BSP's per-CPU local APIC ID. */
221 PCPU_SET(apic_id, lapic_id());
222
223 /* Local APIC timer interrupt. */
224 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYSIGT, SEL_KPL, 0);
225 ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER;
226
227 /* XXX: error/thermal interrupts */
228 }
229
230 /*
231 * Create a local APIC instance.
232 */
233 void
234 lapic_create(u_int apic_id, int boot_cpu)
235 {
236 int i;
237
238 if (apic_id > MAX_APIC_ID) {
239 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
240 if (boot_cpu)
241 panic("Can't ignore BSP");
242 return;
243 }
244 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
245 apic_id));
246
247 /*
248 * Assume no local LVT overrides and a cluster of 0 and
249 * intra-cluster ID of 0.
250 */
251 lapics[apic_id].la_present = 1;
252 lapics[apic_id].la_id = apic_id;
253 for (i = 0; i < LVT_MAX; i++) {
254 lapics[apic_id].la_lvts[i] = lvts[i];
255 lapics[apic_id].la_lvts[i].lvt_active = 0;
256 }
257
258 #ifdef SMP
259 cpu_add(apic_id, boot_cpu);
260 #endif
261 }
262
263 /*
264 * Dump contents of local APIC registers
265 */
266 void
267 lapic_dump(const char* str)
268 {
269
270 printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
271 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n",
272 lapic->id, lapic->version, lapic->ldr, lapic->dfr);
273 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
274 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
275 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n",
276 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error,
277 lapic->lvt_pcint);
278 }
279
280 void
281 lapic_setup(int boot)
282 {
283 struct lapic *la;
284 u_int32_t maxlvt;
285 register_t eflags;
286 char buf[MAXCOMLEN + 1];
287
288 la = &lapics[lapic_id()];
289 KASSERT(la->la_present, ("missing APIC structure"));
290 eflags = intr_disable();
291 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
292
293 /* Initialize the TPR to allow all interrupts. */
294 lapic_set_tpr(0);
295
296 /* Setup spurious vector and enable the local APIC. */
297 lapic_enable();
298
299 /* Program LINT[01] LVT entries. */
300 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
301 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
302 /* Program the PMC LVT entry if present. */
303 if (maxlvt >= LVT_PMC)
304 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
305
306 /* Program timer LVT and setup handler. */
307 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer);
308 if (boot) {
309 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid));
310 intrcnt_add(buf, &la->la_timer_count);
311 }
312
313 /* We don't setup the timer during boot on the BSP until later. */
314 if (!(boot && PCPU_GET(cpuid) == 0)) {
315 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor",
316 lapic_id()));
317 lapic_timer_set_divisor(lapic_timer_divisor);
318 lapic_timer_periodic(lapic_timer_period);
319 lapic_timer_enable_intr();
320 }
321
322 /* XXX: Error and thermal LVTs */
323
324 if (cpu_vendor_id == CPU_VENDOR_AMD) {
325 /*
326 * Detect the presence of C1E capability mostly on latest
327 * dual-cores (or future) k8 family. This feature renders
328 * the local APIC timer dead, so we disable it by reading
329 * the Interrupt Pending Message register and clearing both
330 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
331 *
332 * Reference:
333 * "BIOS and Kernel Developer's Guide for AMD NPT
334 * Family 0Fh Processors"
335 * #32559 revision 3.00
336 */
337 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
338 (cpu_id & 0x0fff0000) >= 0x00040000) {
339 uint64_t msr;
340
341 msr = rdmsr(0xc0010055);
342 if (msr & 0x18000000)
343 wrmsr(0xc0010055, msr & ~0x18000000ULL);
344 }
345 }
346
347 intr_restore(eflags);
348 }
349
350 void
351 lapic_reenable_pmc(void)
352 {
353 #ifdef HWPMC_HOOKS
354 uint32_t value;
355
356 value = lapic->lvt_pcint;
357 value &= ~APIC_LVT_M;
358 lapic->lvt_pcint = value;
359 #endif
360 }
361
362 #ifdef HWPMC_HOOKS
363 static void
364 lapic_update_pmc(void *dummy)
365 {
366 struct lapic *la;
367
368 la = &lapics[lapic_id()];
369 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
370 }
371 #endif
372
373 int
374 lapic_enable_pmc(void)
375 {
376 #ifdef HWPMC_HOOKS
377 u_int32_t maxlvt;
378
379 /* Fail if the local APIC is not present. */
380 if (lapic == NULL)
381 return (0);
382
383 /* Fail if the PMC LVT is not present. */
384 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
385 if (maxlvt < LVT_PMC)
386 return (0);
387
388 lvts[LVT_PMC].lvt_masked = 0;
389
390 #ifdef SMP
391 /*
392 * If hwpmc was loaded at boot time then the APs may not be
393 * started yet. In that case, don't forward the request to
394 * them as they will program the lvt when they start.
395 */
396 if (smp_started)
397 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
398 else
399 #endif
400 lapic_update_pmc(NULL);
401 return (1);
402 #else
403 return (0);
404 #endif
405 }
406
407 void
408 lapic_disable_pmc(void)
409 {
410 #ifdef HWPMC_HOOKS
411 u_int32_t maxlvt;
412
413 /* Fail if the local APIC is not present. */
414 if (lapic == NULL)
415 return;
416
417 /* Fail if the PMC LVT is not present. */
418 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
419 if (maxlvt < LVT_PMC)
420 return;
421
422 lvts[LVT_PMC].lvt_masked = 1;
423
424 #ifdef SMP
425 /* The APs should always be started when hwpmc is unloaded. */
426 KASSERT(mp_ncpus == 1 || smp_started, ("hwpmc unloaded too early"));
427 #endif
428 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
429 #endif
430 }
431
432 /*
433 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so
434 * that it can drive hardclock, statclock, and profclock. This function
435 * returns true if it is able to use the local APIC timer to drive the
436 * clocks and false if it is not able.
437 */
438 int
439 lapic_setup_clock(void)
440 {
441 u_long value;
442
443 /* Can't drive the timer without a local APIC. */
444 if (lapic == NULL)
445 return (0);
446
447 /* Start off with a divisor of 2 (power on reset default). */
448 lapic_timer_divisor = 2;
449
450 /* Try to calibrate the local APIC timer. */
451 do {
452 lapic_timer_set_divisor(lapic_timer_divisor);
453 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
454 DELAY(2000000);
455 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
456 if (value != APIC_TIMER_MAX_COUNT)
457 break;
458 lapic_timer_divisor <<= 1;
459 } while (lapic_timer_divisor <= 128);
460 if (lapic_timer_divisor > 128)
461 panic("lapic: Divisor too big");
462 value /= 2;
463 if (bootverbose)
464 printf("lapic: Divisor %lu, Frequency %lu hz\n",
465 lapic_timer_divisor, value);
466
467 /*
468 * We want to run stathz in the neighborhood of 128hz. We would
469 * like profhz to run as often as possible, so we let it run on
470 * each clock tick. We try to honor the requested 'hz' value as
471 * much as possible.
472 *
473 * If 'hz' is above 1500, then we just let the lapic timer
474 * (and profhz) run at hz. If 'hz' is below 1500 but above
475 * 750, then we let the lapic timer run at 2 * 'hz'. If 'hz'
476 * is below 750 then we let the lapic timer run at 4 * 'hz'.
477 */
478 if (hz >= 1500)
479 lapic_timer_hz = hz;
480 else if (hz >= 750)
481 lapic_timer_hz = hz * 2;
482 else
483 lapic_timer_hz = hz * 4;
484 if (lapic_timer_hz < 128)
485 stathz = lapic_timer_hz;
486 else
487 stathz = lapic_timer_hz / (lapic_timer_hz / 128);
488 profhz = lapic_timer_hz;
489 lapic_timer_period = value / lapic_timer_hz;
490
491 /*
492 * Start up the timer on the BSP. The APs will kick off their
493 * timer during lapic_setup().
494 */
495 lapic_timer_periodic(lapic_timer_period);
496 lapic_timer_enable_intr();
497 return (1);
498 }
499
500 void
501 lapic_disable(void)
502 {
503 uint32_t value;
504
505 /* Software disable the local APIC. */
506 value = lapic->svr;
507 value &= ~APIC_SVR_SWEN;
508 lapic->svr = value;
509 }
510
511 static void
512 lapic_enable(void)
513 {
514 u_int32_t value;
515
516 /* Program the spurious vector to enable the local APIC. */
517 value = lapic->svr;
518 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
519 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
520 lapic->svr = value;
521 }
522
523 /* Reset the local APIC on the BSP during resume. */
524 static void
525 lapic_resume(struct pic *pic)
526 {
527
528 lapic_setup(0);
529 }
530
531 int
532 lapic_id(void)
533 {
534
535 KASSERT(lapic != NULL, ("local APIC is not mapped"));
536 return (lapic->id >> APIC_ID_SHIFT);
537 }
538
539 int
540 lapic_intr_pending(u_int vector)
541 {
542 volatile u_int32_t *irr;
543
544 /*
545 * The IRR registers are an array of 128-bit registers each of
546 * which only describes 32 interrupts in the low 32 bits.. Thus,
547 * we divide the vector by 32 to get the 128-bit index. We then
548 * multiply that index by 4 to get the equivalent index from
549 * treating the IRR as an array of 32-bit registers. Finally, we
550 * modulus the vector by 32 to determine the individual bit to
551 * test.
552 */
553 irr = &lapic->irr0;
554 return (irr[(vector / 32) * 4] & 1 << (vector % 32));
555 }
556
557 void
558 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
559 {
560 struct lapic *la;
561
562 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
563 __func__, apic_id));
564 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
565 __func__, cluster));
566 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
567 ("%s: intra cluster id %u too big", __func__, cluster_id));
568 la = &lapics[apic_id];
569 la->la_cluster = cluster;
570 la->la_cluster_id = cluster_id;
571 }
572
573 int
574 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
575 {
576
577 if (pin > LVT_MAX)
578 return (EINVAL);
579 if (apic_id == APIC_ID_ALL) {
580 lvts[pin].lvt_masked = masked;
581 if (bootverbose)
582 printf("lapic:");
583 } else {
584 KASSERT(lapics[apic_id].la_present,
585 ("%s: missing APIC %u", __func__, apic_id));
586 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
587 lapics[apic_id].la_lvts[pin].lvt_active = 1;
588 if (bootverbose)
589 printf("lapic%u:", apic_id);
590 }
591 if (bootverbose)
592 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
593 return (0);
594 }
595
596 int
597 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
598 {
599 struct lvt *lvt;
600
601 if (pin > LVT_MAX)
602 return (EINVAL);
603 if (apic_id == APIC_ID_ALL) {
604 lvt = &lvts[pin];
605 if (bootverbose)
606 printf("lapic:");
607 } else {
608 KASSERT(lapics[apic_id].la_present,
609 ("%s: missing APIC %u", __func__, apic_id));
610 lvt = &lapics[apic_id].la_lvts[pin];
611 lvt->lvt_active = 1;
612 if (bootverbose)
613 printf("lapic%u:", apic_id);
614 }
615 lvt->lvt_mode = mode;
616 switch (mode) {
617 case APIC_LVT_DM_NMI:
618 case APIC_LVT_DM_SMI:
619 case APIC_LVT_DM_INIT:
620 case APIC_LVT_DM_EXTINT:
621 lvt->lvt_edgetrigger = 1;
622 lvt->lvt_activehi = 1;
623 if (mode == APIC_LVT_DM_EXTINT)
624 lvt->lvt_masked = 1;
625 else
626 lvt->lvt_masked = 0;
627 break;
628 default:
629 panic("Unsupported delivery mode: 0x%x\n", mode);
630 }
631 if (bootverbose) {
632 printf(" Routing ");
633 switch (mode) {
634 case APIC_LVT_DM_NMI:
635 printf("NMI");
636 break;
637 case APIC_LVT_DM_SMI:
638 printf("SMI");
639 break;
640 case APIC_LVT_DM_INIT:
641 printf("INIT");
642 break;
643 case APIC_LVT_DM_EXTINT:
644 printf("ExtINT");
645 break;
646 }
647 printf(" -> LINT%u\n", pin);
648 }
649 return (0);
650 }
651
652 int
653 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
654 {
655
656 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM)
657 return (EINVAL);
658 if (apic_id == APIC_ID_ALL) {
659 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
660 if (bootverbose)
661 printf("lapic:");
662 } else {
663 KASSERT(lapics[apic_id].la_present,
664 ("%s: missing APIC %u", __func__, apic_id));
665 lapics[apic_id].la_lvts[pin].lvt_active = 1;
666 lapics[apic_id].la_lvts[pin].lvt_activehi =
667 (pol == INTR_POLARITY_HIGH);
668 if (bootverbose)
669 printf("lapic%u:", apic_id);
670 }
671 if (bootverbose)
672 printf(" LINT%u polarity: %s\n", pin,
673 pol == INTR_POLARITY_HIGH ? "high" : "low");
674 return (0);
675 }
676
677 int
678 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger)
679 {
680
681 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
682 return (EINVAL);
683 if (apic_id == APIC_ID_ALL) {
684 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
685 if (bootverbose)
686 printf("lapic:");
687 } else {
688 KASSERT(lapics[apic_id].la_present,
689 ("%s: missing APIC %u", __func__, apic_id));
690 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
691 (trigger == INTR_TRIGGER_EDGE);
692 lapics[apic_id].la_lvts[pin].lvt_active = 1;
693 if (bootverbose)
694 printf("lapic%u:", apic_id);
695 }
696 if (bootverbose)
697 printf(" LINT%u trigger: %s\n", pin,
698 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
699 return (0);
700 }
701
702 /*
703 * Adjust the TPR of the current CPU so that it blocks all interrupts below
704 * the passed in vector.
705 */
706 void
707 lapic_set_tpr(u_int vector)
708 {
709 #ifdef CHEAP_TPR
710 lapic->tpr = vector;
711 #else
712 u_int32_t tpr;
713
714 tpr = lapic->tpr & ~APIC_TPR_PRIO;
715 tpr |= vector;
716 lapic->tpr = tpr;
717 #endif
718 }
719
720 void
721 lapic_eoi(void)
722 {
723
724 lapic->eoi = 0;
725 }
726
727 void
728 lapic_handle_intr(int vector, struct trapframe *frame)
729 {
730 struct intsrc *isrc;
731
732 if (vector == -1)
733 panic("Couldn't get vector from ISR!");
734 isrc = intr_lookup_source(apic_idt_to_irq(vector));
735 intr_execute_handlers(isrc, frame);
736 }
737
738 void
739 lapic_handle_timer(struct trapframe *frame)
740 {
741 struct lapic *la;
742
743 /* Send EOI first thing. */
744 lapic_eoi();
745
746 #if defined(SMP) && !defined(SCHED_ULE)
747 /*
748 * Don't do any accounting for the disabled HTT cores, since it
749 * will provide misleading numbers for the userland.
750 *
751 * No locking is necessary here, since even if we loose the race
752 * when hlt_cpus_mask changes it is not a big deal, really.
753 *
754 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask
755 * and unlike other schedulers it actually schedules threads to
756 * those CPUs.
757 */
758 if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0)
759 return;
760 #endif
761
762 /* Look up our local APIC structure for the tick counters. */
763 la = &lapics[PCPU_GET(apic_id)];
764 (*la->la_timer_count)++;
765 critical_enter();
766
767 #ifdef KDTRACE_HOOKS
768 /*
769 * If the DTrace hooks are configured and a callback function
770 * has been registered, then call it to process the high speed
771 * timers.
772 */
773 int cpu = PCPU_GET(cpuid);
774 if (lapic_cyclic_clock_func[cpu] != NULL)
775 (*lapic_cyclic_clock_func[cpu])(frame);
776 #endif
777
778 /* Fire hardclock at hz. */
779 la->la_hard_ticks += hz;
780 if (la->la_hard_ticks >= lapic_timer_hz) {
781 la->la_hard_ticks -= lapic_timer_hz;
782 if (PCPU_GET(cpuid) == 0)
783 hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
784 else
785 hardclock_cpu(TRAPF_USERMODE(frame));
786 }
787
788 /* Fire statclock at stathz. */
789 la->la_stat_ticks += stathz;
790 if (la->la_stat_ticks >= lapic_timer_hz) {
791 la->la_stat_ticks -= lapic_timer_hz;
792 statclock(TRAPF_USERMODE(frame));
793 }
794
795 /* Fire profclock at profhz, but only when needed. */
796 la->la_prof_ticks += profhz;
797 if (la->la_prof_ticks >= lapic_timer_hz) {
798 la->la_prof_ticks -= lapic_timer_hz;
799 if (profprocs != 0)
800 profclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
801 }
802 critical_exit();
803 }
804
805 static void
806 lapic_timer_set_divisor(u_int divisor)
807 {
808
809 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor));
810 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) /
811 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor));
812 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1];
813 }
814
815 static void
816 lapic_timer_oneshot(u_int count)
817 {
818 u_int32_t value;
819
820 value = lapic->lvt_timer;
821 value &= ~APIC_LVTT_TM;
822 value |= APIC_LVTT_TM_ONE_SHOT;
823 lapic->lvt_timer = value;
824 lapic->icr_timer = count;
825 }
826
827 static void
828 lapic_timer_periodic(u_int count)
829 {
830 u_int32_t value;
831
832 value = lapic->lvt_timer;
833 value &= ~APIC_LVTT_TM;
834 value |= APIC_LVTT_TM_PERIODIC;
835 lapic->lvt_timer = value;
836 lapic->icr_timer = count;
837 }
838
839 static void
840 lapic_timer_enable_intr(void)
841 {
842 u_int32_t value;
843
844 value = lapic->lvt_timer;
845 value &= ~APIC_LVT_M;
846 lapic->lvt_timer = value;
847 }
848
849 /* Request a free IDT vector to be used by the specified IRQ. */
850 u_int
851 apic_alloc_vector(u_int irq)
852 {
853 u_int vector;
854
855 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
856
857 /*
858 * Search for a free vector. Currently we just use a very simple
859 * algorithm to find the first free vector.
860 */
861 mtx_lock_spin(&icu_lock);
862 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
863 if (ioint_irqs[vector] != 0)
864 continue;
865 ioint_irqs[vector] = irq;
866 mtx_unlock_spin(&icu_lock);
867 return (vector + APIC_IO_INTS);
868 }
869 mtx_unlock_spin(&icu_lock);
870 panic("Couldn't find an APIC vector for IRQ %u", irq);
871 }
872
873 /*
874 * Request 'count' free contiguous IDT vectors to be used by 'count'
875 * IRQs. 'count' must be a power of two and the vectors will be
876 * aligned on a boundary of 'align'. If the request cannot be
877 * satisfied, 0 is returned.
878 */
879 u_int
880 apic_alloc_vectors(u_int *irqs, u_int count, u_int align)
881 {
882 u_int first, run, vector;
883
884 KASSERT(powerof2(count), ("bad count"));
885 KASSERT(powerof2(align), ("bad align"));
886 KASSERT(align >= count, ("align < count"));
887 #ifdef INVARIANTS
888 for (run = 0; run < count; run++)
889 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u",
890 irqs[run], run));
891 #endif
892
893 /*
894 * Search for 'count' free vectors. As with apic_alloc_vector(),
895 * this just uses a simple first fit algorithm.
896 */
897 run = 0;
898 first = 0;
899 mtx_lock_spin(&icu_lock);
900 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
901
902 /* Vector is in use, end run. */
903 if (ioint_irqs[vector] != 0) {
904 run = 0;
905 first = 0;
906 continue;
907 }
908
909 /* Start a new run if run == 0 and vector is aligned. */
910 if (run == 0) {
911 if ((vector & (align - 1)) != 0)
912 continue;
913 first = vector;
914 }
915 run++;
916
917 /* Keep looping if the run isn't long enough yet. */
918 if (run < count)
919 continue;
920
921 /* Found a run, assign IRQs and return the first vector. */
922 for (vector = 0; vector < count; vector++)
923 ioint_irqs[first + vector] = irqs[vector];
924 mtx_unlock_spin(&icu_lock);
925 return (first + APIC_IO_INTS);
926 }
927 mtx_unlock_spin(&icu_lock);
928 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count);
929 return (0);
930 }
931
932 void
933 apic_enable_vector(u_int vector)
934 {
935
936 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
937 KASSERT(ioint_handlers[vector / 32] != NULL,
938 ("No ISR handler for vector %u", vector));
939 setidt(vector, ioint_handlers[vector / 32], SDT_SYSIGT, SEL_KPL, 0);
940 }
941
942 void
943 apic_disable_vector(u_int vector)
944 {
945
946 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
947 KASSERT(ioint_handlers[vector / 32] != NULL,
948 ("No ISR handler for vector %u", vector));
949 setidt(vector, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
950 }
951
952 /* Release an APIC vector when it's no longer in use. */
953 void
954 apic_free_vector(u_int vector, u_int irq)
955 {
956 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
957 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
958 ("Vector %u does not map to an IRQ line", vector));
959 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
960 KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch"));
961 mtx_lock_spin(&icu_lock);
962 ioint_irqs[vector - APIC_IO_INTS] = 0;
963 mtx_unlock_spin(&icu_lock);
964 }
965
966 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */
967 u_int
968 apic_idt_to_irq(u_int vector)
969 {
970
971 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
972 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
973 ("Vector %u does not map to an IRQ line", vector));
974 return (ioint_irqs[vector - APIC_IO_INTS]);
975 }
976
977 #ifdef DDB
978 /*
979 * Dump data about APIC IDT vector mappings.
980 */
981 DB_SHOW_COMMAND(apic, db_show_apic)
982 {
983 struct intsrc *isrc;
984 int i, verbose;
985 u_int irq;
986
987 if (strcmp(modif, "vv") == 0)
988 verbose = 2;
989 else if (strcmp(modif, "v") == 0)
990 verbose = 1;
991 else
992 verbose = 0;
993 for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) {
994 irq = ioint_irqs[i];
995 if (irq != 0 && irq != IRQ_SYSCALL) {
996 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS);
997 if (irq == IRQ_TIMER)
998 db_printf("lapic timer\n");
999 else if (irq < NUM_IO_INTS) {
1000 isrc = intr_lookup_source(irq);
1001 if (isrc == NULL || verbose == 0)
1002 db_printf("IRQ %u\n", irq);
1003 else
1004 db_dump_intr_event(isrc->is_event,
1005 verbose == 2);
1006 } else
1007 db_printf("IRQ %u ???\n", irq);
1008 }
1009 }
1010 }
1011
1012 static void
1013 dump_mask(const char *prefix, uint32_t v, int base)
1014 {
1015 int i, first;
1016
1017 first = 1;
1018 for (i = 0; i < 32; i++)
1019 if (v & (1 << i)) {
1020 if (first) {
1021 db_printf("%s:", prefix);
1022 first = 0;
1023 }
1024 db_printf(" %02x", base + i);
1025 }
1026 if (!first)
1027 db_printf("\n");
1028 }
1029
1030 /* Show info from the lapic regs for this CPU. */
1031 DB_SHOW_COMMAND(lapic, db_show_lapic)
1032 {
1033 uint32_t v;
1034
1035 db_printf("lapic ID = %d\n", lapic_id());
1036 v = lapic->version;
1037 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4,
1038 v & 0xf);
1039 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT);
1040 v = lapic->svr;
1041 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR,
1042 v & APIC_SVR_ENABLE ? "enabled" : "disabled");
1043 db_printf("TPR = %02x\n", lapic->tpr);
1044
1045 #define dump_field(prefix, index) \
1046 dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \
1047 index * 32)
1048
1049 db_printf("In-service Interrupts:\n");
1050 dump_field(isr, 0);
1051 dump_field(isr, 1);
1052 dump_field(isr, 2);
1053 dump_field(isr, 3);
1054 dump_field(isr, 4);
1055 dump_field(isr, 5);
1056 dump_field(isr, 6);
1057 dump_field(isr, 7);
1058
1059 db_printf("TMR Interrupts:\n");
1060 dump_field(tmr, 0);
1061 dump_field(tmr, 1);
1062 dump_field(tmr, 2);
1063 dump_field(tmr, 3);
1064 dump_field(tmr, 4);
1065 dump_field(tmr, 5);
1066 dump_field(tmr, 6);
1067 dump_field(tmr, 7);
1068
1069 db_printf("IRR Interrupts:\n");
1070 dump_field(irr, 0);
1071 dump_field(irr, 1);
1072 dump_field(irr, 2);
1073 dump_field(irr, 3);
1074 dump_field(irr, 4);
1075 dump_field(irr, 5);
1076 dump_field(irr, 6);
1077 dump_field(irr, 7);
1078
1079 #undef dump_field
1080 }
1081 #endif
1082
1083 /*
1084 * APIC probing support code. This includes code to manage enumerators.
1085 */
1086
1087 static SLIST_HEAD(, apic_enumerator) enumerators =
1088 SLIST_HEAD_INITIALIZER(enumerators);
1089 static struct apic_enumerator *best_enum;
1090
1091 void
1092 apic_register_enumerator(struct apic_enumerator *enumerator)
1093 {
1094 #ifdef INVARIANTS
1095 struct apic_enumerator *apic_enum;
1096
1097 SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
1098 if (apic_enum == enumerator)
1099 panic("%s: Duplicate register of %s", __func__,
1100 enumerator->apic_name);
1101 }
1102 #endif
1103 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
1104 }
1105
1106 /*
1107 * We have to look for CPU's very, very early because certain subsystems
1108 * want to know how many CPU's we have extremely early on in the boot
1109 * process.
1110 */
1111 static void
1112 apic_init(void *dummy __unused)
1113 {
1114 struct apic_enumerator *enumerator;
1115 int retval, best;
1116
1117 /* Don't probe if APIC mode is disabled. */
1118 if (resource_disabled("apic", 0))
1119 return;
1120
1121 /* First, probe all the enumerators to find the best match. */
1122 best_enum = NULL;
1123 best = 0;
1124 SLIST_FOREACH(enumerator, &enumerators, apic_next) {
1125 retval = enumerator->apic_probe();
1126 if (retval > 0)
1127 continue;
1128 if (best_enum == NULL || best < retval) {
1129 best_enum = enumerator;
1130 best = retval;
1131 }
1132 }
1133 if (best_enum == NULL) {
1134 if (bootverbose)
1135 printf("APIC: Could not find any APICs.\n");
1136 return;
1137 }
1138
1139 if (bootverbose)
1140 printf("APIC: Using the %s enumerator.\n",
1141 best_enum->apic_name);
1142
1143 /* Second, probe the CPU's in the system. */
1144 retval = best_enum->apic_probe_cpus();
1145 if (retval != 0)
1146 printf("%s: Failed to probe CPUs: returned %d\n",
1147 best_enum->apic_name, retval);
1148 }
1149 SYSINIT(apic_init, SI_SUB_TUNABLES - 1, SI_ORDER_SECOND, apic_init, NULL);
1150
1151 /*
1152 * Setup the local APIC. We have to do this prior to starting up the APs
1153 * in the SMP case.
1154 */
1155 static void
1156 apic_setup_local(void *dummy __unused)
1157 {
1158 int retval;
1159
1160 if (best_enum == NULL)
1161 return;
1162 retval = best_enum->apic_setup_local();
1163 if (retval != 0)
1164 printf("%s: Failed to setup the local APIC: returned %d\n",
1165 best_enum->apic_name, retval);
1166 }
1167 SYSINIT(apic_setup_local, SI_SUB_CPU, SI_ORDER_SECOND, apic_setup_local,
1168 NULL);
1169
1170 /*
1171 * Setup the I/O APICs.
1172 */
1173 static void
1174 apic_setup_io(void *dummy __unused)
1175 {
1176 int retval;
1177
1178 if (best_enum == NULL)
1179 return;
1180 retval = best_enum->apic_setup_io();
1181 if (retval != 0)
1182 printf("%s: Failed to setup I/O APICs: returned %d\n",
1183 best_enum->apic_name, retval);
1184
1185 /*
1186 * Finish setting up the local APIC on the BSP once we know how to
1187 * properly program the LINT pins.
1188 */
1189 lapic_setup(1);
1190 intr_register_pic(&lapic_pic);
1191 if (bootverbose)
1192 lapic_dump("BSP");
1193
1194 /* Enable the MSI "pic". */
1195 msi_init();
1196 }
1197 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL);
1198
1199 #ifdef SMP
1200 /*
1201 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are
1202 * private to the sys/amd64 code. The public interface for the rest of the
1203 * kernel is defined in mp_machdep.c.
1204 */
1205 int
1206 lapic_ipi_wait(int delay)
1207 {
1208 int x, incr;
1209
1210 /*
1211 * Wait delay loops for IPI to be sent. This is highly bogus
1212 * since this is sensitive to CPU clock speed. If delay is
1213 * -1, we wait forever.
1214 */
1215 if (delay == -1) {
1216 incr = 0;
1217 delay = 1;
1218 } else
1219 incr = 1;
1220 for (x = 0; x < delay; x += incr) {
1221 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE)
1222 return (1);
1223 ia32_pause();
1224 }
1225 return (0);
1226 }
1227
1228 void
1229 lapic_ipi_raw(register_t icrlo, u_int dest)
1230 {
1231 register_t value, eflags;
1232
1233 /* XXX: Need more sanity checking of icrlo? */
1234 KASSERT(lapic != NULL, ("%s called too early", __func__));
1235 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1236 ("%s: invalid dest field", __func__));
1237 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
1238 ("%s: reserved bits set in ICR LO register", __func__));
1239
1240 /* Set destination in ICR HI register if it is being used. */
1241 eflags = intr_disable();
1242 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
1243 value = lapic->icr_hi;
1244 value &= ~APIC_ID_MASK;
1245 value |= dest << APIC_ID_SHIFT;
1246 lapic->icr_hi = value;
1247 }
1248
1249 /* Program the contents of the IPI and dispatch it. */
1250 value = lapic->icr_lo;
1251 value &= APIC_ICRLO_RESV_MASK;
1252 value |= icrlo;
1253 lapic->icr_lo = value;
1254 intr_restore(eflags);
1255 }
1256
1257 #define BEFORE_SPIN 1000000
1258 #ifdef DETECT_DEADLOCK
1259 #define AFTER_SPIN 1000
1260 #endif
1261
1262 void
1263 lapic_ipi_vectored(u_int vector, int dest)
1264 {
1265 register_t icrlo, destfield;
1266
1267 KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
1268 ("%s: invalid vector %d", __func__, vector));
1269
1270 icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY |
1271 APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE;
1272 destfield = 0;
1273 switch (dest) {
1274 case APIC_IPI_DEST_SELF:
1275 icrlo |= APIC_DEST_SELF;
1276 break;
1277 case APIC_IPI_DEST_ALL:
1278 icrlo |= APIC_DEST_ALLISELF;
1279 break;
1280 case APIC_IPI_DEST_OTHERS:
1281 icrlo |= APIC_DEST_ALLESELF;
1282 break;
1283 default:
1284 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1285 ("%s: invalid destination 0x%x", __func__, dest));
1286 destfield = dest;
1287 }
1288
1289 /* Wait for an earlier IPI to finish. */
1290 if (!lapic_ipi_wait(BEFORE_SPIN)) {
1291 if (panicstr != NULL)
1292 return;
1293 else
1294 panic("APIC: Previous IPI is stuck");
1295 }
1296
1297 lapic_ipi_raw(icrlo, destfield);
1298
1299 #ifdef DETECT_DEADLOCK
1300 /* Wait for IPI to be delivered. */
1301 if (!lapic_ipi_wait(AFTER_SPIN)) {
1302 #ifdef needsattention
1303 /*
1304 * XXX FIXME:
1305 *
1306 * The above function waits for the message to actually be
1307 * delivered. It breaks out after an arbitrary timeout
1308 * since the message should eventually be delivered (at
1309 * least in theory) and that if it wasn't we would catch
1310 * the failure with the check above when the next IPI is
1311 * sent.
1312 *
1313 * We could skip this wait entirely, EXCEPT it probably
1314 * protects us from other routines that assume that the
1315 * message was delivered and acted upon when this function
1316 * returns.
1317 */
1318 printf("APIC: IPI might be stuck\n");
1319 #else /* !needsattention */
1320 /* Wait until mesage is sent without a timeout. */
1321 while (lapic->icr_lo & APIC_DELSTAT_PEND)
1322 ia32_pause();
1323 #endif /* needsattention */
1324 }
1325 #endif /* DETECT_DEADLOCK */
1326 }
1327 #endif /* SMP */
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