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sys/amd64/amd64/local_apic.c
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1 /*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * Copyright (c) 1996, by Steve Passe 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Local APIC support on Pentium and later processors. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include "opt_hwpmc_hooks.h" 38 #include "opt_kdtrace.h" 39 40 #include "opt_ddb.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/bus.h> 45 #include <sys/kernel.h> 46 #include <sys/lock.h> 47 #include <sys/mutex.h> 48 #include <sys/pcpu.h> 49 #include <sys/smp.h> 50 51 #include <vm/vm.h> 52 #include <vm/pmap.h> 53 54 #include <machine/apicreg.h> 55 #include <machine/cpu.h> 56 #include <machine/cputypes.h> 57 #include <machine/frame.h> 58 #include <machine/intr_machdep.h> 59 #include <machine/apicvar.h> 60 #include <machine/mca.h> 61 #include <machine/md_var.h> 62 #include <machine/smp.h> 63 #include <machine/specialreg.h> 64 65 #ifdef DDB 66 #include <sys/interrupt.h> 67 #include <ddb/ddb.h> 68 #endif 69 70 #ifdef KDTRACE_HOOKS 71 #include <sys/dtrace_bsd.h> 72 cyclic_clock_func_t lapic_cyclic_clock_func[MAXCPU]; 73 #endif 74 75 /* Sanity checks on IDT vectors. */ 76 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT); 77 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS); 78 CTASSERT(APIC_LOCAL_INTS == 240); 79 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT); 80 81 /* Magic IRQ values for the timer and syscalls. */ 82 #define IRQ_TIMER (NUM_IO_INTS + 1) 83 #define IRQ_SYSCALL (NUM_IO_INTS + 2) 84 85 /* 86 * Support for local APICs. Local APICs manage interrupts on each 87 * individual processor as opposed to I/O APICs which receive interrupts 88 * from I/O devices and then forward them on to the local APICs. 89 * 90 * Local APICs can also send interrupts to each other thus providing the 91 * mechanism for IPIs. 92 */ 93 94 struct lvt { 95 u_int lvt_edgetrigger:1; 96 u_int lvt_activehi:1; 97 u_int lvt_masked:1; 98 u_int lvt_active:1; 99 u_int lvt_mode:16; 100 u_int lvt_vector:8; 101 }; 102 103 struct lapic { 104 struct lvt la_lvts[LVT_MAX + 1]; 105 u_int la_id:8; 106 u_int la_cluster:4; 107 u_int la_cluster_id:2; 108 u_int la_present:1; 109 u_long *la_timer_count; 110 u_long la_hard_ticks; 111 u_long la_stat_ticks; 112 u_long la_prof_ticks; 113 } static lapics[MAX_APIC_ID + 1]; 114 115 /* Global defaults for local APIC LVT entries. */ 116 static struct lvt lvts[LVT_MAX + 1] = { 117 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */ 118 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */ 119 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */ 120 { 1, 1, 0, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */ 121 { 1, 1, 1, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */ 122 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */ 123 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_CMC_INT }, /* CMCI */ 124 }; 125 126 static inthand_t *ioint_handlers[] = { 127 NULL, /* 0 - 31 */ 128 IDTVEC(apic_isr1), /* 32 - 63 */ 129 IDTVEC(apic_isr2), /* 64 - 95 */ 130 IDTVEC(apic_isr3), /* 96 - 127 */ 131 IDTVEC(apic_isr4), /* 128 - 159 */ 132 IDTVEC(apic_isr5), /* 160 - 191 */ 133 IDTVEC(apic_isr6), /* 192 - 223 */ 134 IDTVEC(apic_isr7), /* 224 - 255 */ 135 }; 136 137 /* Include IDT_SYSCALL to make indexing easier. */ 138 static u_int ioint_irqs[APIC_NUM_IOINTS + 1]; 139 140 static u_int32_t lapic_timer_divisors[] = { 141 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16, 142 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128 143 }; 144 145 extern inthand_t IDTVEC(rsvd); 146 147 volatile lapic_t *lapic; 148 vm_paddr_t lapic_paddr; 149 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz; 150 151 static void lapic_enable(void); 152 static void lapic_resume(struct pic *pic); 153 static void lapic_timer_enable_intr(void); 154 static void lapic_timer_oneshot(u_int count); 155 static void lapic_timer_periodic(u_int count); 156 static void lapic_timer_set_divisor(u_int divisor); 157 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value); 158 159 struct pic lapic_pic = { .pic_resume = lapic_resume }; 160 161 static uint32_t 162 lvt_mode(struct lapic *la, u_int pin, uint32_t value) 163 { 164 struct lvt *lvt; 165 166 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin)); 167 if (la->la_lvts[pin].lvt_active) 168 lvt = &la->la_lvts[pin]; 169 else 170 lvt = &lvts[pin]; 171 172 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM | 173 APIC_LVT_VECTOR); 174 if (lvt->lvt_edgetrigger == 0) 175 value |= APIC_LVT_TM; 176 if (lvt->lvt_activehi == 0) 177 value |= APIC_LVT_IIPP_INTALO; 178 if (lvt->lvt_masked) 179 value |= APIC_LVT_M; 180 value |= lvt->lvt_mode; 181 switch (lvt->lvt_mode) { 182 case APIC_LVT_DM_NMI: 183 case APIC_LVT_DM_SMI: 184 case APIC_LVT_DM_INIT: 185 case APIC_LVT_DM_EXTINT: 186 if (!lvt->lvt_edgetrigger) { 187 printf("lapic%u: Forcing LINT%u to edge trigger\n", 188 la->la_id, pin); 189 value |= APIC_LVT_TM; 190 } 191 /* Use a vector of 0. */ 192 break; 193 case APIC_LVT_DM_FIXED: 194 value |= lvt->lvt_vector; 195 break; 196 default: 197 panic("bad APIC LVT delivery mode: %#x\n", value); 198 } 199 return (value); 200 } 201 202 /* 203 * Map the local APIC and setup necessary interrupt vectors. 204 */ 205 void 206 lapic_init(vm_paddr_t addr) 207 { 208 209 /* Map the local APIC and setup the spurious interrupt handler. */ 210 KASSERT(trunc_page(addr) == addr, 211 ("local APIC not aligned on a page boundary")); 212 lapic = pmap_mapdev(addr, sizeof(lapic_t)); 213 lapic_paddr = addr; 214 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 215 216 /* Perform basic initialization of the BSP's local APIC. */ 217 lapic_enable(); 218 ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL; 219 220 /* Set BSP's per-CPU local APIC ID. */ 221 PCPU_SET(apic_id, lapic_id()); 222 223 /* Local APIC timer interrupt. */ 224 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYSIGT, SEL_KPL, 0); 225 ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER; 226 227 /* Local APIC error interrupt. */ 228 setidt(APIC_ERROR_INT, IDTVEC(errorint), SDT_SYSIGT, SEL_KPL, 0); 229 230 /* XXX: Thermal interrupt */ 231 232 /* Local APIC CMCI. */ 233 setidt(APIC_CMC_INT, IDTVEC(cmcint), SDT_SYSIGT, SEL_KPL, 0); 234 } 235 236 /* 237 * Create a local APIC instance. 238 */ 239 void 240 lapic_create(u_int apic_id, int boot_cpu) 241 { 242 int i; 243 244 if (apic_id > MAX_APIC_ID) { 245 printf("APIC: Ignoring local APIC with ID %d\n", apic_id); 246 if (boot_cpu) 247 panic("Can't ignore BSP"); 248 return; 249 } 250 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u", 251 apic_id)); 252 253 /* 254 * Assume no local LVT overrides and a cluster of 0 and 255 * intra-cluster ID of 0. 256 */ 257 lapics[apic_id].la_present = 1; 258 lapics[apic_id].la_id = apic_id; 259 for (i = 0; i <= LVT_MAX; i++) { 260 lapics[apic_id].la_lvts[i] = lvts[i]; 261 lapics[apic_id].la_lvts[i].lvt_active = 0; 262 } 263 264 #ifdef SMP 265 cpu_add(apic_id, boot_cpu); 266 #endif 267 } 268 269 /* 270 * Dump contents of local APIC registers 271 */ 272 void 273 lapic_dump(const char* str) 274 { 275 uint32_t maxlvt; 276 277 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 278 printf("cpu%d %s:\n", PCPU_GET(cpuid), str); 279 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n", 280 lapic->id, lapic->version, lapic->ldr, lapic->dfr); 281 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n", 282 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr); 283 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x", 284 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error); 285 if (maxlvt >= LVT_PMC) 286 printf(" pmc: 0x%08x", lapic->lvt_pcint); 287 printf("\n"); 288 if (maxlvt >= LVT_CMCI) 289 printf(" cmci: 0x%08x\n", lapic->lvt_cmci); 290 } 291 292 void 293 lapic_setup(int boot) 294 { 295 struct lapic *la; 296 u_int32_t maxlvt; 297 register_t eflags; 298 char buf[MAXCOMLEN + 1]; 299 300 la = &lapics[lapic_id()]; 301 KASSERT(la->la_present, ("missing APIC structure")); 302 eflags = intr_disable(); 303 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 304 305 /* Initialize the TPR to allow all interrupts. */ 306 lapic_set_tpr(0); 307 308 /* Setup spurious vector and enable the local APIC. */ 309 lapic_enable(); 310 311 /* Program LINT[01] LVT entries. */ 312 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0); 313 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1); 314 315 /* Program the PMC LVT entry if present. */ 316 if (maxlvt >= LVT_PMC) 317 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 318 319 /* Program timer LVT and setup handler. */ 320 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer); 321 if (boot) { 322 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid)); 323 intrcnt_add(buf, &la->la_timer_count); 324 } 325 326 /* We don't setup the timer during boot on the BSP until later. */ 327 if (!(boot && PCPU_GET(cpuid) == 0)) { 328 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor", 329 lapic_id())); 330 lapic_timer_set_divisor(lapic_timer_divisor); 331 lapic_timer_periodic(lapic_timer_period); 332 lapic_timer_enable_intr(); 333 } 334 335 /* Program error LVT and clear any existing errors. */ 336 lapic->lvt_error = lvt_mode(la, LVT_ERROR, lapic->lvt_error); 337 lapic->esr = 0; 338 339 /* XXX: Thermal LVT */ 340 341 if (cpu_vendor_id == CPU_VENDOR_AMD) { 342 /* 343 * Detect the presence of C1E capability mostly on latest 344 * dual-cores (or future) k8 family. This feature renders 345 * the local APIC timer dead, so we disable it by reading 346 * the Interrupt Pending Message register and clearing both 347 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 348 * 349 * Reference: 350 * "BIOS and Kernel Developer's Guide for AMD NPT 351 * Family 0Fh Processors" 352 * #32559 revision 3.00 353 */ 354 if ((cpu_id & 0x00000f00) == 0x00000f00 && 355 (cpu_id & 0x0fff0000) >= 0x00040000) { 356 uint64_t msr; 357 358 msr = rdmsr(0xc0010055); 359 if (msr & 0x18000000) 360 wrmsr(0xc0010055, msr & ~0x18000000ULL); 361 } 362 } 363 364 /* Program the CMCI LVT entry if present. */ 365 if (maxlvt >= LVT_CMCI) 366 lapic->lvt_cmci = lvt_mode(la, LVT_CMCI, lapic->lvt_cmci); 367 368 intr_restore(eflags); 369 } 370 371 void 372 lapic_reenable_pmc(void) 373 { 374 #ifdef HWPMC_HOOKS 375 uint32_t value; 376 377 value = lapic->lvt_pcint; 378 value &= ~APIC_LVT_M; 379 lapic->lvt_pcint = value; 380 #endif 381 } 382 383 #ifdef HWPMC_HOOKS 384 static void 385 lapic_update_pmc(void *dummy) 386 { 387 struct lapic *la; 388 389 la = &lapics[lapic_id()]; 390 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 391 } 392 #endif 393 394 int 395 lapic_enable_pmc(void) 396 { 397 #ifdef HWPMC_HOOKS 398 u_int32_t maxlvt; 399 400 /* Fail if the local APIC is not present. */ 401 if (lapic == NULL) 402 return (0); 403 404 /* Fail if the PMC LVT is not present. */ 405 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 406 if (maxlvt < LVT_PMC) 407 return (0); 408 409 lvts[LVT_PMC].lvt_masked = 0; 410 411 #ifdef SMP 412 /* 413 * If hwpmc was loaded at boot time then the APs may not be 414 * started yet. In that case, don't forward the request to 415 * them as they will program the lvt when they start. 416 */ 417 if (smp_started) 418 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL); 419 else 420 #endif 421 lapic_update_pmc(NULL); 422 return (1); 423 #else 424 return (0); 425 #endif 426 } 427 428 void 429 lapic_disable_pmc(void) 430 { 431 #ifdef HWPMC_HOOKS 432 u_int32_t maxlvt; 433 434 /* Fail if the local APIC is not present. */ 435 if (lapic == NULL) 436 return; 437 438 /* Fail if the PMC LVT is not present. */ 439 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 440 if (maxlvt < LVT_PMC) 441 return; 442 443 lvts[LVT_PMC].lvt_masked = 1; 444 445 #ifdef SMP 446 /* The APs should always be started when hwpmc is unloaded. */ 447 KASSERT(mp_ncpus == 1 || smp_started, ("hwpmc unloaded too early")); 448 #endif 449 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL); 450 #endif 451 } 452 453 /* 454 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so 455 * that it can drive hardclock, statclock, and profclock. This function 456 * returns true if it is able to use the local APIC timer to drive the 457 * clocks and false if it is not able. 458 */ 459 int 460 lapic_setup_clock(void) 461 { 462 u_long value; 463 464 /* Can't drive the timer without a local APIC. */ 465 if (lapic == NULL) 466 return (0); 467 468 /* Start off with a divisor of 2 (power on reset default). */ 469 lapic_timer_divisor = 2; 470 471 /* Try to calibrate the local APIC timer. */ 472 do { 473 lapic_timer_set_divisor(lapic_timer_divisor); 474 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT); 475 DELAY(2000000); 476 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer; 477 if (value != APIC_TIMER_MAX_COUNT) 478 break; 479 lapic_timer_divisor <<= 1; 480 } while (lapic_timer_divisor <= 128); 481 if (lapic_timer_divisor > 128) 482 panic("lapic: Divisor too big"); 483 value /= 2; 484 if (bootverbose) 485 printf("lapic: Divisor %lu, Frequency %lu Hz\n", 486 lapic_timer_divisor, value); 487 488 /* 489 * We want to run stathz in the neighborhood of 128hz. We would 490 * like profhz to run as often as possible, so we let it run on 491 * each clock tick. We try to honor the requested 'hz' value as 492 * much as possible. 493 * 494 * If 'hz' is above 1500, then we just let the lapic timer 495 * (and profhz) run at hz. If 'hz' is below 1500 but above 496 * 750, then we let the lapic timer run at 2 * 'hz'. If 'hz' 497 * is below 750 then we let the lapic timer run at 4 * 'hz'. 498 */ 499 if (hz >= 1500) 500 lapic_timer_hz = hz; 501 else if (hz >= 750) 502 lapic_timer_hz = hz * 2; 503 else 504 lapic_timer_hz = hz * 4; 505 if (lapic_timer_hz < 128) 506 stathz = lapic_timer_hz; 507 else 508 stathz = lapic_timer_hz / (lapic_timer_hz / 128); 509 profhz = lapic_timer_hz; 510 lapic_timer_period = value / lapic_timer_hz; 511 512 /* 513 * Start up the timer on the BSP. The APs will kick off their 514 * timer during lapic_setup(). 515 */ 516 lapic_timer_periodic(lapic_timer_period); 517 lapic_timer_enable_intr(); 518 return (1); 519 } 520 521 void 522 lapic_disable(void) 523 { 524 uint32_t value; 525 526 /* Software disable the local APIC. */ 527 value = lapic->svr; 528 value &= ~APIC_SVR_SWEN; 529 lapic->svr = value; 530 } 531 532 static void 533 lapic_enable(void) 534 { 535 u_int32_t value; 536 537 /* Program the spurious vector to enable the local APIC. */ 538 value = lapic->svr; 539 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS); 540 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT); 541 lapic->svr = value; 542 } 543 544 /* Reset the local APIC on the BSP during resume. */ 545 static void 546 lapic_resume(struct pic *pic) 547 { 548 549 lapic_setup(0); 550 } 551 552 int 553 lapic_id(void) 554 { 555 556 KASSERT(lapic != NULL, ("local APIC is not mapped")); 557 return (lapic->id >> APIC_ID_SHIFT); 558 } 559 560 int 561 lapic_intr_pending(u_int vector) 562 { 563 volatile u_int32_t *irr; 564 565 /* 566 * The IRR registers are an array of 128-bit registers each of 567 * which only describes 32 interrupts in the low 32 bits.. Thus, 568 * we divide the vector by 32 to get the 128-bit index. We then 569 * multiply that index by 4 to get the equivalent index from 570 * treating the IRR as an array of 32-bit registers. Finally, we 571 * modulus the vector by 32 to determine the individual bit to 572 * test. 573 */ 574 irr = &lapic->irr0; 575 return (irr[(vector / 32) * 4] & 1 << (vector % 32)); 576 } 577 578 void 579 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 580 { 581 struct lapic *la; 582 583 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist", 584 __func__, apic_id)); 585 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big", 586 __func__, cluster)); 587 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID, 588 ("%s: intra cluster id %u too big", __func__, cluster_id)); 589 la = &lapics[apic_id]; 590 la->la_cluster = cluster; 591 la->la_cluster_id = cluster_id; 592 } 593 594 int 595 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked) 596 { 597 598 if (pin > LVT_MAX) 599 return (EINVAL); 600 if (apic_id == APIC_ID_ALL) { 601 lvts[pin].lvt_masked = masked; 602 if (bootverbose) 603 printf("lapic:"); 604 } else { 605 KASSERT(lapics[apic_id].la_present, 606 ("%s: missing APIC %u", __func__, apic_id)); 607 lapics[apic_id].la_lvts[pin].lvt_masked = masked; 608 lapics[apic_id].la_lvts[pin].lvt_active = 1; 609 if (bootverbose) 610 printf("lapic%u:", apic_id); 611 } 612 if (bootverbose) 613 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked"); 614 return (0); 615 } 616 617 int 618 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode) 619 { 620 struct lvt *lvt; 621 622 if (pin > LVT_MAX) 623 return (EINVAL); 624 if (apic_id == APIC_ID_ALL) { 625 lvt = &lvts[pin]; 626 if (bootverbose) 627 printf("lapic:"); 628 } else { 629 KASSERT(lapics[apic_id].la_present, 630 ("%s: missing APIC %u", __func__, apic_id)); 631 lvt = &lapics[apic_id].la_lvts[pin]; 632 lvt->lvt_active = 1; 633 if (bootverbose) 634 printf("lapic%u:", apic_id); 635 } 636 lvt->lvt_mode = mode; 637 switch (mode) { 638 case APIC_LVT_DM_NMI: 639 case APIC_LVT_DM_SMI: 640 case APIC_LVT_DM_INIT: 641 case APIC_LVT_DM_EXTINT: 642 lvt->lvt_edgetrigger = 1; 643 lvt->lvt_activehi = 1; 644 if (mode == APIC_LVT_DM_EXTINT) 645 lvt->lvt_masked = 1; 646 else 647 lvt->lvt_masked = 0; 648 break; 649 default: 650 panic("Unsupported delivery mode: 0x%x\n", mode); 651 } 652 if (bootverbose) { 653 printf(" Routing "); 654 switch (mode) { 655 case APIC_LVT_DM_NMI: 656 printf("NMI"); 657 break; 658 case APIC_LVT_DM_SMI: 659 printf("SMI"); 660 break; 661 case APIC_LVT_DM_INIT: 662 printf("INIT"); 663 break; 664 case APIC_LVT_DM_EXTINT: 665 printf("ExtINT"); 666 break; 667 } 668 printf(" -> LINT%u\n", pin); 669 } 670 return (0); 671 } 672 673 int 674 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol) 675 { 676 677 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM) 678 return (EINVAL); 679 if (apic_id == APIC_ID_ALL) { 680 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH); 681 if (bootverbose) 682 printf("lapic:"); 683 } else { 684 KASSERT(lapics[apic_id].la_present, 685 ("%s: missing APIC %u", __func__, apic_id)); 686 lapics[apic_id].la_lvts[pin].lvt_active = 1; 687 lapics[apic_id].la_lvts[pin].lvt_activehi = 688 (pol == INTR_POLARITY_HIGH); 689 if (bootverbose) 690 printf("lapic%u:", apic_id); 691 } 692 if (bootverbose) 693 printf(" LINT%u polarity: %s\n", pin, 694 pol == INTR_POLARITY_HIGH ? "high" : "low"); 695 return (0); 696 } 697 698 int 699 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger) 700 { 701 702 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM) 703 return (EINVAL); 704 if (apic_id == APIC_ID_ALL) { 705 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE); 706 if (bootverbose) 707 printf("lapic:"); 708 } else { 709 KASSERT(lapics[apic_id].la_present, 710 ("%s: missing APIC %u", __func__, apic_id)); 711 lapics[apic_id].la_lvts[pin].lvt_edgetrigger = 712 (trigger == INTR_TRIGGER_EDGE); 713 lapics[apic_id].la_lvts[pin].lvt_active = 1; 714 if (bootverbose) 715 printf("lapic%u:", apic_id); 716 } 717 if (bootverbose) 718 printf(" LINT%u trigger: %s\n", pin, 719 trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 720 return (0); 721 } 722 723 /* 724 * Adjust the TPR of the current CPU so that it blocks all interrupts below 725 * the passed in vector. 726 */ 727 void 728 lapic_set_tpr(u_int vector) 729 { 730 #ifdef CHEAP_TPR 731 lapic->tpr = vector; 732 #else 733 u_int32_t tpr; 734 735 tpr = lapic->tpr & ~APIC_TPR_PRIO; 736 tpr |= vector; 737 lapic->tpr = tpr; 738 #endif 739 } 740 741 void 742 lapic_eoi(void) 743 { 744 745 lapic->eoi = 0; 746 } 747 748 void 749 lapic_handle_intr(int vector, struct trapframe *frame) 750 { 751 struct intsrc *isrc; 752 753 if (vector == -1) 754 panic("Couldn't get vector from ISR!"); 755 isrc = intr_lookup_source(apic_idt_to_irq(vector)); 756 intr_execute_handlers(isrc, frame); 757 } 758 759 void 760 lapic_handle_timer(struct trapframe *frame) 761 { 762 struct lapic *la; 763 764 /* Send EOI first thing. */ 765 lapic_eoi(); 766 767 #if defined(SMP) && !defined(SCHED_ULE) 768 /* 769 * Don't do any accounting for the disabled HTT cores, since it 770 * will provide misleading numbers for the userland. 771 * 772 * No locking is necessary here, since even if we loose the race 773 * when hlt_cpus_mask changes it is not a big deal, really. 774 * 775 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask 776 * and unlike other schedulers it actually schedules threads to 777 * those CPUs. 778 */ 779 if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0) 780 return; 781 #endif 782 783 /* Look up our local APIC structure for the tick counters. */ 784 la = &lapics[PCPU_GET(apic_id)]; 785 (*la->la_timer_count)++; 786 critical_enter(); 787 788 #ifdef KDTRACE_HOOKS 789 /* 790 * If the DTrace hooks are configured and a callback function 791 * has been registered, then call it to process the high speed 792 * timers. 793 */ 794 int cpu = PCPU_GET(cpuid); 795 if (lapic_cyclic_clock_func[cpu] != NULL) 796 (*lapic_cyclic_clock_func[cpu])(frame); 797 #endif 798 799 /* Fire hardclock at hz. */ 800 la->la_hard_ticks += hz; 801 if (la->la_hard_ticks >= lapic_timer_hz) { 802 la->la_hard_ticks -= lapic_timer_hz; 803 if (PCPU_GET(cpuid) == 0) 804 hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); 805 else 806 hardclock_cpu(TRAPF_USERMODE(frame)); 807 } 808 809 /* Fire statclock at stathz. */ 810 la->la_stat_ticks += stathz; 811 if (la->la_stat_ticks >= lapic_timer_hz) { 812 la->la_stat_ticks -= lapic_timer_hz; 813 statclock(TRAPF_USERMODE(frame)); 814 } 815 816 /* Fire profclock at profhz, but only when needed. */ 817 la->la_prof_ticks += profhz; 818 if (la->la_prof_ticks >= lapic_timer_hz) { 819 la->la_prof_ticks -= lapic_timer_hz; 820 if (profprocs != 0) 821 profclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); 822 } 823 critical_exit(); 824 } 825 826 static void 827 lapic_timer_set_divisor(u_int divisor) 828 { 829 830 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor)); 831 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) / 832 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor)); 833 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1]; 834 } 835 836 static void 837 lapic_timer_oneshot(u_int count) 838 { 839 u_int32_t value; 840 841 value = lapic->lvt_timer; 842 value &= ~APIC_LVTT_TM; 843 value |= APIC_LVTT_TM_ONE_SHOT; 844 lapic->lvt_timer = value; 845 lapic->icr_timer = count; 846 } 847 848 static void 849 lapic_timer_periodic(u_int count) 850 { 851 u_int32_t value; 852 853 value = lapic->lvt_timer; 854 value &= ~APIC_LVTT_TM; 855 value |= APIC_LVTT_TM_PERIODIC; 856 lapic->lvt_timer = value; 857 lapic->icr_timer = count; 858 } 859 860 static void 861 lapic_timer_enable_intr(void) 862 { 863 u_int32_t value; 864 865 value = lapic->lvt_timer; 866 value &= ~APIC_LVT_M; 867 lapic->lvt_timer = value; 868 } 869 870 void 871 lapic_handle_cmc(void) 872 { 873 874 lapic_eoi(); 875 cmc_intr(); 876 } 877 878 /* 879 * Called from the mca_init() to activate the CMC interrupt if this CPU is 880 * responsible for monitoring any MC banks for CMC events. Since mca_init() 881 * is called prior to lapic_setup() during boot, this just needs to unmask 882 * this CPU's LVT_CMCI entry. 883 */ 884 void 885 lapic_enable_cmc(void) 886 { 887 u_int apic_id; 888 889 apic_id = PCPU_GET(apic_id); 890 KASSERT(lapics[apic_id].la_present, 891 ("%s: missing APIC %u", __func__, apic_id)); 892 lapics[apic_id].la_lvts[LVT_CMCI].lvt_masked = 0; 893 lapics[apic_id].la_lvts[LVT_CMCI].lvt_active = 1; 894 if (bootverbose) 895 printf("lapic%u: CMCI unmasked\n", apic_id); 896 } 897 898 void 899 lapic_handle_error(void) 900 { 901 u_int32_t esr; 902 903 /* 904 * Read the contents of the error status register. Write to 905 * the register first before reading from it to force the APIC 906 * to update its value to indicate any errors that have 907 * occurred since the previous write to the register. 908 */ 909 lapic->esr = 0; 910 esr = lapic->esr; 911 912 printf("CPU%d: local APIC error 0x%x\n", PCPU_GET(cpuid), esr); 913 lapic_eoi(); 914 } 915 916 /* Request a free IDT vector to be used by the specified IRQ. */ 917 u_int 918 apic_alloc_vector(u_int irq) 919 { 920 u_int vector; 921 922 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 923 924 /* 925 * Search for a free vector. Currently we just use a very simple 926 * algorithm to find the first free vector. 927 */ 928 mtx_lock_spin(&icu_lock); 929 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 930 if (ioint_irqs[vector] != 0) 931 continue; 932 ioint_irqs[vector] = irq; 933 mtx_unlock_spin(&icu_lock); 934 return (vector + APIC_IO_INTS); 935 } 936 mtx_unlock_spin(&icu_lock); 937 panic("Couldn't find an APIC vector for IRQ %u", irq); 938 } 939 940 /* 941 * Request 'count' free contiguous IDT vectors to be used by 'count' 942 * IRQs. 'count' must be a power of two and the vectors will be 943 * aligned on a boundary of 'align'. If the request cannot be 944 * satisfied, 0 is returned. 945 */ 946 u_int 947 apic_alloc_vectors(u_int *irqs, u_int count, u_int align) 948 { 949 u_int first, run, vector; 950 951 KASSERT(powerof2(count), ("bad count")); 952 KASSERT(powerof2(align), ("bad align")); 953 KASSERT(align >= count, ("align < count")); 954 #ifdef INVARIANTS 955 for (run = 0; run < count; run++) 956 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u", 957 irqs[run], run)); 958 #endif 959 960 /* 961 * Search for 'count' free vectors. As with apic_alloc_vector(), 962 * this just uses a simple first fit algorithm. 963 */ 964 run = 0; 965 first = 0; 966 mtx_lock_spin(&icu_lock); 967 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 968 969 /* Vector is in use, end run. */ 970 if (ioint_irqs[vector] != 0) { 971 run = 0; 972 first = 0; 973 continue; 974 } 975 976 /* Start a new run if run == 0 and vector is aligned. */ 977 if (run == 0) { 978 if ((vector & (align - 1)) != 0) 979 continue; 980 first = vector; 981 } 982 run++; 983 984 /* Keep looping if the run isn't long enough yet. */ 985 if (run < count) 986 continue; 987 988 /* Found a run, assign IRQs and return the first vector. */ 989 for (vector = 0; vector < count; vector++) 990 ioint_irqs[first + vector] = irqs[vector]; 991 mtx_unlock_spin(&icu_lock); 992 return (first + APIC_IO_INTS); 993 } 994 mtx_unlock_spin(&icu_lock); 995 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count); 996 return (0); 997 } 998 999 void 1000 apic_enable_vector(u_int vector) 1001 { 1002 1003 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 1004 KASSERT(ioint_handlers[vector / 32] != NULL, 1005 ("No ISR handler for vector %u", vector)); 1006 setidt(vector, ioint_handlers[vector / 32], SDT_SYSIGT, SEL_KPL, 0); 1007 } 1008 1009 void 1010 apic_disable_vector(u_int vector) 1011 { 1012 1013 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 1014 KASSERT(ioint_handlers[vector / 32] != NULL, 1015 ("No ISR handler for vector %u", vector)); 1016 setidt(vector, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 1017 } 1018 1019 /* Release an APIC vector when it's no longer in use. */ 1020 void 1021 apic_free_vector(u_int vector, u_int irq) 1022 { 1023 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 1024 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 1025 ("Vector %u does not map to an IRQ line", vector)); 1026 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 1027 KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch")); 1028 mtx_lock_spin(&icu_lock); 1029 ioint_irqs[vector - APIC_IO_INTS] = 0; 1030 mtx_unlock_spin(&icu_lock); 1031 } 1032 1033 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */ 1034 u_int 1035 apic_idt_to_irq(u_int vector) 1036 { 1037 1038 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 1039 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 1040 ("Vector %u does not map to an IRQ line", vector)); 1041 return (ioint_irqs[vector - APIC_IO_INTS]); 1042 } 1043 1044 #ifdef DDB 1045 /* 1046 * Dump data about APIC IDT vector mappings. 1047 */ 1048 DB_SHOW_COMMAND(apic, db_show_apic) 1049 { 1050 struct intsrc *isrc; 1051 int i, verbose; 1052 u_int irq; 1053 1054 if (strcmp(modif, "vv") == 0) 1055 verbose = 2; 1056 else if (strcmp(modif, "v") == 0) 1057 verbose = 1; 1058 else 1059 verbose = 0; 1060 for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) { 1061 irq = ioint_irqs[i]; 1062 if (irq != 0 && irq != IRQ_SYSCALL) { 1063 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS); 1064 if (irq == IRQ_TIMER) 1065 db_printf("lapic timer\n"); 1066 else if (irq < NUM_IO_INTS) { 1067 isrc = intr_lookup_source(irq); 1068 if (isrc == NULL || verbose == 0) 1069 db_printf("IRQ %u\n", irq); 1070 else 1071 db_dump_intr_event(isrc->is_event, 1072 verbose == 2); 1073 } else 1074 db_printf("IRQ %u ???\n", irq); 1075 } 1076 } 1077 } 1078 1079 static void 1080 dump_mask(const char *prefix, uint32_t v, int base) 1081 { 1082 int i, first; 1083 1084 first = 1; 1085 for (i = 0; i < 32; i++) 1086 if (v & (1 << i)) { 1087 if (first) { 1088 db_printf("%s:", prefix); 1089 first = 0; 1090 } 1091 db_printf(" %02x", base + i); 1092 } 1093 if (!first) 1094 db_printf("\n"); 1095 } 1096 1097 /* Show info from the lapic regs for this CPU. */ 1098 DB_SHOW_COMMAND(lapic, db_show_lapic) 1099 { 1100 uint32_t v; 1101 1102 db_printf("lapic ID = %d\n", lapic_id()); 1103 v = lapic->version; 1104 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4, 1105 v & 0xf); 1106 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT); 1107 v = lapic->svr; 1108 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR, 1109 v & APIC_SVR_ENABLE ? "enabled" : "disabled"); 1110 db_printf("TPR = %02x\n", lapic->tpr); 1111 1112 #define dump_field(prefix, index) \ 1113 dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \ 1114 index * 32) 1115 1116 db_printf("In-service Interrupts:\n"); 1117 dump_field(isr, 0); 1118 dump_field(isr, 1); 1119 dump_field(isr, 2); 1120 dump_field(isr, 3); 1121 dump_field(isr, 4); 1122 dump_field(isr, 5); 1123 dump_field(isr, 6); 1124 dump_field(isr, 7); 1125 1126 db_printf("TMR Interrupts:\n"); 1127 dump_field(tmr, 0); 1128 dump_field(tmr, 1); 1129 dump_field(tmr, 2); 1130 dump_field(tmr, 3); 1131 dump_field(tmr, 4); 1132 dump_field(tmr, 5); 1133 dump_field(tmr, 6); 1134 dump_field(tmr, 7); 1135 1136 db_printf("IRR Interrupts:\n"); 1137 dump_field(irr, 0); 1138 dump_field(irr, 1); 1139 dump_field(irr, 2); 1140 dump_field(irr, 3); 1141 dump_field(irr, 4); 1142 dump_field(irr, 5); 1143 dump_field(irr, 6); 1144 dump_field(irr, 7); 1145 1146 #undef dump_field 1147 } 1148 #endif 1149 1150 /* 1151 * APIC probing support code. This includes code to manage enumerators. 1152 */ 1153 1154 static SLIST_HEAD(, apic_enumerator) enumerators = 1155 SLIST_HEAD_INITIALIZER(enumerators); 1156 static struct apic_enumerator *best_enum; 1157 1158 void 1159 apic_register_enumerator(struct apic_enumerator *enumerator) 1160 { 1161 #ifdef INVARIANTS 1162 struct apic_enumerator *apic_enum; 1163 1164 SLIST_FOREACH(apic_enum, &enumerators, apic_next) { 1165 if (apic_enum == enumerator) 1166 panic("%s: Duplicate register of %s", __func__, 1167 enumerator->apic_name); 1168 } 1169 #endif 1170 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next); 1171 } 1172 1173 /* 1174 * We have to look for CPU's very, very early because certain subsystems 1175 * want to know how many CPU's we have extremely early on in the boot 1176 * process. 1177 */ 1178 static void 1179 apic_init(void *dummy __unused) 1180 { 1181 struct apic_enumerator *enumerator; 1182 int retval, best; 1183 1184 /* Don't probe if APIC mode is disabled. */ 1185 if (resource_disabled("apic", 0)) 1186 return; 1187 1188 /* First, probe all the enumerators to find the best match. */ 1189 best_enum = NULL; 1190 best = 0; 1191 SLIST_FOREACH(enumerator, &enumerators, apic_next) { 1192 retval = enumerator->apic_probe(); 1193 if (retval > 0) 1194 continue; 1195 if (best_enum == NULL || best < retval) { 1196 best_enum = enumerator; 1197 best = retval; 1198 } 1199 } 1200 if (best_enum == NULL) { 1201 if (bootverbose) 1202 printf("APIC: Could not find any APICs.\n"); 1203 return; 1204 } 1205 1206 if (bootverbose) 1207 printf("APIC: Using the %s enumerator.\n", 1208 best_enum->apic_name); 1209 1210 /* Second, probe the CPU's in the system. */ 1211 retval = best_enum->apic_probe_cpus(); 1212 if (retval != 0) 1213 printf("%s: Failed to probe CPUs: returned %d\n", 1214 best_enum->apic_name, retval); 1215 } 1216 SYSINIT(apic_init, SI_SUB_TUNABLES - 1, SI_ORDER_SECOND, apic_init, NULL); 1217 1218 /* 1219 * Setup the local APIC. We have to do this prior to starting up the APs 1220 * in the SMP case. 1221 */ 1222 static void 1223 apic_setup_local(void *dummy __unused) 1224 { 1225 int retval; 1226 1227 if (best_enum == NULL) 1228 return; 1229 retval = best_enum->apic_setup_local(); 1230 if (retval != 0) 1231 printf("%s: Failed to setup the local APIC: returned %d\n", 1232 best_enum->apic_name, retval); 1233 } 1234 SYSINIT(apic_setup_local, SI_SUB_CPU, SI_ORDER_SECOND, apic_setup_local, 1235 NULL); 1236 1237 /* 1238 * Setup the I/O APICs. 1239 */ 1240 static void 1241 apic_setup_io(void *dummy __unused) 1242 { 1243 int retval; 1244 1245 if (best_enum == NULL) 1246 return; 1247 retval = best_enum->apic_setup_io(); 1248 if (retval != 0) 1249 printf("%s: Failed to setup I/O APICs: returned %d\n", 1250 best_enum->apic_name, retval); 1251 1252 /* 1253 * Finish setting up the local APIC on the BSP once we know how to 1254 * properly program the LINT pins. 1255 */ 1256 lapic_setup(1); 1257 intr_register_pic(&lapic_pic); 1258 if (bootverbose) 1259 lapic_dump("BSP"); 1260 1261 /* Enable the MSI "pic". */ 1262 msi_init(); 1263 } 1264 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL); 1265 1266 #ifdef SMP 1267 /* 1268 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are 1269 * private to the sys/amd64 code. The public interface for the rest of the 1270 * kernel is defined in mp_machdep.c. 1271 */ 1272 int 1273 lapic_ipi_wait(int delay) 1274 { 1275 int x, incr; 1276 1277 /* 1278 * Wait delay loops for IPI to be sent. This is highly bogus 1279 * since this is sensitive to CPU clock speed. If delay is 1280 * -1, we wait forever. 1281 */ 1282 if (delay == -1) { 1283 incr = 0; 1284 delay = 1; 1285 } else 1286 incr = 1; 1287 for (x = 0; x < delay; x += incr) { 1288 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE) 1289 return (1); 1290 ia32_pause(); 1291 } 1292 return (0); 1293 } 1294 1295 void 1296 lapic_ipi_raw(register_t icrlo, u_int dest) 1297 { 1298 register_t value, eflags; 1299 1300 /* XXX: Need more sanity checking of icrlo? */ 1301 KASSERT(lapic != NULL, ("%s called too early", __func__)); 1302 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1303 ("%s: invalid dest field", __func__)); 1304 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0, 1305 ("%s: reserved bits set in ICR LO register", __func__)); 1306 1307 /* Set destination in ICR HI register if it is being used. */ 1308 eflags = intr_disable(); 1309 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) { 1310 value = lapic->icr_hi; 1311 value &= ~APIC_ID_MASK; 1312 value |= dest << APIC_ID_SHIFT; 1313 lapic->icr_hi = value; 1314 } 1315 1316 /* Program the contents of the IPI and dispatch it. */ 1317 value = lapic->icr_lo; 1318 value &= APIC_ICRLO_RESV_MASK; 1319 value |= icrlo; 1320 lapic->icr_lo = value; 1321 intr_restore(eflags); 1322 } 1323 1324 #define BEFORE_SPIN 1000000 1325 #ifdef DETECT_DEADLOCK 1326 #define AFTER_SPIN 1000 1327 #endif 1328 1329 void 1330 lapic_ipi_vectored(u_int vector, int dest) 1331 { 1332 register_t icrlo, destfield; 1333 1334 KASSERT((vector & ~APIC_VECTOR_MASK) == 0, 1335 ("%s: invalid vector %d", __func__, vector)); 1336 1337 icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY | 1338 APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE; 1339 destfield = 0; 1340 switch (dest) { 1341 case APIC_IPI_DEST_SELF: 1342 icrlo |= APIC_DEST_SELF; 1343 break; 1344 case APIC_IPI_DEST_ALL: 1345 icrlo |= APIC_DEST_ALLISELF; 1346 break; 1347 case APIC_IPI_DEST_OTHERS: 1348 icrlo |= APIC_DEST_ALLESELF; 1349 break; 1350 default: 1351 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1352 ("%s: invalid destination 0x%x", __func__, dest)); 1353 destfield = dest; 1354 } 1355 1356 /* Wait for an earlier IPI to finish. */ 1357 if (!lapic_ipi_wait(BEFORE_SPIN)) { 1358 if (panicstr != NULL) 1359 return; 1360 else 1361 panic("APIC: Previous IPI is stuck"); 1362 } 1363 1364 lapic_ipi_raw(icrlo, destfield); 1365 1366 #ifdef DETECT_DEADLOCK 1367 /* Wait for IPI to be delivered. */ 1368 if (!lapic_ipi_wait(AFTER_SPIN)) { 1369 #ifdef needsattention 1370 /* 1371 * XXX FIXME: 1372 * 1373 * The above function waits for the message to actually be 1374 * delivered. It breaks out after an arbitrary timeout 1375 * since the message should eventually be delivered (at 1376 * least in theory) and that if it wasn't we would catch 1377 * the failure with the check above when the next IPI is 1378 * sent. 1379 * 1380 * We could skip this wait entirely, EXCEPT it probably 1381 * protects us from other routines that assume that the 1382 * message was delivered and acted upon when this function 1383 * returns. 1384 */ 1385 printf("APIC: IPI might be stuck\n"); 1386 #else /* !needsattention */ 1387 /* Wait until mesage is sent without a timeout. */ 1388 while (lapic->icr_lo & APIC_DELSTAT_PEND) 1389 ia32_pause(); 1390 #endif /* needsattention */ 1391 } 1392 #endif /* DETECT_DEADLOCK */ 1393 } 1394 #endif /* SMP */
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