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sys/amd64/amd64/local_apic.c
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1 /*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * Copyright (c) 1996, by Steve Passe 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Local APIC support on Pentium and later processors. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD: releng/8.0/sys/amd64/amd64/local_apic.c 196996 2009-09-08 21:50:34Z jhb $"); 36 37 #include "opt_hwpmc_hooks.h" 38 #include "opt_kdtrace.h" 39 40 #include "opt_ddb.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/bus.h> 45 #include <sys/kernel.h> 46 #include <sys/lock.h> 47 #include <sys/mutex.h> 48 #include <sys/pcpu.h> 49 #include <sys/proc.h> 50 #include <sys/sched.h> 51 #include <sys/smp.h> 52 53 #include <vm/vm.h> 54 #include <vm/pmap.h> 55 56 #include <machine/apicreg.h> 57 #include <machine/cpu.h> 58 #include <machine/cputypes.h> 59 #include <machine/frame.h> 60 #include <machine/intr_machdep.h> 61 #include <machine/apicvar.h> 62 #include <machine/md_var.h> 63 #include <machine/smp.h> 64 #include <machine/specialreg.h> 65 66 #ifdef DDB 67 #include <sys/interrupt.h> 68 #include <ddb/ddb.h> 69 #endif 70 71 #ifdef KDTRACE_HOOKS 72 #include <sys/dtrace_bsd.h> 73 cyclic_clock_func_t lapic_cyclic_clock_func[MAXCPU]; 74 #endif 75 76 /* Sanity checks on IDT vectors. */ 77 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT); 78 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS); 79 CTASSERT(APIC_LOCAL_INTS == 240); 80 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT); 81 82 /* Magic IRQ values for the timer and syscalls. */ 83 #define IRQ_TIMER (NUM_IO_INTS + 1) 84 #define IRQ_SYSCALL (NUM_IO_INTS + 2) 85 86 /* 87 * Support for local APICs. Local APICs manage interrupts on each 88 * individual processor as opposed to I/O APICs which receive interrupts 89 * from I/O devices and then forward them on to the local APICs. 90 * 91 * Local APICs can also send interrupts to each other thus providing the 92 * mechanism for IPIs. 93 */ 94 95 struct lvt { 96 u_int lvt_edgetrigger:1; 97 u_int lvt_activehi:1; 98 u_int lvt_masked:1; 99 u_int lvt_active:1; 100 u_int lvt_mode:16; 101 u_int lvt_vector:8; 102 }; 103 104 struct lapic { 105 struct lvt la_lvts[LVT_MAX + 1]; 106 u_int la_id:8; 107 u_int la_cluster:4; 108 u_int la_cluster_id:2; 109 u_int la_present:1; 110 u_long *la_timer_count; 111 u_long la_hard_ticks; 112 u_long la_stat_ticks; 113 u_long la_prof_ticks; 114 /* Include IDT_SYSCALL to make indexing easier. */ 115 int la_ioint_irqs[APIC_NUM_IOINTS + 1]; 116 } static lapics[MAX_APIC_ID + 1]; 117 118 /* XXX: should thermal be an NMI? */ 119 120 /* Global defaults for local APIC LVT entries. */ 121 static struct lvt lvts[LVT_MAX + 1] = { 122 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */ 123 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */ 124 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */ 125 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */ 126 { 1, 1, 1, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */ 127 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */ 128 }; 129 130 static inthand_t *ioint_handlers[] = { 131 NULL, /* 0 - 31 */ 132 IDTVEC(apic_isr1), /* 32 - 63 */ 133 IDTVEC(apic_isr2), /* 64 - 95 */ 134 IDTVEC(apic_isr3), /* 96 - 127 */ 135 IDTVEC(apic_isr4), /* 128 - 159 */ 136 IDTVEC(apic_isr5), /* 160 - 191 */ 137 IDTVEC(apic_isr6), /* 192 - 223 */ 138 IDTVEC(apic_isr7), /* 224 - 255 */ 139 }; 140 141 142 static u_int32_t lapic_timer_divisors[] = { 143 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16, 144 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128 145 }; 146 147 extern inthand_t IDTVEC(rsvd); 148 149 volatile lapic_t *lapic; 150 vm_paddr_t lapic_paddr; 151 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz; 152 153 static void lapic_enable(void); 154 static void lapic_resume(struct pic *pic); 155 static void lapic_timer_enable_intr(void); 156 static void lapic_timer_oneshot(u_int count); 157 static void lapic_timer_periodic(u_int count); 158 static void lapic_timer_set_divisor(u_int divisor); 159 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value); 160 161 struct pic lapic_pic = { .pic_resume = lapic_resume }; 162 163 static uint32_t 164 lvt_mode(struct lapic *la, u_int pin, uint32_t value) 165 { 166 struct lvt *lvt; 167 168 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin)); 169 if (la->la_lvts[pin].lvt_active) 170 lvt = &la->la_lvts[pin]; 171 else 172 lvt = &lvts[pin]; 173 174 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM | 175 APIC_LVT_VECTOR); 176 if (lvt->lvt_edgetrigger == 0) 177 value |= APIC_LVT_TM; 178 if (lvt->lvt_activehi == 0) 179 value |= APIC_LVT_IIPP_INTALO; 180 if (lvt->lvt_masked) 181 value |= APIC_LVT_M; 182 value |= lvt->lvt_mode; 183 switch (lvt->lvt_mode) { 184 case APIC_LVT_DM_NMI: 185 case APIC_LVT_DM_SMI: 186 case APIC_LVT_DM_INIT: 187 case APIC_LVT_DM_EXTINT: 188 if (!lvt->lvt_edgetrigger) { 189 printf("lapic%u: Forcing LINT%u to edge trigger\n", 190 la->la_id, pin); 191 value |= APIC_LVT_TM; 192 } 193 /* Use a vector of 0. */ 194 break; 195 case APIC_LVT_DM_FIXED: 196 value |= lvt->lvt_vector; 197 break; 198 default: 199 panic("bad APIC LVT delivery mode: %#x\n", value); 200 } 201 return (value); 202 } 203 204 /* 205 * Map the local APIC and setup necessary interrupt vectors. 206 */ 207 void 208 lapic_init(vm_paddr_t addr) 209 { 210 211 /* Map the local APIC and setup the spurious interrupt handler. */ 212 KASSERT(trunc_page(addr) == addr, 213 ("local APIC not aligned on a page boundary")); 214 lapic = pmap_mapdev(addr, sizeof(lapic_t)); 215 lapic_paddr = addr; 216 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 217 218 /* Perform basic initialization of the BSP's local APIC. */ 219 lapic_enable(); 220 221 /* Set BSP's per-CPU local APIC ID. */ 222 PCPU_SET(apic_id, lapic_id()); 223 224 /* Local APIC timer interrupt. */ 225 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYSIGT, SEL_KPL, 0); 226 227 /* XXX: error/thermal interrupts */ 228 } 229 230 /* 231 * Create a local APIC instance. 232 */ 233 void 234 lapic_create(u_int apic_id, int boot_cpu) 235 { 236 int i; 237 238 if (apic_id > MAX_APIC_ID) { 239 printf("APIC: Ignoring local APIC with ID %d\n", apic_id); 240 if (boot_cpu) 241 panic("Can't ignore BSP"); 242 return; 243 } 244 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u", 245 apic_id)); 246 247 /* 248 * Assume no local LVT overrides and a cluster of 0 and 249 * intra-cluster ID of 0. 250 */ 251 lapics[apic_id].la_present = 1; 252 lapics[apic_id].la_id = apic_id; 253 for (i = 0; i < LVT_MAX; i++) { 254 lapics[apic_id].la_lvts[i] = lvts[i]; 255 lapics[apic_id].la_lvts[i].lvt_active = 0; 256 } 257 for (i = 0; i <= APIC_NUM_IOINTS; i++) 258 lapics[apic_id].la_ioint_irqs[i] = -1; 259 lapics[apic_id].la_ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL; 260 lapics[apic_id].la_ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = 261 IRQ_TIMER; 262 263 #ifdef SMP 264 cpu_add(apic_id, boot_cpu); 265 #endif 266 } 267 268 /* 269 * Dump contents of local APIC registers 270 */ 271 void 272 lapic_dump(const char* str) 273 { 274 275 printf("cpu%d %s:\n", PCPU_GET(cpuid), str); 276 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n", 277 lapic->id, lapic->version, lapic->ldr, lapic->dfr); 278 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n", 279 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr); 280 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n", 281 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error, 282 lapic->lvt_pcint); 283 } 284 285 void 286 lapic_setup(int boot) 287 { 288 struct lapic *la; 289 u_int32_t maxlvt; 290 register_t eflags; 291 char buf[MAXCOMLEN + 1]; 292 293 la = &lapics[lapic_id()]; 294 KASSERT(la->la_present, ("missing APIC structure")); 295 eflags = intr_disable(); 296 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 297 298 /* Initialize the TPR to allow all interrupts. */ 299 lapic_set_tpr(0); 300 301 /* Setup spurious vector and enable the local APIC. */ 302 lapic_enable(); 303 304 /* Program LINT[01] LVT entries. */ 305 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0); 306 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1); 307 308 /* Program the PMC LVT entry if present. */ 309 if (maxlvt >= LVT_PMC) 310 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 311 312 /* Program timer LVT and setup handler. */ 313 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer); 314 if (boot) { 315 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid)); 316 intrcnt_add(buf, &la->la_timer_count); 317 } 318 319 /* We don't setup the timer during boot on the BSP until later. */ 320 if (!(boot && PCPU_GET(cpuid) == 0) && lapic_timer_hz != 0) { 321 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor", 322 lapic_id())); 323 lapic_timer_set_divisor(lapic_timer_divisor); 324 lapic_timer_periodic(lapic_timer_period); 325 lapic_timer_enable_intr(); 326 } 327 328 /* XXX: Error and thermal LVTs */ 329 330 intr_restore(eflags); 331 } 332 333 void 334 lapic_reenable_pmc(void) 335 { 336 #ifdef HWPMC_HOOKS 337 uint32_t value; 338 339 value = lapic->lvt_pcint; 340 value &= ~APIC_LVT_M; 341 lapic->lvt_pcint = value; 342 #endif 343 } 344 345 #ifdef HWPMC_HOOKS 346 static void 347 lapic_update_pmc(void *dummy) 348 { 349 struct lapic *la; 350 351 la = &lapics[lapic_id()]; 352 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 353 } 354 #endif 355 356 int 357 lapic_enable_pmc(void) 358 { 359 #ifdef HWPMC_HOOKS 360 u_int32_t maxlvt; 361 362 /* Fail if the local APIC is not present. */ 363 if (lapic == NULL) 364 return (0); 365 366 /* Fail if the PMC LVT is not present. */ 367 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 368 if (maxlvt < LVT_PMC) 369 return (0); 370 371 lvts[LVT_PMC].lvt_masked = 0; 372 373 #ifdef SMP 374 /* 375 * If hwpmc was loaded at boot time then the APs may not be 376 * started yet. In that case, don't forward the request to 377 * them as they will program the lvt when they start. 378 */ 379 if (smp_started) 380 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL); 381 else 382 #endif 383 lapic_update_pmc(NULL); 384 return (1); 385 #else 386 return (0); 387 #endif 388 } 389 390 void 391 lapic_disable_pmc(void) 392 { 393 #ifdef HWPMC_HOOKS 394 u_int32_t maxlvt; 395 396 /* Fail if the local APIC is not present. */ 397 if (lapic == NULL) 398 return; 399 400 /* Fail if the PMC LVT is not present. */ 401 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 402 if (maxlvt < LVT_PMC) 403 return; 404 405 lvts[LVT_PMC].lvt_masked = 1; 406 407 #ifdef SMP 408 /* The APs should always be started when hwpmc is unloaded. */ 409 KASSERT(mp_ncpus == 1 || smp_started, ("hwpmc unloaded too early")); 410 #endif 411 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL); 412 #endif 413 } 414 415 /* 416 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so 417 * that it can drive hardclock, statclock, and profclock. This function 418 * returns true if it is able to use the local APIC timer to drive the 419 * clocks and false if it is not able. 420 */ 421 int 422 lapic_setup_clock(void) 423 { 424 u_long value; 425 int i; 426 427 /* Can't drive the timer without a local APIC. */ 428 if (lapic == NULL) 429 return (0); 430 431 if (resource_int_value("apic", 0, "clock", &i) == 0 && i == 0) 432 return (0); 433 434 /* Start off with a divisor of 2 (power on reset default). */ 435 lapic_timer_divisor = 2; 436 437 /* Try to calibrate the local APIC timer. */ 438 do { 439 lapic_timer_set_divisor(lapic_timer_divisor); 440 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT); 441 DELAY(2000000); 442 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer; 443 if (value != APIC_TIMER_MAX_COUNT) 444 break; 445 lapic_timer_divisor <<= 1; 446 } while (lapic_timer_divisor <= 128); 447 if (lapic_timer_divisor > 128) 448 panic("lapic: Divisor too big"); 449 value /= 2; 450 if (bootverbose) 451 printf("lapic: Divisor %lu, Frequency %lu hz\n", 452 lapic_timer_divisor, value); 453 454 /* 455 * We want to run stathz in the neighborhood of 128hz. We would 456 * like profhz to run as often as possible, so we let it run on 457 * each clock tick. We try to honor the requested 'hz' value as 458 * much as possible. 459 * 460 * If 'hz' is above 1500, then we just let the lapic timer 461 * (and profhz) run at hz. If 'hz' is below 1500 but above 462 * 750, then we let the lapic timer run at 2 * 'hz'. If 'hz' 463 * is below 750 then we let the lapic timer run at 4 * 'hz'. 464 */ 465 if (hz >= 1500) 466 lapic_timer_hz = hz; 467 else if (hz >= 750) 468 lapic_timer_hz = hz * 2; 469 else 470 lapic_timer_hz = hz * 4; 471 if (lapic_timer_hz < 128) 472 stathz = lapic_timer_hz; 473 else 474 stathz = lapic_timer_hz / (lapic_timer_hz / 128); 475 profhz = lapic_timer_hz; 476 lapic_timer_period = value / lapic_timer_hz; 477 478 /* 479 * Start up the timer on the BSP. The APs will kick off their 480 * timer during lapic_setup(). 481 */ 482 lapic_timer_periodic(lapic_timer_period); 483 lapic_timer_enable_intr(); 484 return (1); 485 } 486 487 void 488 lapic_disable(void) 489 { 490 uint32_t value; 491 492 /* Software disable the local APIC. */ 493 value = lapic->svr; 494 value &= ~APIC_SVR_SWEN; 495 lapic->svr = value; 496 } 497 498 static void 499 lapic_enable(void) 500 { 501 u_int32_t value; 502 503 /* Program the spurious vector to enable the local APIC. */ 504 value = lapic->svr; 505 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS); 506 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT); 507 lapic->svr = value; 508 } 509 510 /* Reset the local APIC on the BSP during resume. */ 511 static void 512 lapic_resume(struct pic *pic) 513 { 514 515 lapic_setup(0); 516 } 517 518 int 519 lapic_id(void) 520 { 521 522 KASSERT(lapic != NULL, ("local APIC is not mapped")); 523 return (lapic->id >> APIC_ID_SHIFT); 524 } 525 526 int 527 lapic_intr_pending(u_int vector) 528 { 529 volatile u_int32_t *irr; 530 531 /* 532 * The IRR registers are an array of 128-bit registers each of 533 * which only describes 32 interrupts in the low 32 bits.. Thus, 534 * we divide the vector by 32 to get the 128-bit index. We then 535 * multiply that index by 4 to get the equivalent index from 536 * treating the IRR as an array of 32-bit registers. Finally, we 537 * modulus the vector by 32 to determine the individual bit to 538 * test. 539 */ 540 irr = &lapic->irr0; 541 return (irr[(vector / 32) * 4] & 1 << (vector % 32)); 542 } 543 544 void 545 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 546 { 547 struct lapic *la; 548 549 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist", 550 __func__, apic_id)); 551 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big", 552 __func__, cluster)); 553 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID, 554 ("%s: intra cluster id %u too big", __func__, cluster_id)); 555 la = &lapics[apic_id]; 556 la->la_cluster = cluster; 557 la->la_cluster_id = cluster_id; 558 } 559 560 int 561 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked) 562 { 563 564 if (pin > LVT_MAX) 565 return (EINVAL); 566 if (apic_id == APIC_ID_ALL) { 567 lvts[pin].lvt_masked = masked; 568 if (bootverbose) 569 printf("lapic:"); 570 } else { 571 KASSERT(lapics[apic_id].la_present, 572 ("%s: missing APIC %u", __func__, apic_id)); 573 lapics[apic_id].la_lvts[pin].lvt_masked = masked; 574 lapics[apic_id].la_lvts[pin].lvt_active = 1; 575 if (bootverbose) 576 printf("lapic%u:", apic_id); 577 } 578 if (bootverbose) 579 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked"); 580 return (0); 581 } 582 583 int 584 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode) 585 { 586 struct lvt *lvt; 587 588 if (pin > LVT_MAX) 589 return (EINVAL); 590 if (apic_id == APIC_ID_ALL) { 591 lvt = &lvts[pin]; 592 if (bootverbose) 593 printf("lapic:"); 594 } else { 595 KASSERT(lapics[apic_id].la_present, 596 ("%s: missing APIC %u", __func__, apic_id)); 597 lvt = &lapics[apic_id].la_lvts[pin]; 598 lvt->lvt_active = 1; 599 if (bootverbose) 600 printf("lapic%u:", apic_id); 601 } 602 lvt->lvt_mode = mode; 603 switch (mode) { 604 case APIC_LVT_DM_NMI: 605 case APIC_LVT_DM_SMI: 606 case APIC_LVT_DM_INIT: 607 case APIC_LVT_DM_EXTINT: 608 lvt->lvt_edgetrigger = 1; 609 lvt->lvt_activehi = 1; 610 if (mode == APIC_LVT_DM_EXTINT) 611 lvt->lvt_masked = 1; 612 else 613 lvt->lvt_masked = 0; 614 break; 615 default: 616 panic("Unsupported delivery mode: 0x%x\n", mode); 617 } 618 if (bootverbose) { 619 printf(" Routing "); 620 switch (mode) { 621 case APIC_LVT_DM_NMI: 622 printf("NMI"); 623 break; 624 case APIC_LVT_DM_SMI: 625 printf("SMI"); 626 break; 627 case APIC_LVT_DM_INIT: 628 printf("INIT"); 629 break; 630 case APIC_LVT_DM_EXTINT: 631 printf("ExtINT"); 632 break; 633 } 634 printf(" -> LINT%u\n", pin); 635 } 636 return (0); 637 } 638 639 int 640 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol) 641 { 642 643 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM) 644 return (EINVAL); 645 if (apic_id == APIC_ID_ALL) { 646 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH); 647 if (bootverbose) 648 printf("lapic:"); 649 } else { 650 KASSERT(lapics[apic_id].la_present, 651 ("%s: missing APIC %u", __func__, apic_id)); 652 lapics[apic_id].la_lvts[pin].lvt_active = 1; 653 lapics[apic_id].la_lvts[pin].lvt_activehi = 654 (pol == INTR_POLARITY_HIGH); 655 if (bootverbose) 656 printf("lapic%u:", apic_id); 657 } 658 if (bootverbose) 659 printf(" LINT%u polarity: %s\n", pin, 660 pol == INTR_POLARITY_HIGH ? "high" : "low"); 661 return (0); 662 } 663 664 int 665 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger) 666 { 667 668 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM) 669 return (EINVAL); 670 if (apic_id == APIC_ID_ALL) { 671 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE); 672 if (bootverbose) 673 printf("lapic:"); 674 } else { 675 KASSERT(lapics[apic_id].la_present, 676 ("%s: missing APIC %u", __func__, apic_id)); 677 lapics[apic_id].la_lvts[pin].lvt_edgetrigger = 678 (trigger == INTR_TRIGGER_EDGE); 679 lapics[apic_id].la_lvts[pin].lvt_active = 1; 680 if (bootverbose) 681 printf("lapic%u:", apic_id); 682 } 683 if (bootverbose) 684 printf(" LINT%u trigger: %s\n", pin, 685 trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 686 return (0); 687 } 688 689 /* 690 * Adjust the TPR of the current CPU so that it blocks all interrupts below 691 * the passed in vector. 692 */ 693 void 694 lapic_set_tpr(u_int vector) 695 { 696 #ifdef CHEAP_TPR 697 lapic->tpr = vector; 698 #else 699 u_int32_t tpr; 700 701 tpr = lapic->tpr & ~APIC_TPR_PRIO; 702 tpr |= vector; 703 lapic->tpr = tpr; 704 #endif 705 } 706 707 void 708 lapic_eoi(void) 709 { 710 711 lapic->eoi = 0; 712 } 713 714 /* 715 * Read the contents of the error status register. We have to write 716 * to the register first before reading from it. 717 */ 718 u_int 719 lapic_error(void) 720 { 721 722 lapic->esr = 0; 723 return (lapic->esr); 724 } 725 726 void 727 lapic_handle_intr(int vector, struct trapframe *frame) 728 { 729 struct intsrc *isrc; 730 731 if (vector == -1) 732 panic("Couldn't get vector from ISR!"); 733 isrc = intr_lookup_source(apic_idt_to_irq(PCPU_GET(apic_id), 734 vector)); 735 intr_execute_handlers(isrc, frame); 736 } 737 738 void 739 lapic_handle_timer(struct trapframe *frame) 740 { 741 struct lapic *la; 742 743 /* Send EOI first thing. */ 744 lapic_eoi(); 745 746 #if defined(SMP) && !defined(SCHED_ULE) 747 /* 748 * Don't do any accounting for the disabled HTT cores, since it 749 * will provide misleading numbers for the userland. 750 * 751 * No locking is necessary here, since even if we loose the race 752 * when hlt_cpus_mask changes it is not a big deal, really. 753 * 754 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask 755 * and unlike other schedulers it actually schedules threads to 756 * those CPUs. 757 */ 758 if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0) 759 return; 760 #endif 761 762 /* Look up our local APIC structure for the tick counters. */ 763 la = &lapics[PCPU_GET(apic_id)]; 764 (*la->la_timer_count)++; 765 critical_enter(); 766 767 #ifdef KDTRACE_HOOKS 768 /* 769 * If the DTrace hooks are configured and a callback function 770 * has been registered, then call it to process the high speed 771 * timers. 772 */ 773 int cpu = PCPU_GET(cpuid); 774 if (lapic_cyclic_clock_func[cpu] != NULL) 775 (*lapic_cyclic_clock_func[cpu])(frame); 776 #endif 777 778 /* Fire hardclock at hz. */ 779 la->la_hard_ticks += hz; 780 if (la->la_hard_ticks >= lapic_timer_hz) { 781 la->la_hard_ticks -= lapic_timer_hz; 782 if (PCPU_GET(cpuid) == 0) 783 hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); 784 else 785 hardclock_cpu(TRAPF_USERMODE(frame)); 786 } 787 788 /* Fire statclock at stathz. */ 789 la->la_stat_ticks += stathz; 790 if (la->la_stat_ticks >= lapic_timer_hz) { 791 la->la_stat_ticks -= lapic_timer_hz; 792 statclock(TRAPF_USERMODE(frame)); 793 } 794 795 /* Fire profclock at profhz, but only when needed. */ 796 la->la_prof_ticks += profhz; 797 if (la->la_prof_ticks >= lapic_timer_hz) { 798 la->la_prof_ticks -= lapic_timer_hz; 799 if (profprocs != 0) 800 profclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); 801 } 802 critical_exit(); 803 } 804 805 static void 806 lapic_timer_set_divisor(u_int divisor) 807 { 808 809 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor)); 810 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) / 811 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor)); 812 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1]; 813 } 814 815 static void 816 lapic_timer_oneshot(u_int count) 817 { 818 u_int32_t value; 819 820 value = lapic->lvt_timer; 821 value &= ~APIC_LVTT_TM; 822 value |= APIC_LVTT_TM_ONE_SHOT; 823 lapic->lvt_timer = value; 824 lapic->icr_timer = count; 825 } 826 827 static void 828 lapic_timer_periodic(u_int count) 829 { 830 u_int32_t value; 831 832 value = lapic->lvt_timer; 833 value &= ~APIC_LVTT_TM; 834 value |= APIC_LVTT_TM_PERIODIC; 835 lapic->lvt_timer = value; 836 lapic->icr_timer = count; 837 } 838 839 static void 840 lapic_timer_enable_intr(void) 841 { 842 u_int32_t value; 843 844 value = lapic->lvt_timer; 845 value &= ~APIC_LVT_M; 846 lapic->lvt_timer = value; 847 } 848 849 u_int 850 apic_cpuid(u_int apic_id) 851 { 852 #ifdef SMP 853 return apic_cpuids[apic_id]; 854 #else 855 return 0; 856 #endif 857 } 858 859 /* Request a free IDT vector to be used by the specified IRQ. */ 860 u_int 861 apic_alloc_vector(u_int apic_id, u_int irq) 862 { 863 u_int vector; 864 865 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 866 867 /* 868 * Search for a free vector. Currently we just use a very simple 869 * algorithm to find the first free vector. 870 */ 871 mtx_lock_spin(&icu_lock); 872 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 873 if (lapics[apic_id].la_ioint_irqs[vector] != -1) 874 continue; 875 lapics[apic_id].la_ioint_irqs[vector] = irq; 876 mtx_unlock_spin(&icu_lock); 877 return (vector + APIC_IO_INTS); 878 } 879 mtx_unlock_spin(&icu_lock); 880 return (0); 881 } 882 883 /* 884 * Request 'count' free contiguous IDT vectors to be used by 'count' 885 * IRQs. 'count' must be a power of two and the vectors will be 886 * aligned on a boundary of 'align'. If the request cannot be 887 * satisfied, 0 is returned. 888 */ 889 u_int 890 apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align) 891 { 892 u_int first, run, vector; 893 894 KASSERT(powerof2(count), ("bad count")); 895 KASSERT(powerof2(align), ("bad align")); 896 KASSERT(align >= count, ("align < count")); 897 #ifdef INVARIANTS 898 for (run = 0; run < count; run++) 899 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u", 900 irqs[run], run)); 901 #endif 902 903 /* 904 * Search for 'count' free vectors. As with apic_alloc_vector(), 905 * this just uses a simple first fit algorithm. 906 */ 907 run = 0; 908 first = 0; 909 mtx_lock_spin(&icu_lock); 910 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 911 912 /* Vector is in use, end run. */ 913 if (lapics[apic_id].la_ioint_irqs[vector] != -1) { 914 run = 0; 915 first = 0; 916 continue; 917 } 918 919 /* Start a new run if run == 0 and vector is aligned. */ 920 if (run == 0) { 921 if ((vector & (align - 1)) != 0) 922 continue; 923 first = vector; 924 } 925 run++; 926 927 /* Keep looping if the run isn't long enough yet. */ 928 if (run < count) 929 continue; 930 931 /* Found a run, assign IRQs and return the first vector. */ 932 for (vector = 0; vector < count; vector++) 933 lapics[apic_id].la_ioint_irqs[first + vector] = 934 irqs[vector]; 935 mtx_unlock_spin(&icu_lock); 936 return (first + APIC_IO_INTS); 937 } 938 mtx_unlock_spin(&icu_lock); 939 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count); 940 return (0); 941 } 942 943 /* 944 * Enable a vector for a particular apic_id. Since all lapics share idt 945 * entries and ioint_handlers this enables the vector on all lapics. lapics 946 * which do not have the vector configured would report spurious interrupts 947 * should it fire. 948 */ 949 void 950 apic_enable_vector(u_int apic_id, u_int vector) 951 { 952 953 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 954 KASSERT(ioint_handlers[vector / 32] != NULL, 955 ("No ISR handler for vector %u", vector)); 956 setidt(vector, ioint_handlers[vector / 32], SDT_SYSIGT, SEL_KPL, 0); 957 } 958 959 void 960 apic_disable_vector(u_int apic_id, u_int vector) 961 { 962 963 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 964 KASSERT(ioint_handlers[vector / 32] != NULL, 965 ("No ISR handler for vector %u", vector)); 966 #ifdef notyet 967 /* 968 * We can not currently clear the idt entry because other cpus 969 * may have a valid vector at this offset. 970 */ 971 setidt(vector, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 972 #endif 973 } 974 975 /* Release an APIC vector when it's no longer in use. */ 976 void 977 apic_free_vector(u_int apic_id, u_int vector, u_int irq) 978 { 979 struct thread *td; 980 981 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 982 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 983 ("Vector %u does not map to an IRQ line", vector)); 984 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 985 KASSERT(lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] == 986 irq, ("IRQ mismatch")); 987 988 /* 989 * Bind us to the cpu that owned the vector before freeing it so 990 * we don't lose an interrupt delivery race. 991 */ 992 td = curthread; 993 if (!rebooting) { 994 thread_lock(td); 995 if (sched_is_bound(td)) 996 panic("apic_free_vector: Thread already bound.\n"); 997 sched_bind(td, apic_cpuid(apic_id)); 998 thread_unlock(td); 999 } 1000 mtx_lock_spin(&icu_lock); 1001 lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] = -1; 1002 mtx_unlock_spin(&icu_lock); 1003 if (!rebooting) { 1004 thread_lock(td); 1005 sched_unbind(td); 1006 thread_unlock(td); 1007 } 1008 } 1009 1010 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */ 1011 u_int 1012 apic_idt_to_irq(u_int apic_id, u_int vector) 1013 { 1014 int irq; 1015 1016 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 1017 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 1018 ("Vector %u does not map to an IRQ line", vector)); 1019 irq = lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS]; 1020 if (irq < 0) 1021 irq = 0; 1022 return (irq); 1023 } 1024 1025 #ifdef DDB 1026 /* 1027 * Dump data about APIC IDT vector mappings. 1028 */ 1029 DB_SHOW_COMMAND(apic, db_show_apic) 1030 { 1031 struct intsrc *isrc; 1032 int i, verbose; 1033 u_int apic_id; 1034 u_int irq; 1035 1036 if (strcmp(modif, "vv") == 0) 1037 verbose = 2; 1038 else if (strcmp(modif, "v") == 0) 1039 verbose = 1; 1040 else 1041 verbose = 0; 1042 for (apic_id = 0; apic_id <= MAX_APIC_ID; apic_id++) { 1043 if (lapics[apic_id].la_present == 0) 1044 continue; 1045 db_printf("Interrupts bound to lapic %u\n", apic_id); 1046 for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) { 1047 irq = lapics[apic_id].la_ioint_irqs[i]; 1048 if (irq == -1 || irq == IRQ_SYSCALL) 1049 continue; 1050 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS); 1051 if (irq == IRQ_TIMER) 1052 db_printf("lapic timer\n"); 1053 else if (irq < NUM_IO_INTS) { 1054 isrc = intr_lookup_source(irq); 1055 if (isrc == NULL || verbose == 0) 1056 db_printf("IRQ %u\n", irq); 1057 else 1058 db_dump_intr_event(isrc->is_event, 1059 verbose == 2); 1060 } else 1061 db_printf("IRQ %u ???\n", irq); 1062 } 1063 } 1064 } 1065 1066 static void 1067 dump_mask(const char *prefix, uint32_t v, int base) 1068 { 1069 int i, first; 1070 1071 first = 1; 1072 for (i = 0; i < 32; i++) 1073 if (v & (1 << i)) { 1074 if (first) { 1075 db_printf("%s:", prefix); 1076 first = 0; 1077 } 1078 db_printf(" %02x", base + i); 1079 } 1080 if (!first) 1081 db_printf("\n"); 1082 } 1083 1084 /* Show info from the lapic regs for this CPU. */ 1085 DB_SHOW_COMMAND(lapic, db_show_lapic) 1086 { 1087 uint32_t v; 1088 1089 db_printf("lapic ID = %d\n", lapic_id()); 1090 v = lapic->version; 1091 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4, 1092 v & 0xf); 1093 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT); 1094 v = lapic->svr; 1095 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR, 1096 v & APIC_SVR_ENABLE ? "enabled" : "disabled"); 1097 db_printf("TPR = %02x\n", lapic->tpr); 1098 1099 #define dump_field(prefix, index) \ 1100 dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \ 1101 index * 32) 1102 1103 db_printf("In-service Interrupts:\n"); 1104 dump_field(isr, 0); 1105 dump_field(isr, 1); 1106 dump_field(isr, 2); 1107 dump_field(isr, 3); 1108 dump_field(isr, 4); 1109 dump_field(isr, 5); 1110 dump_field(isr, 6); 1111 dump_field(isr, 7); 1112 1113 db_printf("TMR Interrupts:\n"); 1114 dump_field(tmr, 0); 1115 dump_field(tmr, 1); 1116 dump_field(tmr, 2); 1117 dump_field(tmr, 3); 1118 dump_field(tmr, 4); 1119 dump_field(tmr, 5); 1120 dump_field(tmr, 6); 1121 dump_field(tmr, 7); 1122 1123 db_printf("IRR Interrupts:\n"); 1124 dump_field(irr, 0); 1125 dump_field(irr, 1); 1126 dump_field(irr, 2); 1127 dump_field(irr, 3); 1128 dump_field(irr, 4); 1129 dump_field(irr, 5); 1130 dump_field(irr, 6); 1131 dump_field(irr, 7); 1132 1133 #undef dump_field 1134 } 1135 #endif 1136 1137 /* 1138 * APIC probing support code. This includes code to manage enumerators. 1139 */ 1140 1141 static SLIST_HEAD(, apic_enumerator) enumerators = 1142 SLIST_HEAD_INITIALIZER(enumerators); 1143 static struct apic_enumerator *best_enum; 1144 1145 void 1146 apic_register_enumerator(struct apic_enumerator *enumerator) 1147 { 1148 #ifdef INVARIANTS 1149 struct apic_enumerator *apic_enum; 1150 1151 SLIST_FOREACH(apic_enum, &enumerators, apic_next) { 1152 if (apic_enum == enumerator) 1153 panic("%s: Duplicate register of %s", __func__, 1154 enumerator->apic_name); 1155 } 1156 #endif 1157 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next); 1158 } 1159 1160 /* 1161 * We have to look for CPU's very, very early because certain subsystems 1162 * want to know how many CPU's we have extremely early on in the boot 1163 * process. 1164 */ 1165 static void 1166 apic_init(void *dummy __unused) 1167 { 1168 struct apic_enumerator *enumerator; 1169 int retval, best; 1170 1171 /* Don't probe if APIC mode is disabled. */ 1172 if (resource_disabled("apic", 0)) 1173 return; 1174 1175 /* First, probe all the enumerators to find the best match. */ 1176 best_enum = NULL; 1177 best = 0; 1178 SLIST_FOREACH(enumerator, &enumerators, apic_next) { 1179 retval = enumerator->apic_probe(); 1180 if (retval > 0) 1181 continue; 1182 if (best_enum == NULL || best < retval) { 1183 best_enum = enumerator; 1184 best = retval; 1185 } 1186 } 1187 if (best_enum == NULL) { 1188 if (bootverbose) 1189 printf("APIC: Could not find any APICs.\n"); 1190 return; 1191 } 1192 1193 if (bootverbose) 1194 printf("APIC: Using the %s enumerator.\n", 1195 best_enum->apic_name); 1196 1197 /* Second, probe the CPU's in the system. */ 1198 retval = best_enum->apic_probe_cpus(); 1199 if (retval != 0) 1200 printf("%s: Failed to probe CPUs: returned %d\n", 1201 best_enum->apic_name, retval); 1202 } 1203 SYSINIT(apic_init, SI_SUB_TUNABLES - 1, SI_ORDER_SECOND, apic_init, NULL); 1204 1205 /* 1206 * Setup the local APIC. We have to do this prior to starting up the APs 1207 * in the SMP case. 1208 */ 1209 static void 1210 apic_setup_local(void *dummy __unused) 1211 { 1212 int retval; 1213 1214 if (best_enum == NULL) 1215 return; 1216 retval = best_enum->apic_setup_local(); 1217 if (retval != 0) 1218 printf("%s: Failed to setup the local APIC: returned %d\n", 1219 best_enum->apic_name, retval); 1220 } 1221 SYSINIT(apic_setup_local, SI_SUB_CPU, SI_ORDER_SECOND, apic_setup_local, 1222 NULL); 1223 1224 /* 1225 * Setup the I/O APICs. 1226 */ 1227 static void 1228 apic_setup_io(void *dummy __unused) 1229 { 1230 int retval; 1231 1232 if (best_enum == NULL) 1233 return; 1234 retval = best_enum->apic_setup_io(); 1235 if (retval != 0) 1236 printf("%s: Failed to setup I/O APICs: returned %d\n", 1237 best_enum->apic_name, retval); 1238 1239 /* 1240 * Finish setting up the local APIC on the BSP once we know how to 1241 * properly program the LINT pins. 1242 */ 1243 lapic_setup(1); 1244 intr_register_pic(&lapic_pic); 1245 if (bootverbose) 1246 lapic_dump("BSP"); 1247 1248 /* Enable the MSI "pic". */ 1249 msi_init(); 1250 } 1251 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL); 1252 1253 #ifdef SMP 1254 /* 1255 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are 1256 * private to the sys/amd64 code. The public interface for the rest of the 1257 * kernel is defined in mp_machdep.c. 1258 */ 1259 int 1260 lapic_ipi_wait(int delay) 1261 { 1262 int x, incr; 1263 1264 /* 1265 * Wait delay loops for IPI to be sent. This is highly bogus 1266 * since this is sensitive to CPU clock speed. If delay is 1267 * -1, we wait forever. 1268 */ 1269 if (delay == -1) { 1270 incr = 0; 1271 delay = 1; 1272 } else 1273 incr = 1; 1274 for (x = 0; x < delay; x += incr) { 1275 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE) 1276 return (1); 1277 ia32_pause(); 1278 } 1279 return (0); 1280 } 1281 1282 void 1283 lapic_ipi_raw(register_t icrlo, u_int dest) 1284 { 1285 register_t value, eflags; 1286 1287 /* XXX: Need more sanity checking of icrlo? */ 1288 KASSERT(lapic != NULL, ("%s called too early", __func__)); 1289 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1290 ("%s: invalid dest field", __func__)); 1291 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0, 1292 ("%s: reserved bits set in ICR LO register", __func__)); 1293 1294 /* Set destination in ICR HI register if it is being used. */ 1295 eflags = intr_disable(); 1296 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) { 1297 value = lapic->icr_hi; 1298 value &= ~APIC_ID_MASK; 1299 value |= dest << APIC_ID_SHIFT; 1300 lapic->icr_hi = value; 1301 } 1302 1303 /* Program the contents of the IPI and dispatch it. */ 1304 value = lapic->icr_lo; 1305 value &= APIC_ICRLO_RESV_MASK; 1306 value |= icrlo; 1307 lapic->icr_lo = value; 1308 intr_restore(eflags); 1309 } 1310 1311 #define BEFORE_SPIN 1000000 1312 #ifdef DETECT_DEADLOCK 1313 #define AFTER_SPIN 1000 1314 #endif 1315 1316 void 1317 lapic_ipi_vectored(u_int vector, int dest) 1318 { 1319 register_t icrlo, destfield; 1320 1321 KASSERT((vector & ~APIC_VECTOR_MASK) == 0, 1322 ("%s: invalid vector %d", __func__, vector)); 1323 1324 icrlo = APIC_DESTMODE_PHY | APIC_TRIGMOD_EDGE; 1325 1326 /* 1327 * IPI_STOP_HARD is just a "fake" vector used to send a NMI. 1328 * Use special rules regard NMI if passed, otherwise specify 1329 * the vector. 1330 */ 1331 if (vector == IPI_STOP_HARD) 1332 icrlo |= APIC_DELMODE_NMI | APIC_LEVEL_ASSERT; 1333 else 1334 icrlo |= vector | APIC_DELMODE_FIXED | APIC_LEVEL_DEASSERT; 1335 destfield = 0; 1336 switch (dest) { 1337 case APIC_IPI_DEST_SELF: 1338 icrlo |= APIC_DEST_SELF; 1339 break; 1340 case APIC_IPI_DEST_ALL: 1341 icrlo |= APIC_DEST_ALLISELF; 1342 break; 1343 case APIC_IPI_DEST_OTHERS: 1344 icrlo |= APIC_DEST_ALLESELF; 1345 break; 1346 default: 1347 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1348 ("%s: invalid destination 0x%x", __func__, dest)); 1349 destfield = dest; 1350 } 1351 1352 /* Wait for an earlier IPI to finish. */ 1353 if (!lapic_ipi_wait(BEFORE_SPIN)) { 1354 if (panicstr != NULL) 1355 return; 1356 else 1357 panic("APIC: Previous IPI is stuck"); 1358 } 1359 1360 lapic_ipi_raw(icrlo, destfield); 1361 1362 #ifdef DETECT_DEADLOCK 1363 /* Wait for IPI to be delivered. */ 1364 if (!lapic_ipi_wait(AFTER_SPIN)) { 1365 #ifdef needsattention 1366 /* 1367 * XXX FIXME: 1368 * 1369 * The above function waits for the message to actually be 1370 * delivered. It breaks out after an arbitrary timeout 1371 * since the message should eventually be delivered (at 1372 * least in theory) and that if it wasn't we would catch 1373 * the failure with the check above when the next IPI is 1374 * sent. 1375 * 1376 * We could skip this wait entirely, EXCEPT it probably 1377 * protects us from other routines that assume that the 1378 * message was delivered and acted upon when this function 1379 * returns. 1380 */ 1381 printf("APIC: IPI might be stuck\n"); 1382 #else /* !needsattention */ 1383 /* Wait until mesage is sent without a timeout. */ 1384 while (lapic->icr_lo & APIC_DELSTAT_PEND) 1385 ia32_pause(); 1386 #endif /* needsattention */ 1387 } 1388 #endif /* DETECT_DEADLOCK */ 1389 } 1390 #endif /* SMP */
Cache object: d521c2a1cad26e9685c8d43181a71122
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