1 /*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /*
31 * Local APIC support on Pentium and later processors.
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD: releng/8.1/sys/amd64/amd64/local_apic.c 206598 2010-04-14 15:00:46Z jhb $");
36
37 #include "opt_hwpmc_hooks.h"
38 #include "opt_kdtrace.h"
39
40 #include "opt_ddb.h"
41
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/bus.h>
45 #include <sys/kernel.h>
46 #include <sys/lock.h>
47 #include <sys/mutex.h>
48 #include <sys/pcpu.h>
49 #include <sys/proc.h>
50 #include <sys/sched.h>
51 #include <sys/smp.h>
52
53 #include <vm/vm.h>
54 #include <vm/pmap.h>
55
56 #include <machine/apicreg.h>
57 #include <machine/cpu.h>
58 #include <machine/cputypes.h>
59 #include <machine/frame.h>
60 #include <machine/intr_machdep.h>
61 #include <machine/apicvar.h>
62 #include <machine/md_var.h>
63 #include <machine/smp.h>
64 #include <machine/specialreg.h>
65
66 #ifdef DDB
67 #include <sys/interrupt.h>
68 #include <ddb/ddb.h>
69 #endif
70
71 #ifdef KDTRACE_HOOKS
72 #include <sys/dtrace_bsd.h>
73 cyclic_clock_func_t lapic_cyclic_clock_func[MAXCPU];
74 #endif
75
76 /* Sanity checks on IDT vectors. */
77 CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT);
78 CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS);
79 CTASSERT(APIC_LOCAL_INTS == 240);
80 CTASSERT(IPI_STOP < APIC_SPURIOUS_INT);
81
82 /* Magic IRQ values for the timer and syscalls. */
83 #define IRQ_TIMER (NUM_IO_INTS + 1)
84 #define IRQ_SYSCALL (NUM_IO_INTS + 2)
85
86 /*
87 * Support for local APICs. Local APICs manage interrupts on each
88 * individual processor as opposed to I/O APICs which receive interrupts
89 * from I/O devices and then forward them on to the local APICs.
90 *
91 * Local APICs can also send interrupts to each other thus providing the
92 * mechanism for IPIs.
93 */
94
95 struct lvt {
96 u_int lvt_edgetrigger:1;
97 u_int lvt_activehi:1;
98 u_int lvt_masked:1;
99 u_int lvt_active:1;
100 u_int lvt_mode:16;
101 u_int lvt_vector:8;
102 };
103
104 struct lapic {
105 struct lvt la_lvts[LVT_MAX + 1];
106 u_int la_id:8;
107 u_int la_cluster:4;
108 u_int la_cluster_id:2;
109 u_int la_present:1;
110 u_long *la_timer_count;
111 u_long la_hard_ticks;
112 u_long la_stat_ticks;
113 u_long la_prof_ticks;
114 /* Include IDT_SYSCALL to make indexing easier. */
115 int la_ioint_irqs[APIC_NUM_IOINTS + 1];
116 } static lapics[MAX_APIC_ID + 1];
117
118 /* Global defaults for local APIC LVT entries. */
119 static struct lvt lvts[LVT_MAX + 1] = {
120 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */
121 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */
122 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */
123 { 1, 1, 0, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */
124 { 1, 1, 1, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */
125 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */
126 };
127
128 static inthand_t *ioint_handlers[] = {
129 NULL, /* 0 - 31 */
130 IDTVEC(apic_isr1), /* 32 - 63 */
131 IDTVEC(apic_isr2), /* 64 - 95 */
132 IDTVEC(apic_isr3), /* 96 - 127 */
133 IDTVEC(apic_isr4), /* 128 - 159 */
134 IDTVEC(apic_isr5), /* 160 - 191 */
135 IDTVEC(apic_isr6), /* 192 - 223 */
136 IDTVEC(apic_isr7), /* 224 - 255 */
137 };
138
139
140 static u_int32_t lapic_timer_divisors[] = {
141 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
142 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128
143 };
144
145 extern inthand_t IDTVEC(rsvd);
146
147 volatile lapic_t *lapic;
148 vm_paddr_t lapic_paddr;
149 static u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz;
150 static enum lapic_clock clockcoverage;
151
152 static void lapic_enable(void);
153 static void lapic_resume(struct pic *pic);
154 static void lapic_timer_enable_intr(void);
155 static void lapic_timer_oneshot(u_int count);
156 static void lapic_timer_periodic(u_int count);
157 static void lapic_timer_set_divisor(u_int divisor);
158 static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value);
159
160 struct pic lapic_pic = { .pic_resume = lapic_resume };
161
162 static uint32_t
163 lvt_mode(struct lapic *la, u_int pin, uint32_t value)
164 {
165 struct lvt *lvt;
166
167 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin));
168 if (la->la_lvts[pin].lvt_active)
169 lvt = &la->la_lvts[pin];
170 else
171 lvt = &lvts[pin];
172
173 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM |
174 APIC_LVT_VECTOR);
175 if (lvt->lvt_edgetrigger == 0)
176 value |= APIC_LVT_TM;
177 if (lvt->lvt_activehi == 0)
178 value |= APIC_LVT_IIPP_INTALO;
179 if (lvt->lvt_masked)
180 value |= APIC_LVT_M;
181 value |= lvt->lvt_mode;
182 switch (lvt->lvt_mode) {
183 case APIC_LVT_DM_NMI:
184 case APIC_LVT_DM_SMI:
185 case APIC_LVT_DM_INIT:
186 case APIC_LVT_DM_EXTINT:
187 if (!lvt->lvt_edgetrigger) {
188 printf("lapic%u: Forcing LINT%u to edge trigger\n",
189 la->la_id, pin);
190 value |= APIC_LVT_TM;
191 }
192 /* Use a vector of 0. */
193 break;
194 case APIC_LVT_DM_FIXED:
195 value |= lvt->lvt_vector;
196 break;
197 default:
198 panic("bad APIC LVT delivery mode: %#x\n", value);
199 }
200 return (value);
201 }
202
203 /*
204 * Map the local APIC and setup necessary interrupt vectors.
205 */
206 void
207 lapic_init(vm_paddr_t addr)
208 {
209
210 /* Map the local APIC and setup the spurious interrupt handler. */
211 KASSERT(trunc_page(addr) == addr,
212 ("local APIC not aligned on a page boundary"));
213 lapic = pmap_mapdev(addr, sizeof(lapic_t));
214 lapic_paddr = addr;
215 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0);
216
217 /* Perform basic initialization of the BSP's local APIC. */
218 lapic_enable();
219
220 /* Set BSP's per-CPU local APIC ID. */
221 PCPU_SET(apic_id, lapic_id());
222
223 /* Local APIC timer interrupt. */
224 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYSIGT, SEL_KPL, 0);
225
226 /* Local APIC error interrupt. */
227 setidt(APIC_ERROR_INT, IDTVEC(errorint), SDT_SYSIGT, SEL_KPL, 0);
228
229 /* XXX: Thermal interrupt */
230 }
231
232 /*
233 * Create a local APIC instance.
234 */
235 void
236 lapic_create(u_int apic_id, int boot_cpu)
237 {
238 int i;
239
240 if (apic_id > MAX_APIC_ID) {
241 printf("APIC: Ignoring local APIC with ID %d\n", apic_id);
242 if (boot_cpu)
243 panic("Can't ignore BSP");
244 return;
245 }
246 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u",
247 apic_id));
248
249 /*
250 * Assume no local LVT overrides and a cluster of 0 and
251 * intra-cluster ID of 0.
252 */
253 lapics[apic_id].la_present = 1;
254 lapics[apic_id].la_id = apic_id;
255 for (i = 0; i < LVT_MAX; i++) {
256 lapics[apic_id].la_lvts[i] = lvts[i];
257 lapics[apic_id].la_lvts[i].lvt_active = 0;
258 }
259 for (i = 0; i <= APIC_NUM_IOINTS; i++)
260 lapics[apic_id].la_ioint_irqs[i] = -1;
261 lapics[apic_id].la_ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL;
262 lapics[apic_id].la_ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] =
263 IRQ_TIMER;
264
265 #ifdef SMP
266 cpu_add(apic_id, boot_cpu);
267 #endif
268 }
269
270 /*
271 * Dump contents of local APIC registers
272 */
273 void
274 lapic_dump(const char* str)
275 {
276
277 printf("cpu%d %s:\n", PCPU_GET(cpuid), str);
278 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n",
279 lapic->id, lapic->version, lapic->ldr, lapic->dfr);
280 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
281 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
282 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pmc: 0x%08x\n",
283 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error,
284 lapic->lvt_pcint);
285 }
286
287 void
288 lapic_setup(int boot)
289 {
290 struct lapic *la;
291 u_int32_t maxlvt;
292 register_t eflags;
293 char buf[MAXCOMLEN + 1];
294
295 la = &lapics[lapic_id()];
296 KASSERT(la->la_present, ("missing APIC structure"));
297 eflags = intr_disable();
298 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
299
300 /* Initialize the TPR to allow all interrupts. */
301 lapic_set_tpr(0);
302
303 /* Setup spurious vector and enable the local APIC. */
304 lapic_enable();
305
306 /* Program LINT[01] LVT entries. */
307 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0);
308 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1);
309
310 /* Program the PMC LVT entry if present. */
311 if (maxlvt >= LVT_PMC)
312 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
313
314 /* Program timer LVT and setup handler. */
315 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer);
316 if (boot) {
317 snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid));
318 intrcnt_add(buf, &la->la_timer_count);
319 }
320
321 /* We don't setup the timer during boot on the BSP until later. */
322 if (!(boot && PCPU_GET(cpuid) == 0) && lapic_timer_hz != 0) {
323 KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor",
324 lapic_id()));
325 lapic_timer_set_divisor(lapic_timer_divisor);
326 lapic_timer_periodic(lapic_timer_period);
327 lapic_timer_enable_intr();
328 }
329
330 /* Program error LVT and clear any existing errors. */
331 lapic->lvt_error = lvt_mode(la, LVT_ERROR, lapic->lvt_error);
332 lapic->esr = 0;
333
334 /* XXX: Thermal LVT */
335
336 intr_restore(eflags);
337 }
338
339 void
340 lapic_reenable_pmc(void)
341 {
342 #ifdef HWPMC_HOOKS
343 uint32_t value;
344
345 value = lapic->lvt_pcint;
346 value &= ~APIC_LVT_M;
347 lapic->lvt_pcint = value;
348 #endif
349 }
350
351 #ifdef HWPMC_HOOKS
352 static void
353 lapic_update_pmc(void *dummy)
354 {
355 struct lapic *la;
356
357 la = &lapics[lapic_id()];
358 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint);
359 }
360 #endif
361
362 int
363 lapic_enable_pmc(void)
364 {
365 #ifdef HWPMC_HOOKS
366 u_int32_t maxlvt;
367
368 /* Fail if the local APIC is not present. */
369 if (lapic == NULL)
370 return (0);
371
372 /* Fail if the PMC LVT is not present. */
373 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
374 if (maxlvt < LVT_PMC)
375 return (0);
376
377 lvts[LVT_PMC].lvt_masked = 0;
378
379 #ifdef SMP
380 /*
381 * If hwpmc was loaded at boot time then the APs may not be
382 * started yet. In that case, don't forward the request to
383 * them as they will program the lvt when they start.
384 */
385 if (smp_started)
386 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
387 else
388 #endif
389 lapic_update_pmc(NULL);
390 return (1);
391 #else
392 return (0);
393 #endif
394 }
395
396 void
397 lapic_disable_pmc(void)
398 {
399 #ifdef HWPMC_HOOKS
400 u_int32_t maxlvt;
401
402 /* Fail if the local APIC is not present. */
403 if (lapic == NULL)
404 return;
405
406 /* Fail if the PMC LVT is not present. */
407 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT;
408 if (maxlvt < LVT_PMC)
409 return;
410
411 lvts[LVT_PMC].lvt_masked = 1;
412
413 #ifdef SMP
414 /* The APs should always be started when hwpmc is unloaded. */
415 KASSERT(mp_ncpus == 1 || smp_started, ("hwpmc unloaded too early"));
416 #endif
417 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL);
418 #endif
419 }
420
421 /*
422 * Called by cpu_initclocks() on the BSP to setup the local APIC timer so
423 * that it can drive hardclock, statclock, and profclock. This function
424 * returns a positive integer if it is convenient to use the local APIC
425 * for all the clocks, a negative integer if it is convenient to use the
426 * local APIC only for the hardclock and 0 if none of them can be handled.
427 */
428 enum lapic_clock
429 lapic_setup_clock(enum lapic_clock srcsdes)
430 {
431 u_long value;
432 int i;
433
434 /* lapic_setup_clock() should not be called with LAPIC_CLOCK_NONE. */
435 MPASS(srcsdes != LAPIC_CLOCK_NONE);
436
437 /* Can't drive the timer without a local APIC. */
438 if (lapic == NULL ||
439 (resource_int_value("apic", 0, "clock", &i) == 0 && i == 0)) {
440 clockcoverage = LAPIC_CLOCK_NONE;
441 return (clockcoverage);
442 }
443
444 /* Start off with a divisor of 2 (power on reset default). */
445 lapic_timer_divisor = 2;
446
447 /* Try to calibrate the local APIC timer. */
448 do {
449 lapic_timer_set_divisor(lapic_timer_divisor);
450 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
451 DELAY(2000000);
452 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
453 if (value != APIC_TIMER_MAX_COUNT)
454 break;
455 lapic_timer_divisor <<= 1;
456 } while (lapic_timer_divisor <= 128);
457 if (lapic_timer_divisor > 128)
458 panic("lapic: Divisor too big");
459 value /= 2;
460 if (bootverbose)
461 printf("lapic: Divisor %lu, Frequency %lu Hz\n",
462 lapic_timer_divisor, value);
463
464 /*
465 * We want to run stathz in the neighborhood of 128hz. We would
466 * like profhz to run as often as possible, so we let it run on
467 * each clock tick. We try to honor the requested 'hz' value as
468 * much as possible.
469 *
470 * If 'hz' is above 1500, then we just let the lapic timer
471 * (and profhz) run at hz. If 'hz' is below 1500 but above
472 * 750, then we let the lapic timer run at 2 * 'hz'. If 'hz'
473 * is below 750 then we let the lapic timer run at 4 * 'hz'.
474 *
475 * Please note that stathz and profhz are set only if all the
476 * clocks are handled through the local APIC.
477 */
478 if (srcsdes == LAPIC_CLOCK_ALL) {
479 if (hz >= 1500)
480 lapic_timer_hz = hz;
481 else if (hz >= 750)
482 lapic_timer_hz = hz * 2;
483 else
484 lapic_timer_hz = hz * 4;
485 } else
486 lapic_timer_hz = hz;
487 lapic_timer_period = value / lapic_timer_hz;
488 if (srcsdes == LAPIC_CLOCK_ALL) {
489 if (lapic_timer_hz < 128)
490 stathz = lapic_timer_hz;
491 else
492 stathz = lapic_timer_hz / (lapic_timer_hz / 128);
493 profhz = lapic_timer_hz;
494 }
495
496 /*
497 * Start up the timer on the BSP. The APs will kick off their
498 * timer during lapic_setup().
499 */
500 lapic_timer_periodic(lapic_timer_period);
501 lapic_timer_enable_intr();
502 clockcoverage = srcsdes;
503 return (srcsdes);
504 }
505
506 void
507 lapic_disable(void)
508 {
509 uint32_t value;
510
511 /* Software disable the local APIC. */
512 value = lapic->svr;
513 value &= ~APIC_SVR_SWEN;
514 lapic->svr = value;
515 }
516
517 static void
518 lapic_enable(void)
519 {
520 u_int32_t value;
521
522 /* Program the spurious vector to enable the local APIC. */
523 value = lapic->svr;
524 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS);
525 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT);
526 lapic->svr = value;
527 }
528
529 /* Reset the local APIC on the BSP during resume. */
530 static void
531 lapic_resume(struct pic *pic)
532 {
533
534 lapic_setup(0);
535 }
536
537 int
538 lapic_id(void)
539 {
540
541 KASSERT(lapic != NULL, ("local APIC is not mapped"));
542 return (lapic->id >> APIC_ID_SHIFT);
543 }
544
545 int
546 lapic_intr_pending(u_int vector)
547 {
548 volatile u_int32_t *irr;
549
550 /*
551 * The IRR registers are an array of 128-bit registers each of
552 * which only describes 32 interrupts in the low 32 bits.. Thus,
553 * we divide the vector by 32 to get the 128-bit index. We then
554 * multiply that index by 4 to get the equivalent index from
555 * treating the IRR as an array of 32-bit registers. Finally, we
556 * modulus the vector by 32 to determine the individual bit to
557 * test.
558 */
559 irr = &lapic->irr0;
560 return (irr[(vector / 32) * 4] & 1 << (vector % 32));
561 }
562
563 void
564 lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id)
565 {
566 struct lapic *la;
567
568 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist",
569 __func__, apic_id));
570 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big",
571 __func__, cluster));
572 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID,
573 ("%s: intra cluster id %u too big", __func__, cluster_id));
574 la = &lapics[apic_id];
575 la->la_cluster = cluster;
576 la->la_cluster_id = cluster_id;
577 }
578
579 int
580 lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked)
581 {
582
583 if (pin > LVT_MAX)
584 return (EINVAL);
585 if (apic_id == APIC_ID_ALL) {
586 lvts[pin].lvt_masked = masked;
587 if (bootverbose)
588 printf("lapic:");
589 } else {
590 KASSERT(lapics[apic_id].la_present,
591 ("%s: missing APIC %u", __func__, apic_id));
592 lapics[apic_id].la_lvts[pin].lvt_masked = masked;
593 lapics[apic_id].la_lvts[pin].lvt_active = 1;
594 if (bootverbose)
595 printf("lapic%u:", apic_id);
596 }
597 if (bootverbose)
598 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked");
599 return (0);
600 }
601
602 int
603 lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode)
604 {
605 struct lvt *lvt;
606
607 if (pin > LVT_MAX)
608 return (EINVAL);
609 if (apic_id == APIC_ID_ALL) {
610 lvt = &lvts[pin];
611 if (bootverbose)
612 printf("lapic:");
613 } else {
614 KASSERT(lapics[apic_id].la_present,
615 ("%s: missing APIC %u", __func__, apic_id));
616 lvt = &lapics[apic_id].la_lvts[pin];
617 lvt->lvt_active = 1;
618 if (bootverbose)
619 printf("lapic%u:", apic_id);
620 }
621 lvt->lvt_mode = mode;
622 switch (mode) {
623 case APIC_LVT_DM_NMI:
624 case APIC_LVT_DM_SMI:
625 case APIC_LVT_DM_INIT:
626 case APIC_LVT_DM_EXTINT:
627 lvt->lvt_edgetrigger = 1;
628 lvt->lvt_activehi = 1;
629 if (mode == APIC_LVT_DM_EXTINT)
630 lvt->lvt_masked = 1;
631 else
632 lvt->lvt_masked = 0;
633 break;
634 default:
635 panic("Unsupported delivery mode: 0x%x\n", mode);
636 }
637 if (bootverbose) {
638 printf(" Routing ");
639 switch (mode) {
640 case APIC_LVT_DM_NMI:
641 printf("NMI");
642 break;
643 case APIC_LVT_DM_SMI:
644 printf("SMI");
645 break;
646 case APIC_LVT_DM_INIT:
647 printf("INIT");
648 break;
649 case APIC_LVT_DM_EXTINT:
650 printf("ExtINT");
651 break;
652 }
653 printf(" -> LINT%u\n", pin);
654 }
655 return (0);
656 }
657
658 int
659 lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol)
660 {
661
662 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM)
663 return (EINVAL);
664 if (apic_id == APIC_ID_ALL) {
665 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH);
666 if (bootverbose)
667 printf("lapic:");
668 } else {
669 KASSERT(lapics[apic_id].la_present,
670 ("%s: missing APIC %u", __func__, apic_id));
671 lapics[apic_id].la_lvts[pin].lvt_active = 1;
672 lapics[apic_id].la_lvts[pin].lvt_activehi =
673 (pol == INTR_POLARITY_HIGH);
674 if (bootverbose)
675 printf("lapic%u:", apic_id);
676 }
677 if (bootverbose)
678 printf(" LINT%u polarity: %s\n", pin,
679 pol == INTR_POLARITY_HIGH ? "high" : "low");
680 return (0);
681 }
682
683 int
684 lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger)
685 {
686
687 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM)
688 return (EINVAL);
689 if (apic_id == APIC_ID_ALL) {
690 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE);
691 if (bootverbose)
692 printf("lapic:");
693 } else {
694 KASSERT(lapics[apic_id].la_present,
695 ("%s: missing APIC %u", __func__, apic_id));
696 lapics[apic_id].la_lvts[pin].lvt_edgetrigger =
697 (trigger == INTR_TRIGGER_EDGE);
698 lapics[apic_id].la_lvts[pin].lvt_active = 1;
699 if (bootverbose)
700 printf("lapic%u:", apic_id);
701 }
702 if (bootverbose)
703 printf(" LINT%u trigger: %s\n", pin,
704 trigger == INTR_TRIGGER_EDGE ? "edge" : "level");
705 return (0);
706 }
707
708 /*
709 * Adjust the TPR of the current CPU so that it blocks all interrupts below
710 * the passed in vector.
711 */
712 void
713 lapic_set_tpr(u_int vector)
714 {
715 #ifdef CHEAP_TPR
716 lapic->tpr = vector;
717 #else
718 u_int32_t tpr;
719
720 tpr = lapic->tpr & ~APIC_TPR_PRIO;
721 tpr |= vector;
722 lapic->tpr = tpr;
723 #endif
724 }
725
726 void
727 lapic_eoi(void)
728 {
729
730 lapic->eoi = 0;
731 }
732
733 void
734 lapic_handle_intr(int vector, struct trapframe *frame)
735 {
736 struct intsrc *isrc;
737
738 if (vector == -1)
739 panic("Couldn't get vector from ISR!");
740 isrc = intr_lookup_source(apic_idt_to_irq(PCPU_GET(apic_id),
741 vector));
742 intr_execute_handlers(isrc, frame);
743 }
744
745 void
746 lapic_handle_timer(struct trapframe *frame)
747 {
748 struct lapic *la;
749
750 /* Send EOI first thing. */
751 lapic_eoi();
752
753 #if defined(SMP) && !defined(SCHED_ULE)
754 /*
755 * Don't do any accounting for the disabled HTT cores, since it
756 * will provide misleading numbers for the userland.
757 *
758 * No locking is necessary here, since even if we loose the race
759 * when hlt_cpus_mask changes it is not a big deal, really.
760 *
761 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask
762 * and unlike other schedulers it actually schedules threads to
763 * those CPUs.
764 */
765 if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0)
766 return;
767 #endif
768
769 /* Look up our local APIC structure for the tick counters. */
770 la = &lapics[PCPU_GET(apic_id)];
771 (*la->la_timer_count)++;
772 critical_enter();
773
774 #ifdef KDTRACE_HOOKS
775 /*
776 * If the DTrace hooks are configured and a callback function
777 * has been registered, then call it to process the high speed
778 * timers.
779 */
780 int cpu = PCPU_GET(cpuid);
781 if (lapic_cyclic_clock_func[cpu] != NULL)
782 (*lapic_cyclic_clock_func[cpu])(frame);
783 #endif
784
785 /* Fire hardclock at hz. */
786 la->la_hard_ticks += hz;
787 if (la->la_hard_ticks >= lapic_timer_hz) {
788 la->la_hard_ticks -= lapic_timer_hz;
789 if (PCPU_GET(cpuid) == 0)
790 hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
791 else
792 hardclock_cpu(TRAPF_USERMODE(frame));
793 }
794 if (clockcoverage == LAPIC_CLOCK_ALL) {
795
796 /* Fire statclock at stathz. */
797 la->la_stat_ticks += stathz;
798 if (la->la_stat_ticks >= lapic_timer_hz) {
799 la->la_stat_ticks -= lapic_timer_hz;
800 statclock(TRAPF_USERMODE(frame));
801 }
802
803 /* Fire profclock at profhz, but only when needed. */
804 la->la_prof_ticks += profhz;
805 if (la->la_prof_ticks >= lapic_timer_hz) {
806 la->la_prof_ticks -= lapic_timer_hz;
807 if (profprocs != 0)
808 profclock(TRAPF_USERMODE(frame),
809 TRAPF_PC(frame));
810 }
811 }
812 critical_exit();
813 }
814
815 static void
816 lapic_timer_set_divisor(u_int divisor)
817 {
818
819 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor));
820 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) /
821 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor));
822 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1];
823 }
824
825 static void
826 lapic_timer_oneshot(u_int count)
827 {
828 u_int32_t value;
829
830 value = lapic->lvt_timer;
831 value &= ~APIC_LVTT_TM;
832 value |= APIC_LVTT_TM_ONE_SHOT;
833 lapic->lvt_timer = value;
834 lapic->icr_timer = count;
835 }
836
837 static void
838 lapic_timer_periodic(u_int count)
839 {
840 u_int32_t value;
841
842 value = lapic->lvt_timer;
843 value &= ~APIC_LVTT_TM;
844 value |= APIC_LVTT_TM_PERIODIC;
845 lapic->lvt_timer = value;
846 lapic->icr_timer = count;
847 }
848
849 static void
850 lapic_timer_enable_intr(void)
851 {
852 u_int32_t value;
853
854 value = lapic->lvt_timer;
855 value &= ~APIC_LVT_M;
856 lapic->lvt_timer = value;
857 }
858
859 void
860 lapic_handle_error(void)
861 {
862 u_int32_t esr;
863
864 /*
865 * Read the contents of the error status register. Write to
866 * the register first before reading from it to force the APIC
867 * to update its value to indicate any errors that have
868 * occurred since the previous write to the register.
869 */
870 lapic->esr = 0;
871 esr = lapic->esr;
872
873 printf("CPU%d: local APIC error 0x%x\n", PCPU_GET(cpuid), esr);
874 lapic_eoi();
875 }
876
877 u_int
878 apic_cpuid(u_int apic_id)
879 {
880 #ifdef SMP
881 return apic_cpuids[apic_id];
882 #else
883 return 0;
884 #endif
885 }
886
887 /* Request a free IDT vector to be used by the specified IRQ. */
888 u_int
889 apic_alloc_vector(u_int apic_id, u_int irq)
890 {
891 u_int vector;
892
893 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
894
895 /*
896 * Search for a free vector. Currently we just use a very simple
897 * algorithm to find the first free vector.
898 */
899 mtx_lock_spin(&icu_lock);
900 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
901 if (lapics[apic_id].la_ioint_irqs[vector] != -1)
902 continue;
903 lapics[apic_id].la_ioint_irqs[vector] = irq;
904 mtx_unlock_spin(&icu_lock);
905 return (vector + APIC_IO_INTS);
906 }
907 mtx_unlock_spin(&icu_lock);
908 return (0);
909 }
910
911 /*
912 * Request 'count' free contiguous IDT vectors to be used by 'count'
913 * IRQs. 'count' must be a power of two and the vectors will be
914 * aligned on a boundary of 'align'. If the request cannot be
915 * satisfied, 0 is returned.
916 */
917 u_int
918 apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align)
919 {
920 u_int first, run, vector;
921
922 KASSERT(powerof2(count), ("bad count"));
923 KASSERT(powerof2(align), ("bad align"));
924 KASSERT(align >= count, ("align < count"));
925 #ifdef INVARIANTS
926 for (run = 0; run < count; run++)
927 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u",
928 irqs[run], run));
929 #endif
930
931 /*
932 * Search for 'count' free vectors. As with apic_alloc_vector(),
933 * this just uses a simple first fit algorithm.
934 */
935 run = 0;
936 first = 0;
937 mtx_lock_spin(&icu_lock);
938 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) {
939
940 /* Vector is in use, end run. */
941 if (lapics[apic_id].la_ioint_irqs[vector] != -1) {
942 run = 0;
943 first = 0;
944 continue;
945 }
946
947 /* Start a new run if run == 0 and vector is aligned. */
948 if (run == 0) {
949 if ((vector & (align - 1)) != 0)
950 continue;
951 first = vector;
952 }
953 run++;
954
955 /* Keep looping if the run isn't long enough yet. */
956 if (run < count)
957 continue;
958
959 /* Found a run, assign IRQs and return the first vector. */
960 for (vector = 0; vector < count; vector++)
961 lapics[apic_id].la_ioint_irqs[first + vector] =
962 irqs[vector];
963 mtx_unlock_spin(&icu_lock);
964 return (first + APIC_IO_INTS);
965 }
966 mtx_unlock_spin(&icu_lock);
967 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count);
968 return (0);
969 }
970
971 /*
972 * Enable a vector for a particular apic_id. Since all lapics share idt
973 * entries and ioint_handlers this enables the vector on all lapics. lapics
974 * which do not have the vector configured would report spurious interrupts
975 * should it fire.
976 */
977 void
978 apic_enable_vector(u_int apic_id, u_int vector)
979 {
980
981 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
982 KASSERT(ioint_handlers[vector / 32] != NULL,
983 ("No ISR handler for vector %u", vector));
984 setidt(vector, ioint_handlers[vector / 32], SDT_SYSIGT, SEL_KPL, 0);
985 }
986
987 void
988 apic_disable_vector(u_int apic_id, u_int vector)
989 {
990
991 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry"));
992 KASSERT(ioint_handlers[vector / 32] != NULL,
993 ("No ISR handler for vector %u", vector));
994 #ifdef notyet
995 /*
996 * We can not currently clear the idt entry because other cpus
997 * may have a valid vector at this offset.
998 */
999 setidt(vector, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
1000 #endif
1001 }
1002
1003 /* Release an APIC vector when it's no longer in use. */
1004 void
1005 apic_free_vector(u_int apic_id, u_int vector, u_int irq)
1006 {
1007 struct thread *td;
1008
1009 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
1010 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
1011 ("Vector %u does not map to an IRQ line", vector));
1012 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq));
1013 KASSERT(lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] ==
1014 irq, ("IRQ mismatch"));
1015
1016 /*
1017 * Bind us to the cpu that owned the vector before freeing it so
1018 * we don't lose an interrupt delivery race.
1019 */
1020 td = curthread;
1021 if (!rebooting) {
1022 thread_lock(td);
1023 if (sched_is_bound(td))
1024 panic("apic_free_vector: Thread already bound.\n");
1025 sched_bind(td, apic_cpuid(apic_id));
1026 thread_unlock(td);
1027 }
1028 mtx_lock_spin(&icu_lock);
1029 lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] = -1;
1030 mtx_unlock_spin(&icu_lock);
1031 if (!rebooting) {
1032 thread_lock(td);
1033 sched_unbind(td);
1034 thread_unlock(td);
1035 }
1036 }
1037
1038 /* Map an IDT vector (APIC) to an IRQ (interrupt source). */
1039 u_int
1040 apic_idt_to_irq(u_int apic_id, u_int vector)
1041 {
1042 int irq;
1043
1044 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL &&
1045 vector <= APIC_IO_INTS + APIC_NUM_IOINTS,
1046 ("Vector %u does not map to an IRQ line", vector));
1047 irq = lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS];
1048 if (irq < 0)
1049 irq = 0;
1050 return (irq);
1051 }
1052
1053 #ifdef DDB
1054 /*
1055 * Dump data about APIC IDT vector mappings.
1056 */
1057 DB_SHOW_COMMAND(apic, db_show_apic)
1058 {
1059 struct intsrc *isrc;
1060 int i, verbose;
1061 u_int apic_id;
1062 u_int irq;
1063
1064 if (strcmp(modif, "vv") == 0)
1065 verbose = 2;
1066 else if (strcmp(modif, "v") == 0)
1067 verbose = 1;
1068 else
1069 verbose = 0;
1070 for (apic_id = 0; apic_id <= MAX_APIC_ID; apic_id++) {
1071 if (lapics[apic_id].la_present == 0)
1072 continue;
1073 db_printf("Interrupts bound to lapic %u\n", apic_id);
1074 for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) {
1075 irq = lapics[apic_id].la_ioint_irqs[i];
1076 if (irq == -1 || irq == IRQ_SYSCALL)
1077 continue;
1078 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS);
1079 if (irq == IRQ_TIMER)
1080 db_printf("lapic timer\n");
1081 else if (irq < NUM_IO_INTS) {
1082 isrc = intr_lookup_source(irq);
1083 if (isrc == NULL || verbose == 0)
1084 db_printf("IRQ %u\n", irq);
1085 else
1086 db_dump_intr_event(isrc->is_event,
1087 verbose == 2);
1088 } else
1089 db_printf("IRQ %u ???\n", irq);
1090 }
1091 }
1092 }
1093
1094 static void
1095 dump_mask(const char *prefix, uint32_t v, int base)
1096 {
1097 int i, first;
1098
1099 first = 1;
1100 for (i = 0; i < 32; i++)
1101 if (v & (1 << i)) {
1102 if (first) {
1103 db_printf("%s:", prefix);
1104 first = 0;
1105 }
1106 db_printf(" %02x", base + i);
1107 }
1108 if (!first)
1109 db_printf("\n");
1110 }
1111
1112 /* Show info from the lapic regs for this CPU. */
1113 DB_SHOW_COMMAND(lapic, db_show_lapic)
1114 {
1115 uint32_t v;
1116
1117 db_printf("lapic ID = %d\n", lapic_id());
1118 v = lapic->version;
1119 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4,
1120 v & 0xf);
1121 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT);
1122 v = lapic->svr;
1123 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR,
1124 v & APIC_SVR_ENABLE ? "enabled" : "disabled");
1125 db_printf("TPR = %02x\n", lapic->tpr);
1126
1127 #define dump_field(prefix, index) \
1128 dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \
1129 index * 32)
1130
1131 db_printf("In-service Interrupts:\n");
1132 dump_field(isr, 0);
1133 dump_field(isr, 1);
1134 dump_field(isr, 2);
1135 dump_field(isr, 3);
1136 dump_field(isr, 4);
1137 dump_field(isr, 5);
1138 dump_field(isr, 6);
1139 dump_field(isr, 7);
1140
1141 db_printf("TMR Interrupts:\n");
1142 dump_field(tmr, 0);
1143 dump_field(tmr, 1);
1144 dump_field(tmr, 2);
1145 dump_field(tmr, 3);
1146 dump_field(tmr, 4);
1147 dump_field(tmr, 5);
1148 dump_field(tmr, 6);
1149 dump_field(tmr, 7);
1150
1151 db_printf("IRR Interrupts:\n");
1152 dump_field(irr, 0);
1153 dump_field(irr, 1);
1154 dump_field(irr, 2);
1155 dump_field(irr, 3);
1156 dump_field(irr, 4);
1157 dump_field(irr, 5);
1158 dump_field(irr, 6);
1159 dump_field(irr, 7);
1160
1161 #undef dump_field
1162 }
1163 #endif
1164
1165 /*
1166 * APIC probing support code. This includes code to manage enumerators.
1167 */
1168
1169 static SLIST_HEAD(, apic_enumerator) enumerators =
1170 SLIST_HEAD_INITIALIZER(enumerators);
1171 static struct apic_enumerator *best_enum;
1172
1173 void
1174 apic_register_enumerator(struct apic_enumerator *enumerator)
1175 {
1176 #ifdef INVARIANTS
1177 struct apic_enumerator *apic_enum;
1178
1179 SLIST_FOREACH(apic_enum, &enumerators, apic_next) {
1180 if (apic_enum == enumerator)
1181 panic("%s: Duplicate register of %s", __func__,
1182 enumerator->apic_name);
1183 }
1184 #endif
1185 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next);
1186 }
1187
1188 /*
1189 * We have to look for CPU's very, very early because certain subsystems
1190 * want to know how many CPU's we have extremely early on in the boot
1191 * process.
1192 */
1193 static void
1194 apic_init(void *dummy __unused)
1195 {
1196 struct apic_enumerator *enumerator;
1197 int retval, best;
1198
1199 /* Don't probe if APIC mode is disabled. */
1200 if (resource_disabled("apic", 0))
1201 return;
1202
1203 /* First, probe all the enumerators to find the best match. */
1204 best_enum = NULL;
1205 best = 0;
1206 SLIST_FOREACH(enumerator, &enumerators, apic_next) {
1207 retval = enumerator->apic_probe();
1208 if (retval > 0)
1209 continue;
1210 if (best_enum == NULL || best < retval) {
1211 best_enum = enumerator;
1212 best = retval;
1213 }
1214 }
1215 if (best_enum == NULL) {
1216 if (bootverbose)
1217 printf("APIC: Could not find any APICs.\n");
1218 return;
1219 }
1220
1221 if (bootverbose)
1222 printf("APIC: Using the %s enumerator.\n",
1223 best_enum->apic_name);
1224
1225 /* Second, probe the CPU's in the system. */
1226 retval = best_enum->apic_probe_cpus();
1227 if (retval != 0)
1228 printf("%s: Failed to probe CPUs: returned %d\n",
1229 best_enum->apic_name, retval);
1230 }
1231 SYSINIT(apic_init, SI_SUB_TUNABLES - 1, SI_ORDER_SECOND, apic_init, NULL);
1232
1233 /*
1234 * Setup the local APIC. We have to do this prior to starting up the APs
1235 * in the SMP case.
1236 */
1237 static void
1238 apic_setup_local(void *dummy __unused)
1239 {
1240 int retval;
1241
1242 if (best_enum == NULL)
1243 return;
1244 retval = best_enum->apic_setup_local();
1245 if (retval != 0)
1246 printf("%s: Failed to setup the local APIC: returned %d\n",
1247 best_enum->apic_name, retval);
1248 }
1249 SYSINIT(apic_setup_local, SI_SUB_CPU, SI_ORDER_SECOND, apic_setup_local,
1250 NULL);
1251
1252 /*
1253 * Setup the I/O APICs.
1254 */
1255 static void
1256 apic_setup_io(void *dummy __unused)
1257 {
1258 int retval;
1259
1260 if (best_enum == NULL)
1261 return;
1262 retval = best_enum->apic_setup_io();
1263 if (retval != 0)
1264 printf("%s: Failed to setup I/O APICs: returned %d\n",
1265 best_enum->apic_name, retval);
1266
1267 /*
1268 * Finish setting up the local APIC on the BSP once we know how to
1269 * properly program the LINT pins.
1270 */
1271 lapic_setup(1);
1272 intr_register_pic(&lapic_pic);
1273 if (bootverbose)
1274 lapic_dump("BSP");
1275
1276 /* Enable the MSI "pic". */
1277 msi_init();
1278 }
1279 SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL);
1280
1281 #ifdef SMP
1282 /*
1283 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are
1284 * private to the sys/amd64 code. The public interface for the rest of the
1285 * kernel is defined in mp_machdep.c.
1286 */
1287 int
1288 lapic_ipi_wait(int delay)
1289 {
1290 int x, incr;
1291
1292 /*
1293 * Wait delay loops for IPI to be sent. This is highly bogus
1294 * since this is sensitive to CPU clock speed. If delay is
1295 * -1, we wait forever.
1296 */
1297 if (delay == -1) {
1298 incr = 0;
1299 delay = 1;
1300 } else
1301 incr = 1;
1302 for (x = 0; x < delay; x += incr) {
1303 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE)
1304 return (1);
1305 ia32_pause();
1306 }
1307 return (0);
1308 }
1309
1310 void
1311 lapic_ipi_raw(register_t icrlo, u_int dest)
1312 {
1313 register_t value, eflags;
1314
1315 /* XXX: Need more sanity checking of icrlo? */
1316 KASSERT(lapic != NULL, ("%s called too early", __func__));
1317 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1318 ("%s: invalid dest field", __func__));
1319 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0,
1320 ("%s: reserved bits set in ICR LO register", __func__));
1321
1322 /* Set destination in ICR HI register if it is being used. */
1323 eflags = intr_disable();
1324 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) {
1325 value = lapic->icr_hi;
1326 value &= ~APIC_ID_MASK;
1327 value |= dest << APIC_ID_SHIFT;
1328 lapic->icr_hi = value;
1329 }
1330
1331 /* Program the contents of the IPI and dispatch it. */
1332 value = lapic->icr_lo;
1333 value &= APIC_ICRLO_RESV_MASK;
1334 value |= icrlo;
1335 lapic->icr_lo = value;
1336 intr_restore(eflags);
1337 }
1338
1339 #define BEFORE_SPIN 1000000
1340 #ifdef DETECT_DEADLOCK
1341 #define AFTER_SPIN 1000
1342 #endif
1343
1344 void
1345 lapic_ipi_vectored(u_int vector, int dest)
1346 {
1347 register_t icrlo, destfield;
1348
1349 KASSERT((vector & ~APIC_VECTOR_MASK) == 0,
1350 ("%s: invalid vector %d", __func__, vector));
1351
1352 icrlo = APIC_DESTMODE_PHY | APIC_TRIGMOD_EDGE;
1353
1354 /*
1355 * IPI_STOP_HARD is just a "fake" vector used to send a NMI.
1356 * Use special rules regard NMI if passed, otherwise specify
1357 * the vector.
1358 */
1359 if (vector == IPI_STOP_HARD)
1360 icrlo |= APIC_DELMODE_NMI | APIC_LEVEL_ASSERT;
1361 else
1362 icrlo |= vector | APIC_DELMODE_FIXED | APIC_LEVEL_DEASSERT;
1363 destfield = 0;
1364 switch (dest) {
1365 case APIC_IPI_DEST_SELF:
1366 icrlo |= APIC_DEST_SELF;
1367 break;
1368 case APIC_IPI_DEST_ALL:
1369 icrlo |= APIC_DEST_ALLISELF;
1370 break;
1371 case APIC_IPI_DEST_OTHERS:
1372 icrlo |= APIC_DEST_ALLESELF;
1373 break;
1374 default:
1375 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0,
1376 ("%s: invalid destination 0x%x", __func__, dest));
1377 destfield = dest;
1378 }
1379
1380 /* Wait for an earlier IPI to finish. */
1381 if (!lapic_ipi_wait(BEFORE_SPIN)) {
1382 if (panicstr != NULL)
1383 return;
1384 else
1385 panic("APIC: Previous IPI is stuck");
1386 }
1387
1388 lapic_ipi_raw(icrlo, destfield);
1389
1390 #ifdef DETECT_DEADLOCK
1391 /* Wait for IPI to be delivered. */
1392 if (!lapic_ipi_wait(AFTER_SPIN)) {
1393 #ifdef needsattention
1394 /*
1395 * XXX FIXME:
1396 *
1397 * The above function waits for the message to actually be
1398 * delivered. It breaks out after an arbitrary timeout
1399 * since the message should eventually be delivered (at
1400 * least in theory) and that if it wasn't we would catch
1401 * the failure with the check above when the next IPI is
1402 * sent.
1403 *
1404 * We could skip this wait entirely, EXCEPT it probably
1405 * protects us from other routines that assume that the
1406 * message was delivered and acted upon when this function
1407 * returns.
1408 */
1409 printf("APIC: IPI might be stuck\n");
1410 #else /* !needsattention */
1411 /* Wait until mesage is sent without a timeout. */
1412 while (lapic->icr_lo & APIC_DELSTAT_PEND)
1413 ia32_pause();
1414 #endif /* needsattention */
1415 }
1416 #endif /* DETECT_DEADLOCK */
1417 }
1418 #endif /* SMP */
Cache object: b410416afa98096c054dd726a459adaf
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