Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/amd64/amd64/machdep.c
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1 /*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD: releng/10.1/sys/amd64/amd64/machdep.c 287146 2015-08-25 20:48:58Z delphij $"); 43 44 #include "opt_atalk.h" 45 #include "opt_atpic.h" 46 #include "opt_compat.h" 47 #include "opt_cpu.h" 48 #include "opt_ddb.h" 49 #include "opt_inet.h" 50 #include "opt_ipx.h" 51 #include "opt_isa.h" 52 #include "opt_kstack_pages.h" 53 #include "opt_maxmem.h" 54 #include "opt_mp_watchdog.h" 55 #include "opt_perfmon.h" 56 #include "opt_platform.h" 57 #include "opt_sched.h" 58 #include "opt_kdtrace.h" 59 60 #include <sys/param.h> 61 #include <sys/proc.h> 62 #include <sys/systm.h> 63 #include <sys/bio.h> 64 #include <sys/buf.h> 65 #include <sys/bus.h> 66 #include <sys/callout.h> 67 #include <sys/cons.h> 68 #include <sys/cpu.h> 69 #include <sys/efi.h> 70 #include <sys/eventhandler.h> 71 #include <sys/exec.h> 72 #include <sys/imgact.h> 73 #include <sys/kdb.h> 74 #include <sys/kernel.h> 75 #include <sys/ktr.h> 76 #include <sys/linker.h> 77 #include <sys/lock.h> 78 #include <sys/malloc.h> 79 #include <sys/memrange.h> 80 #include <sys/msgbuf.h> 81 #include <sys/mutex.h> 82 #include <sys/pcpu.h> 83 #include <sys/ptrace.h> 84 #include <sys/reboot.h> 85 #include <sys/rwlock.h> 86 #include <sys/sched.h> 87 #include <sys/signalvar.h> 88 #ifdef SMP 89 #include <sys/smp.h> 90 #endif 91 #include <sys/syscallsubr.h> 92 #include <sys/sysctl.h> 93 #include <sys/sysent.h> 94 #include <sys/sysproto.h> 95 #include <sys/ucontext.h> 96 #include <sys/vmmeter.h> 97 98 #include <vm/vm.h> 99 #include <vm/vm_extern.h> 100 #include <vm/vm_kern.h> 101 #include <vm/vm_page.h> 102 #include <vm/vm_map.h> 103 #include <vm/vm_object.h> 104 #include <vm/vm_pager.h> 105 #include <vm/vm_param.h> 106 107 #ifdef DDB 108 #ifndef KDB 109 #error KDB must be enabled in order for DDB to work! 110 #endif 111 #include <ddb/ddb.h> 112 #include <ddb/db_sym.h> 113 #endif 114 115 #include <net/netisr.h> 116 117 #include <machine/clock.h> 118 #include <machine/cpu.h> 119 #include <machine/cputypes.h> 120 #include <machine/intr_machdep.h> 121 #include <x86/mca.h> 122 #include <machine/md_var.h> 123 #include <machine/metadata.h> 124 #include <machine/mp_watchdog.h> 125 #include <machine/pc/bios.h> 126 #include <machine/pcb.h> 127 #include <machine/proc.h> 128 #include <machine/reg.h> 129 #include <machine/sigframe.h> 130 #include <machine/specialreg.h> 131 #ifdef PERFMON 132 #include <machine/perfmon.h> 133 #endif 134 #include <machine/tss.h> 135 #ifdef SMP 136 #include <machine/smp.h> 137 #endif 138 #ifdef FDT 139 #include <x86/fdt.h> 140 #endif 141 142 #ifdef DEV_ATPIC 143 #include <x86/isa/icu.h> 144 #else 145 #include <machine/apicvar.h> 146 #endif 147 148 #include <isa/isareg.h> 149 #include <isa/rtc.h> 150 151 /* Sanity check for __curthread() */ 152 CTASSERT(offsetof(struct pcpu, pc_curthread) == 0); 153 154 extern u_int64_t hammer_time(u_int64_t, u_int64_t); 155 156 extern void printcpuinfo(void); /* XXX header file */ 157 extern void identify_cpu(void); 158 extern void panicifcpuunsupported(void); 159 160 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 161 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 162 163 static void cpu_startup(void *); 164 static void get_fpcontext(struct thread *td, mcontext_t *mcp, 165 char *xfpusave, size_t xfpusave_len); 166 static int set_fpcontext(struct thread *td, const mcontext_t *mcp, 167 char *xfpustate, size_t xfpustate_len); 168 SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 169 170 /* 171 * The file "conf/ldscript.amd64" defines the symbol "kernphys". Its value is 172 * the physical address at which the kernel is loaded. 173 */ 174 extern char kernphys[]; 175 #ifdef DDB 176 extern vm_offset_t ksym_start, ksym_end; 177 #endif 178 179 struct msgbuf *msgbufp; 180 181 /* Intel ICH registers */ 182 #define ICH_PMBASE 0x400 183 #define ICH_SMI_EN ICH_PMBASE + 0x30 184 185 int _udatasel, _ucodesel, _ucode32sel, _ufssel, _ugssel; 186 187 int cold = 1; 188 189 long Maxmem = 0; 190 long realmem = 0; 191 192 /* 193 * The number of PHYSMAP entries must be one less than the number of 194 * PHYSSEG entries because the PHYSMAP entry that spans the largest 195 * physical address that is accessible by ISA DMA is split into two 196 * PHYSSEG entries. 197 */ 198 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 199 200 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 201 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 202 203 /* must be 2 less so 0 0 can signal end of chunks */ 204 #define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(phys_avail[0])) - 2) 205 #define DUMP_AVAIL_ARRAY_END ((sizeof(dump_avail) / sizeof(dump_avail[0])) - 2) 206 207 struct kva_md_info kmi; 208 209 static struct trapframe proc0_tf; 210 struct region_descriptor r_gdt, r_idt; 211 212 struct pcpu __pcpu[MAXCPU]; 213 214 struct mtx icu_lock; 215 216 struct mem_range_softc mem_range_softc; 217 218 struct mtx dt_lock; /* lock for GDT and LDT */ 219 220 void (*vmm_resume_p)(void); 221 222 static void 223 cpu_startup(dummy) 224 void *dummy; 225 { 226 uintmax_t memsize; 227 char *sysenv; 228 229 /* 230 * On MacBooks, we need to disallow the legacy USB circuit to 231 * generate an SMI# because this can cause several problems, 232 * namely: incorrect CPU frequency detection and failure to 233 * start the APs. 234 * We do this by disabling a bit in the SMI_EN (SMI Control and 235 * Enable register) of the Intel ICH LPC Interface Bridge. 236 */ 237 sysenv = getenv("smbios.system.product"); 238 if (sysenv != NULL) { 239 if (strncmp(sysenv, "MacBook1,1", 10) == 0 || 240 strncmp(sysenv, "MacBook3,1", 10) == 0 || 241 strncmp(sysenv, "MacBook4,1", 10) == 0 || 242 strncmp(sysenv, "MacBookPro1,1", 13) == 0 || 243 strncmp(sysenv, "MacBookPro1,2", 13) == 0 || 244 strncmp(sysenv, "MacBookPro3,1", 13) == 0 || 245 strncmp(sysenv, "MacBookPro4,1", 13) == 0 || 246 strncmp(sysenv, "Macmini1,1", 10) == 0) { 247 if (bootverbose) 248 printf("Disabling LEGACY_USB_EN bit on " 249 "Intel ICH.\n"); 250 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8); 251 } 252 freeenv(sysenv); 253 } 254 255 /* 256 * Good {morning,afternoon,evening,night}. 257 */ 258 startrtclock(); 259 printcpuinfo(); 260 panicifcpuunsupported(); 261 #ifdef PERFMON 262 perfmon_init(); 263 #endif 264 265 /* 266 * Display physical memory if SMBIOS reports reasonable amount. 267 */ 268 memsize = 0; 269 sysenv = getenv("smbios.memory.enabled"); 270 if (sysenv != NULL) { 271 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10; 272 freeenv(sysenv); 273 } 274 if (memsize < ptoa((uintmax_t)cnt.v_free_count)) 275 memsize = ptoa((uintmax_t)Maxmem); 276 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20); 277 realmem = atop(memsize); 278 279 /* 280 * Display any holes after the first chunk of extended memory. 281 */ 282 if (bootverbose) { 283 int indx; 284 285 printf("Physical memory chunk(s):\n"); 286 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 287 vm_paddr_t size; 288 289 size = phys_avail[indx + 1] - phys_avail[indx]; 290 printf( 291 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n", 292 (uintmax_t)phys_avail[indx], 293 (uintmax_t)phys_avail[indx + 1] - 1, 294 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE); 295 } 296 } 297 298 vm_ksubmap_init(&kmi); 299 300 printf("avail memory = %ju (%ju MB)\n", 301 ptoa((uintmax_t)cnt.v_free_count), 302 ptoa((uintmax_t)cnt.v_free_count) / 1048576); 303 304 /* 305 * Set up buffers, so they can be used to read disk labels. 306 */ 307 bufinit(); 308 vm_pager_bufferinit(); 309 310 cpu_setregs(); 311 } 312 313 /* 314 * Send an interrupt to process. 315 * 316 * Stack is set up to allow sigcode stored 317 * at top to call routine, followed by call 318 * to sigreturn routine below. After sigreturn 319 * resets the signal mask, the stack, and the 320 * frame pointer, it returns to the user 321 * specified pc, psl. 322 */ 323 void 324 sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask) 325 { 326 struct sigframe sf, *sfp; 327 struct pcb *pcb; 328 struct proc *p; 329 struct thread *td; 330 struct sigacts *psp; 331 char *sp; 332 struct trapframe *regs; 333 char *xfpusave; 334 size_t xfpusave_len; 335 int sig; 336 int oonstack; 337 338 td = curthread; 339 pcb = td->td_pcb; 340 p = td->td_proc; 341 PROC_LOCK_ASSERT(p, MA_OWNED); 342 sig = ksi->ksi_signo; 343 psp = p->p_sigacts; 344 mtx_assert(&psp->ps_mtx, MA_OWNED); 345 regs = td->td_frame; 346 oonstack = sigonstack(regs->tf_rsp); 347 348 if (cpu_max_ext_state_size > sizeof(struct savefpu) && use_xsave) { 349 xfpusave_len = cpu_max_ext_state_size - sizeof(struct savefpu); 350 xfpusave = __builtin_alloca(xfpusave_len); 351 } else { 352 xfpusave_len = 0; 353 xfpusave = NULL; 354 } 355 356 /* Save user context. */ 357 bzero(&sf, sizeof(sf)); 358 sf.sf_uc.uc_sigmask = *mask; 359 sf.sf_uc.uc_stack = td->td_sigstk; 360 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK) 361 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE; 362 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0; 363 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(*regs)); 364 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); /* magic */ 365 get_fpcontext(td, &sf.sf_uc.uc_mcontext, xfpusave, xfpusave_len); 366 fpstate_drop(td); 367 sf.sf_uc.uc_mcontext.mc_fsbase = pcb->pcb_fsbase; 368 sf.sf_uc.uc_mcontext.mc_gsbase = pcb->pcb_gsbase; 369 bzero(sf.sf_uc.uc_mcontext.mc_spare, 370 sizeof(sf.sf_uc.uc_mcontext.mc_spare)); 371 bzero(sf.sf_uc.__spare__, sizeof(sf.sf_uc.__spare__)); 372 373 /* Allocate space for the signal handler context. */ 374 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack && 375 SIGISMEMBER(psp->ps_sigonstack, sig)) { 376 sp = td->td_sigstk.ss_sp + td->td_sigstk.ss_size; 377 #if defined(COMPAT_43) 378 td->td_sigstk.ss_flags |= SS_ONSTACK; 379 #endif 380 } else 381 sp = (char *)regs->tf_rsp - 128; 382 if (xfpusave != NULL) { 383 sp -= xfpusave_len; 384 sp = (char *)((unsigned long)sp & ~0x3Ful); 385 sf.sf_uc.uc_mcontext.mc_xfpustate = (register_t)sp; 386 } 387 sp -= sizeof(struct sigframe); 388 /* Align to 16 bytes. */ 389 sfp = (struct sigframe *)((unsigned long)sp & ~0xFul); 390 391 /* Translate the signal if appropriate. */ 392 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize) 393 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 394 395 /* Build the argument list for the signal handler. */ 396 regs->tf_rdi = sig; /* arg 1 in %rdi */ 397 regs->tf_rdx = (register_t)&sfp->sf_uc; /* arg 3 in %rdx */ 398 bzero(&sf.sf_si, sizeof(sf.sf_si)); 399 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 400 /* Signal handler installed with SA_SIGINFO. */ 401 regs->tf_rsi = (register_t)&sfp->sf_si; /* arg 2 in %rsi */ 402 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 403 404 /* Fill in POSIX parts */ 405 sf.sf_si = ksi->ksi_info; 406 sf.sf_si.si_signo = sig; /* maybe a translated signal */ 407 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 408 } else { 409 /* Old FreeBSD-style arguments. */ 410 regs->tf_rsi = ksi->ksi_code; /* arg 2 in %rsi */ 411 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 412 sf.sf_ahu.sf_handler = catcher; 413 } 414 mtx_unlock(&psp->ps_mtx); 415 PROC_UNLOCK(p); 416 417 /* 418 * Copy the sigframe out to the user's stack. 419 */ 420 if (copyout(&sf, sfp, sizeof(*sfp)) != 0 || 421 (xfpusave != NULL && copyout(xfpusave, 422 (void *)sf.sf_uc.uc_mcontext.mc_xfpustate, xfpusave_len) 423 != 0)) { 424 #ifdef DEBUG 425 printf("process %ld has trashed its stack\n", (long)p->p_pid); 426 #endif 427 PROC_LOCK(p); 428 sigexit(td, SIGILL); 429 } 430 431 regs->tf_rsp = (long)sfp; 432 regs->tf_rip = p->p_sysent->sv_sigcode_base; 433 regs->tf_rflags &= ~(PSL_T | PSL_D); 434 regs->tf_cs = _ucodesel; 435 regs->tf_ds = _udatasel; 436 regs->tf_ss = _udatasel; 437 regs->tf_es = _udatasel; 438 regs->tf_fs = _ufssel; 439 regs->tf_gs = _ugssel; 440 regs->tf_flags = TF_HASSEGS; 441 set_pcb_flags(pcb, PCB_FULL_IRET); 442 PROC_LOCK(p); 443 mtx_lock(&psp->ps_mtx); 444 } 445 446 /* 447 * System call to cleanup state after a signal 448 * has been taken. Reset signal mask and 449 * stack state from context left by sendsig (above). 450 * Return to previous pc and psl as specified by 451 * context left by sendsig. Check carefully to 452 * make sure that the user has not modified the 453 * state to gain improper privileges. 454 * 455 * MPSAFE 456 */ 457 int 458 sys_sigreturn(td, uap) 459 struct thread *td; 460 struct sigreturn_args /* { 461 const struct __ucontext *sigcntxp; 462 } */ *uap; 463 { 464 ucontext_t uc; 465 struct pcb *pcb; 466 struct proc *p; 467 struct trapframe *regs; 468 ucontext_t *ucp; 469 char *xfpustate; 470 size_t xfpustate_len; 471 long rflags; 472 int cs, error, ret; 473 ksiginfo_t ksi; 474 475 pcb = td->td_pcb; 476 p = td->td_proc; 477 478 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 479 if (error != 0) { 480 uprintf("pid %d (%s): sigreturn copyin failed\n", 481 p->p_pid, td->td_name); 482 return (error); 483 } 484 ucp = &uc; 485 if ((ucp->uc_mcontext.mc_flags & ~_MC_FLAG_MASK) != 0) { 486 uprintf("pid %d (%s): sigreturn mc_flags %x\n", p->p_pid, 487 td->td_name, ucp->uc_mcontext.mc_flags); 488 return (EINVAL); 489 } 490 regs = td->td_frame; 491 rflags = ucp->uc_mcontext.mc_rflags; 492 /* 493 * Don't allow users to change privileged or reserved flags. 494 */ 495 if (!EFL_SECURE(rflags, regs->tf_rflags)) { 496 uprintf("pid %d (%s): sigreturn rflags = 0x%lx\n", p->p_pid, 497 td->td_name, rflags); 498 return (EINVAL); 499 } 500 501 /* 502 * Don't allow users to load a valid privileged %cs. Let the 503 * hardware check for invalid selectors, excess privilege in 504 * other selectors, invalid %eip's and invalid %esp's. 505 */ 506 cs = ucp->uc_mcontext.mc_cs; 507 if (!CS_SECURE(cs)) { 508 uprintf("pid %d (%s): sigreturn cs = 0x%x\n", p->p_pid, 509 td->td_name, cs); 510 ksiginfo_init_trap(&ksi); 511 ksi.ksi_signo = SIGBUS; 512 ksi.ksi_code = BUS_OBJERR; 513 ksi.ksi_trapno = T_PROTFLT; 514 ksi.ksi_addr = (void *)regs->tf_rip; 515 trapsignal(td, &ksi); 516 return (EINVAL); 517 } 518 519 if ((uc.uc_mcontext.mc_flags & _MC_HASFPXSTATE) != 0) { 520 xfpustate_len = uc.uc_mcontext.mc_xfpustate_len; 521 if (xfpustate_len > cpu_max_ext_state_size - 522 sizeof(struct savefpu)) { 523 uprintf("pid %d (%s): sigreturn xfpusave_len = 0x%zx\n", 524 p->p_pid, td->td_name, xfpustate_len); 525 return (EINVAL); 526 } 527 xfpustate = __builtin_alloca(xfpustate_len); 528 error = copyin((const void *)uc.uc_mcontext.mc_xfpustate, 529 xfpustate, xfpustate_len); 530 if (error != 0) { 531 uprintf( 532 "pid %d (%s): sigreturn copying xfpustate failed\n", 533 p->p_pid, td->td_name); 534 return (error); 535 } 536 } else { 537 xfpustate = NULL; 538 xfpustate_len = 0; 539 } 540 ret = set_fpcontext(td, &ucp->uc_mcontext, xfpustate, xfpustate_len); 541 if (ret != 0) { 542 uprintf("pid %d (%s): sigreturn set_fpcontext err %d\n", 543 p->p_pid, td->td_name, ret); 544 return (ret); 545 } 546 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(*regs)); 547 pcb->pcb_fsbase = ucp->uc_mcontext.mc_fsbase; 548 pcb->pcb_gsbase = ucp->uc_mcontext.mc_gsbase; 549 550 #if defined(COMPAT_43) 551 if (ucp->uc_mcontext.mc_onstack & 1) 552 td->td_sigstk.ss_flags |= SS_ONSTACK; 553 else 554 td->td_sigstk.ss_flags &= ~SS_ONSTACK; 555 #endif 556 557 kern_sigprocmask(td, SIG_SETMASK, &ucp->uc_sigmask, NULL, 0); 558 set_pcb_flags(pcb, PCB_FULL_IRET); 559 return (EJUSTRETURN); 560 } 561 562 #ifdef COMPAT_FREEBSD4 563 int 564 freebsd4_sigreturn(struct thread *td, struct freebsd4_sigreturn_args *uap) 565 { 566 567 return sys_sigreturn(td, (struct sigreturn_args *)uap); 568 } 569 #endif 570 571 572 /* 573 * Machine dependent boot() routine 574 * 575 * I haven't seen anything to put here yet 576 * Possibly some stuff might be grafted back here from boot() 577 */ 578 void 579 cpu_boot(int howto) 580 { 581 } 582 583 /* 584 * Flush the D-cache for non-DMA I/O so that the I-cache can 585 * be made coherent later. 586 */ 587 void 588 cpu_flush_dcache(void *ptr, size_t len) 589 { 590 /* Not applicable */ 591 } 592 593 /* Get current clock frequency for the given cpu id. */ 594 int 595 cpu_est_clockrate(int cpu_id, uint64_t *rate) 596 { 597 uint64_t tsc1, tsc2; 598 uint64_t acnt, mcnt, perf; 599 register_t reg; 600 601 if (pcpu_find(cpu_id) == NULL || rate == NULL) 602 return (EINVAL); 603 604 /* 605 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist, 606 * DELAY(9) based logic fails. 607 */ 608 if (tsc_is_invariant && !tsc_perf_stat) 609 return (EOPNOTSUPP); 610 611 #ifdef SMP 612 if (smp_cpus > 1) { 613 /* Schedule ourselves on the indicated cpu. */ 614 thread_lock(curthread); 615 sched_bind(curthread, cpu_id); 616 thread_unlock(curthread); 617 } 618 #endif 619 620 /* Calibrate by measuring a short delay. */ 621 reg = intr_disable(); 622 if (tsc_is_invariant) { 623 wrmsr(MSR_MPERF, 0); 624 wrmsr(MSR_APERF, 0); 625 tsc1 = rdtsc(); 626 DELAY(1000); 627 mcnt = rdmsr(MSR_MPERF); 628 acnt = rdmsr(MSR_APERF); 629 tsc2 = rdtsc(); 630 intr_restore(reg); 631 perf = 1000 * acnt / mcnt; 632 *rate = (tsc2 - tsc1) * perf; 633 } else { 634 tsc1 = rdtsc(); 635 DELAY(1000); 636 tsc2 = rdtsc(); 637 intr_restore(reg); 638 *rate = (tsc2 - tsc1) * 1000; 639 } 640 641 #ifdef SMP 642 if (smp_cpus > 1) { 643 thread_lock(curthread); 644 sched_unbind(curthread); 645 thread_unlock(curthread); 646 } 647 #endif 648 649 return (0); 650 } 651 652 /* 653 * Shutdown the CPU as much as possible 654 */ 655 void 656 cpu_halt(void) 657 { 658 for (;;) 659 halt(); 660 } 661 662 void (*cpu_idle_hook)(sbintime_t) = NULL; /* ACPI idle hook. */ 663 static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */ 664 static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */ 665 TUNABLE_INT("machdep.idle_mwait", &idle_mwait); 666 SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RW, &idle_mwait, 667 0, "Use MONITOR/MWAIT for short idle"); 668 669 #define STATE_RUNNING 0x0 670 #define STATE_MWAIT 0x1 671 #define STATE_SLEEPING 0x2 672 673 static void 674 cpu_idle_acpi(sbintime_t sbt) 675 { 676 int *state; 677 678 state = (int *)PCPU_PTR(monitorbuf); 679 *state = STATE_SLEEPING; 680 681 /* See comments in cpu_idle_hlt(). */ 682 disable_intr(); 683 if (sched_runnable()) 684 enable_intr(); 685 else if (cpu_idle_hook) 686 cpu_idle_hook(sbt); 687 else 688 __asm __volatile("sti; hlt"); 689 *state = STATE_RUNNING; 690 } 691 692 static void 693 cpu_idle_hlt(sbintime_t sbt) 694 { 695 int *state; 696 697 state = (int *)PCPU_PTR(monitorbuf); 698 *state = STATE_SLEEPING; 699 700 /* 701 * Since we may be in a critical section from cpu_idle(), if 702 * an interrupt fires during that critical section we may have 703 * a pending preemption. If the CPU halts, then that thread 704 * may not execute until a later interrupt awakens the CPU. 705 * To handle this race, check for a runnable thread after 706 * disabling interrupts and immediately return if one is 707 * found. Also, we must absolutely guarentee that hlt is 708 * the next instruction after sti. This ensures that any 709 * interrupt that fires after the call to disable_intr() will 710 * immediately awaken the CPU from hlt. Finally, please note 711 * that on x86 this works fine because of interrupts enabled only 712 * after the instruction following sti takes place, while IF is set 713 * to 1 immediately, allowing hlt instruction to acknowledge the 714 * interrupt. 715 */ 716 disable_intr(); 717 if (sched_runnable()) 718 enable_intr(); 719 else 720 __asm __volatile("sti; hlt"); 721 *state = STATE_RUNNING; 722 } 723 724 /* 725 * MWAIT cpu power states. Lower 4 bits are sub-states. 726 */ 727 #define MWAIT_C0 0xf0 728 #define MWAIT_C1 0x00 729 #define MWAIT_C2 0x10 730 #define MWAIT_C3 0x20 731 #define MWAIT_C4 0x30 732 733 static void 734 cpu_idle_mwait(sbintime_t sbt) 735 { 736 int *state; 737 738 state = (int *)PCPU_PTR(monitorbuf); 739 *state = STATE_MWAIT; 740 741 /* See comments in cpu_idle_hlt(). */ 742 disable_intr(); 743 if (sched_runnable()) { 744 enable_intr(); 745 *state = STATE_RUNNING; 746 return; 747 } 748 cpu_monitor(state, 0, 0); 749 if (*state == STATE_MWAIT) 750 __asm __volatile("sti; mwait" : : "a" (MWAIT_C1), "c" (0)); 751 else 752 enable_intr(); 753 *state = STATE_RUNNING; 754 } 755 756 static void 757 cpu_idle_spin(sbintime_t sbt) 758 { 759 int *state; 760 int i; 761 762 state = (int *)PCPU_PTR(monitorbuf); 763 *state = STATE_RUNNING; 764 765 /* 766 * The sched_runnable() call is racy but as long as there is 767 * a loop missing it one time will have just a little impact if any 768 * (and it is much better than missing the check at all). 769 */ 770 for (i = 0; i < 1000; i++) { 771 if (sched_runnable()) 772 return; 773 cpu_spinwait(); 774 } 775 } 776 777 /* 778 * C1E renders the local APIC timer dead, so we disable it by 779 * reading the Interrupt Pending Message register and clearing 780 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 781 * 782 * Reference: 783 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" 784 * #32559 revision 3.00+ 785 */ 786 #define MSR_AMDK8_IPM 0xc0010055 787 #define AMDK8_SMIONCMPHALT (1ULL << 27) 788 #define AMDK8_C1EONCMPHALT (1ULL << 28) 789 #define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT) 790 791 static void 792 cpu_probe_amdc1e(void) 793 { 794 795 /* 796 * Detect the presence of C1E capability mostly on latest 797 * dual-cores (or future) k8 family. 798 */ 799 if (cpu_vendor_id == CPU_VENDOR_AMD && 800 (cpu_id & 0x00000f00) == 0x00000f00 && 801 (cpu_id & 0x0fff0000) >= 0x00040000) { 802 cpu_ident_amdc1e = 1; 803 } 804 } 805 806 void (*cpu_idle_fn)(sbintime_t) = cpu_idle_acpi; 807 808 void 809 cpu_idle(int busy) 810 { 811 uint64_t msr; 812 sbintime_t sbt = -1; 813 814 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", 815 busy, curcpu); 816 #ifdef MP_WATCHDOG 817 ap_watchdog(PCPU_GET(cpuid)); 818 #endif 819 /* If we are busy - try to use fast methods. */ 820 if (busy) { 821 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) { 822 cpu_idle_mwait(busy); 823 goto out; 824 } 825 } 826 827 /* If we have time - switch timers into idle mode. */ 828 if (!busy) { 829 critical_enter(); 830 sbt = cpu_idleclock(); 831 } 832 833 /* Apply AMD APIC timer C1E workaround. */ 834 if (cpu_ident_amdc1e && cpu_disable_deep_sleep) { 835 msr = rdmsr(MSR_AMDK8_IPM); 836 if (msr & AMDK8_CMPHALT) 837 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); 838 } 839 840 /* Call main idle method. */ 841 cpu_idle_fn(sbt); 842 843 /* Switch timers mack into active mode. */ 844 if (!busy) { 845 cpu_activeclock(); 846 critical_exit(); 847 } 848 out: 849 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", 850 busy, curcpu); 851 } 852 853 int 854 cpu_idle_wakeup(int cpu) 855 { 856 struct pcpu *pcpu; 857 int *state; 858 859 pcpu = pcpu_find(cpu); 860 state = (int *)pcpu->pc_monitorbuf; 861 /* 862 * This doesn't need to be atomic since missing the race will 863 * simply result in unnecessary IPIs. 864 */ 865 if (*state == STATE_SLEEPING) 866 return (0); 867 if (*state == STATE_MWAIT) 868 *state = STATE_RUNNING; 869 return (1); 870 } 871 872 /* 873 * Ordered by speed/power consumption. 874 */ 875 struct { 876 void *id_fn; 877 char *id_name; 878 } idle_tbl[] = { 879 { cpu_idle_spin, "spin" }, 880 { cpu_idle_mwait, "mwait" }, 881 { cpu_idle_hlt, "hlt" }, 882 { cpu_idle_acpi, "acpi" }, 883 { NULL, NULL } 884 }; 885 886 static int 887 idle_sysctl_available(SYSCTL_HANDLER_ARGS) 888 { 889 char *avail, *p; 890 int error; 891 int i; 892 893 avail = malloc(256, M_TEMP, M_WAITOK); 894 p = avail; 895 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 896 if (strstr(idle_tbl[i].id_name, "mwait") && 897 (cpu_feature2 & CPUID2_MON) == 0) 898 continue; 899 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 900 cpu_idle_hook == NULL) 901 continue; 902 p += sprintf(p, "%s%s", p != avail ? ", " : "", 903 idle_tbl[i].id_name); 904 } 905 error = sysctl_handle_string(oidp, avail, 0, req); 906 free(avail, M_TEMP); 907 return (error); 908 } 909 910 SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD, 911 0, 0, idle_sysctl_available, "A", "list of available idle functions"); 912 913 static int 914 idle_sysctl(SYSCTL_HANDLER_ARGS) 915 { 916 char buf[16]; 917 int error; 918 char *p; 919 int i; 920 921 p = "unknown"; 922 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 923 if (idle_tbl[i].id_fn == cpu_idle_fn) { 924 p = idle_tbl[i].id_name; 925 break; 926 } 927 } 928 strncpy(buf, p, sizeof(buf)); 929 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 930 if (error != 0 || req->newptr == NULL) 931 return (error); 932 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 933 if (strstr(idle_tbl[i].id_name, "mwait") && 934 (cpu_feature2 & CPUID2_MON) == 0) 935 continue; 936 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 937 cpu_idle_hook == NULL) 938 continue; 939 if (strcmp(idle_tbl[i].id_name, buf)) 940 continue; 941 cpu_idle_fn = idle_tbl[i].id_fn; 942 return (0); 943 } 944 return (EINVAL); 945 } 946 947 SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0, 948 idle_sysctl, "A", "currently selected idle function"); 949 950 /* 951 * Reset registers to default values on exec. 952 */ 953 void 954 exec_setregs(struct thread *td, struct image_params *imgp, u_long stack) 955 { 956 struct trapframe *regs = td->td_frame; 957 struct pcb *pcb = td->td_pcb; 958 959 mtx_lock(&dt_lock); 960 if (td->td_proc->p_md.md_ldt != NULL) 961 user_ldt_free(td); 962 else 963 mtx_unlock(&dt_lock); 964 965 pcb->pcb_fsbase = 0; 966 pcb->pcb_gsbase = 0; 967 clear_pcb_flags(pcb, PCB_32BIT); 968 pcb->pcb_initial_fpucw = __INITIAL_FPUCW__; 969 set_pcb_flags(pcb, PCB_FULL_IRET); 970 971 bzero((char *)regs, sizeof(struct trapframe)); 972 regs->tf_rip = imgp->entry_addr; 973 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; 974 regs->tf_rdi = stack; /* argv */ 975 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 976 regs->tf_ss = _udatasel; 977 regs->tf_cs = _ucodesel; 978 regs->tf_ds = _udatasel; 979 regs->tf_es = _udatasel; 980 regs->tf_fs = _ufssel; 981 regs->tf_gs = _ugssel; 982 regs->tf_flags = TF_HASSEGS; 983 td->td_retval[1] = 0; 984 985 /* 986 * Reset the hardware debug registers if they were in use. 987 * They won't have any meaning for the newly exec'd process. 988 */ 989 if (pcb->pcb_flags & PCB_DBREGS) { 990 pcb->pcb_dr0 = 0; 991 pcb->pcb_dr1 = 0; 992 pcb->pcb_dr2 = 0; 993 pcb->pcb_dr3 = 0; 994 pcb->pcb_dr6 = 0; 995 pcb->pcb_dr7 = 0; 996 if (pcb == curpcb) { 997 /* 998 * Clear the debug registers on the running 999 * CPU, otherwise they will end up affecting 1000 * the next process we switch to. 1001 */ 1002 reset_dbregs(); 1003 } 1004 clear_pcb_flags(pcb, PCB_DBREGS); 1005 } 1006 1007 /* 1008 * Drop the FP state if we hold it, so that the process gets a 1009 * clean FP state if it uses the FPU again. 1010 */ 1011 fpstate_drop(td); 1012 } 1013 1014 void 1015 cpu_setregs(void) 1016 { 1017 register_t cr0; 1018 1019 cr0 = rcr0(); 1020 /* 1021 * CR0_MP, CR0_NE and CR0_TS are also set by npx_probe() for the 1022 * BSP. See the comments there about why we set them. 1023 */ 1024 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM; 1025 load_cr0(cr0); 1026 } 1027 1028 /* 1029 * Initialize amd64 and configure to run kernel 1030 */ 1031 1032 /* 1033 * Initialize segments & interrupt table 1034 */ 1035 1036 struct user_segment_descriptor gdt[NGDT * MAXCPU];/* global descriptor tables */ 1037 static struct gate_descriptor idt0[NIDT]; 1038 struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */ 1039 1040 static char dblfault_stack[PAGE_SIZE] __aligned(16); 1041 1042 static char nmi0_stack[PAGE_SIZE] __aligned(16); 1043 CTASSERT(sizeof(struct nmi_pcpu) == 16); 1044 1045 struct amd64tss common_tss[MAXCPU]; 1046 1047 /* 1048 * Software prototypes -- in more palatable form. 1049 * 1050 * Keep GUFS32, GUGS32, GUCODE32 and GUDATA at the same 1051 * slots as corresponding segments for i386 kernel. 1052 */ 1053 struct soft_segment_descriptor gdt_segs[] = { 1054 /* GNULL_SEL 0 Null Descriptor */ 1055 { .ssd_base = 0x0, 1056 .ssd_limit = 0x0, 1057 .ssd_type = 0, 1058 .ssd_dpl = 0, 1059 .ssd_p = 0, 1060 .ssd_long = 0, 1061 .ssd_def32 = 0, 1062 .ssd_gran = 0 }, 1063 /* GNULL2_SEL 1 Null Descriptor */ 1064 { .ssd_base = 0x0, 1065 .ssd_limit = 0x0, 1066 .ssd_type = 0, 1067 .ssd_dpl = 0, 1068 .ssd_p = 0, 1069 .ssd_long = 0, 1070 .ssd_def32 = 0, 1071 .ssd_gran = 0 }, 1072 /* GUFS32_SEL 2 32 bit %gs Descriptor for user */ 1073 { .ssd_base = 0x0, 1074 .ssd_limit = 0xfffff, 1075 .ssd_type = SDT_MEMRWA, 1076 .ssd_dpl = SEL_UPL, 1077 .ssd_p = 1, 1078 .ssd_long = 0, 1079 .ssd_def32 = 1, 1080 .ssd_gran = 1 }, 1081 /* GUGS32_SEL 3 32 bit %fs Descriptor for user */ 1082 { .ssd_base = 0x0, 1083 .ssd_limit = 0xfffff, 1084 .ssd_type = SDT_MEMRWA, 1085 .ssd_dpl = SEL_UPL, 1086 .ssd_p = 1, 1087 .ssd_long = 0, 1088 .ssd_def32 = 1, 1089 .ssd_gran = 1 }, 1090 /* GCODE_SEL 4 Code Descriptor for kernel */ 1091 { .ssd_base = 0x0, 1092 .ssd_limit = 0xfffff, 1093 .ssd_type = SDT_MEMERA, 1094 .ssd_dpl = SEL_KPL, 1095 .ssd_p = 1, 1096 .ssd_long = 1, 1097 .ssd_def32 = 0, 1098 .ssd_gran = 1 }, 1099 /* GDATA_SEL 5 Data Descriptor for kernel */ 1100 { .ssd_base = 0x0, 1101 .ssd_limit = 0xfffff, 1102 .ssd_type = SDT_MEMRWA, 1103 .ssd_dpl = SEL_KPL, 1104 .ssd_p = 1, 1105 .ssd_long = 1, 1106 .ssd_def32 = 0, 1107 .ssd_gran = 1 }, 1108 /* GUCODE32_SEL 6 32 bit Code Descriptor for user */ 1109 { .ssd_base = 0x0, 1110 .ssd_limit = 0xfffff, 1111 .ssd_type = SDT_MEMERA, 1112 .ssd_dpl = SEL_UPL, 1113 .ssd_p = 1, 1114 .ssd_long = 0, 1115 .ssd_def32 = 1, 1116 .ssd_gran = 1 }, 1117 /* GUDATA_SEL 7 32/64 bit Data Descriptor for user */ 1118 { .ssd_base = 0x0, 1119 .ssd_limit = 0xfffff, 1120 .ssd_type = SDT_MEMRWA, 1121 .ssd_dpl = SEL_UPL, 1122 .ssd_p = 1, 1123 .ssd_long = 0, 1124 .ssd_def32 = 1, 1125 .ssd_gran = 1 }, 1126 /* GUCODE_SEL 8 64 bit Code Descriptor for user */ 1127 { .ssd_base = 0x0, 1128 .ssd_limit = 0xfffff, 1129 .ssd_type = SDT_MEMERA, 1130 .ssd_dpl = SEL_UPL, 1131 .ssd_p = 1, 1132 .ssd_long = 1, 1133 .ssd_def32 = 0, 1134 .ssd_gran = 1 }, 1135 /* GPROC0_SEL 9 Proc 0 Tss Descriptor */ 1136 { .ssd_base = 0x0, 1137 .ssd_limit = sizeof(struct amd64tss) + IOPAGES * PAGE_SIZE - 1, 1138 .ssd_type = SDT_SYSTSS, 1139 .ssd_dpl = SEL_KPL, 1140 .ssd_p = 1, 1141 .ssd_long = 0, 1142 .ssd_def32 = 0, 1143 .ssd_gran = 0 }, 1144 /* Actually, the TSS is a system descriptor which is double size */ 1145 { .ssd_base = 0x0, 1146 .ssd_limit = 0x0, 1147 .ssd_type = 0, 1148 .ssd_dpl = 0, 1149 .ssd_p = 0, 1150 .ssd_long = 0, 1151 .ssd_def32 = 0, 1152 .ssd_gran = 0 }, 1153 /* GUSERLDT_SEL 11 LDT Descriptor */ 1154 { .ssd_base = 0x0, 1155 .ssd_limit = 0x0, 1156 .ssd_type = 0, 1157 .ssd_dpl = 0, 1158 .ssd_p = 0, 1159 .ssd_long = 0, 1160 .ssd_def32 = 0, 1161 .ssd_gran = 0 }, 1162 /* GUSERLDT_SEL 12 LDT Descriptor, double size */ 1163 { .ssd_base = 0x0, 1164 .ssd_limit = 0x0, 1165 .ssd_type = 0, 1166 .ssd_dpl = 0, 1167 .ssd_p = 0, 1168 .ssd_long = 0, 1169 .ssd_def32 = 0, 1170 .ssd_gran = 0 }, 1171 }; 1172 1173 void 1174 setidt(idx, func, typ, dpl, ist) 1175 int idx; 1176 inthand_t *func; 1177 int typ; 1178 int dpl; 1179 int ist; 1180 { 1181 struct gate_descriptor *ip; 1182 1183 ip = idt + idx; 1184 ip->gd_looffset = (uintptr_t)func; 1185 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1186 ip->gd_ist = ist; 1187 ip->gd_xx = 0; 1188 ip->gd_type = typ; 1189 ip->gd_dpl = dpl; 1190 ip->gd_p = 1; 1191 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1192 } 1193 1194 extern inthand_t 1195 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1196 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1197 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1198 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1199 IDTVEC(xmm), IDTVEC(dblfault), 1200 #ifdef KDTRACE_HOOKS 1201 IDTVEC(dtrace_ret), 1202 #endif 1203 #ifdef XENHVM 1204 IDTVEC(xen_intr_upcall), 1205 #endif 1206 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1207 1208 #ifdef DDB 1209 /* 1210 * Display the index and function name of any IDT entries that don't use 1211 * the default 'rsvd' entry point. 1212 */ 1213 DB_SHOW_COMMAND(idt, db_show_idt) 1214 { 1215 struct gate_descriptor *ip; 1216 int idx; 1217 uintptr_t func; 1218 1219 ip = idt; 1220 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) { 1221 func = ((long)ip->gd_hioffset << 16 | ip->gd_looffset); 1222 if (func != (uintptr_t)&IDTVEC(rsvd)) { 1223 db_printf("%3d\t", idx); 1224 db_printsym(func, DB_STGY_PROC); 1225 db_printf("\n"); 1226 } 1227 ip++; 1228 } 1229 } 1230 1231 /* Show privileged registers. */ 1232 DB_SHOW_COMMAND(sysregs, db_show_sysregs) 1233 { 1234 struct { 1235 uint16_t limit; 1236 uint64_t base; 1237 } __packed idtr, gdtr; 1238 uint16_t ldt, tr; 1239 1240 __asm __volatile("sidt %0" : "=m" (idtr)); 1241 db_printf("idtr\t0x%016lx/%04x\n", 1242 (u_long)idtr.base, (u_int)idtr.limit); 1243 __asm __volatile("sgdt %0" : "=m" (gdtr)); 1244 db_printf("gdtr\t0x%016lx/%04x\n", 1245 (u_long)gdtr.base, (u_int)gdtr.limit); 1246 __asm __volatile("sldt %0" : "=r" (ldt)); 1247 db_printf("ldtr\t0x%04x\n", ldt); 1248 __asm __volatile("str %0" : "=r" (tr)); 1249 db_printf("tr\t0x%04x\n", tr); 1250 db_printf("cr0\t0x%016lx\n", rcr0()); 1251 db_printf("cr2\t0x%016lx\n", rcr2()); 1252 db_printf("cr3\t0x%016lx\n", rcr3()); 1253 db_printf("cr4\t0x%016lx\n", rcr4()); 1254 db_printf("EFER\t%016lx\n", rdmsr(MSR_EFER)); 1255 db_printf("FEATURES_CTL\t%016lx\n", rdmsr(MSR_IA32_FEATURE_CONTROL)); 1256 db_printf("DEBUG_CTL\t%016lx\n", rdmsr(MSR_DEBUGCTLMSR)); 1257 db_printf("PAT\t%016lx\n", rdmsr(MSR_PAT)); 1258 db_printf("GSBASE\t%016lx\n", rdmsr(MSR_GSBASE)); 1259 } 1260 #endif 1261 1262 void 1263 sdtossd(sd, ssd) 1264 struct user_segment_descriptor *sd; 1265 struct soft_segment_descriptor *ssd; 1266 { 1267 1268 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1269 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1270 ssd->ssd_type = sd->sd_type; 1271 ssd->ssd_dpl = sd->sd_dpl; 1272 ssd->ssd_p = sd->sd_p; 1273 ssd->ssd_long = sd->sd_long; 1274 ssd->ssd_def32 = sd->sd_def32; 1275 ssd->ssd_gran = sd->sd_gran; 1276 } 1277 1278 void 1279 ssdtosd(ssd, sd) 1280 struct soft_segment_descriptor *ssd; 1281 struct user_segment_descriptor *sd; 1282 { 1283 1284 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1285 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1286 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1287 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1288 sd->sd_type = ssd->ssd_type; 1289 sd->sd_dpl = ssd->ssd_dpl; 1290 sd->sd_p = ssd->ssd_p; 1291 sd->sd_long = ssd->ssd_long; 1292 sd->sd_def32 = ssd->ssd_def32; 1293 sd->sd_gran = ssd->ssd_gran; 1294 } 1295 1296 void 1297 ssdtosyssd(ssd, sd) 1298 struct soft_segment_descriptor *ssd; 1299 struct system_segment_descriptor *sd; 1300 { 1301 1302 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1303 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1304 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1305 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1306 sd->sd_type = ssd->ssd_type; 1307 sd->sd_dpl = ssd->ssd_dpl; 1308 sd->sd_p = ssd->ssd_p; 1309 sd->sd_gran = ssd->ssd_gran; 1310 } 1311 1312 #if !defined(DEV_ATPIC) && defined(DEV_ISA) 1313 #include <isa/isavar.h> 1314 #include <isa/isareg.h> 1315 /* 1316 * Return a bitmap of the current interrupt requests. This is 8259-specific 1317 * and is only suitable for use at probe time. 1318 * This is only here to pacify sio. It is NOT FATAL if this doesn't work. 1319 * It shouldn't be here. There should probably be an APIC centric 1320 * implementation in the apic driver code, if at all. 1321 */ 1322 intrmask_t 1323 isa_irq_pending(void) 1324 { 1325 u_char irr1; 1326 u_char irr2; 1327 1328 irr1 = inb(IO_ICU1); 1329 irr2 = inb(IO_ICU2); 1330 return ((irr2 << 8) | irr1); 1331 } 1332 #endif 1333 1334 u_int basemem; 1335 1336 static int 1337 add_physmap_entry(uint64_t base, uint64_t length, vm_paddr_t *physmap, 1338 int *physmap_idxp) 1339 { 1340 int i, insert_idx, physmap_idx; 1341 1342 physmap_idx = *physmap_idxp; 1343 1344 if (length == 0) 1345 return (1); 1346 1347 /* 1348 * Find insertion point while checking for overlap. Start off by 1349 * assuming the new entry will be added to the end. 1350 */ 1351 insert_idx = physmap_idx + 2; 1352 for (i = 0; i <= physmap_idx; i += 2) { 1353 if (base < physmap[i + 1]) { 1354 if (base + length <= physmap[i]) { 1355 insert_idx = i; 1356 break; 1357 } 1358 if (boothowto & RB_VERBOSE) 1359 printf( 1360 "Overlapping memory regions, ignoring second region\n"); 1361 return (1); 1362 } 1363 } 1364 1365 /* See if we can prepend to the next entry. */ 1366 if (insert_idx <= physmap_idx && base + length == physmap[insert_idx]) { 1367 physmap[insert_idx] = base; 1368 return (1); 1369 } 1370 1371 /* See if we can append to the previous entry. */ 1372 if (insert_idx > 0 && base == physmap[insert_idx - 1]) { 1373 physmap[insert_idx - 1] += length; 1374 return (1); 1375 } 1376 1377 physmap_idx += 2; 1378 *physmap_idxp = physmap_idx; 1379 if (physmap_idx == PHYSMAP_SIZE) { 1380 printf( 1381 "Too many segments in the physical address map, giving up\n"); 1382 return (0); 1383 } 1384 1385 /* 1386 * Move the last 'N' entries down to make room for the new 1387 * entry if needed. 1388 */ 1389 for (i = physmap_idx; i > insert_idx; i -= 2) { 1390 physmap[i] = physmap[i - 2]; 1391 physmap[i + 1] = physmap[i - 1]; 1392 } 1393 1394 /* Insert the new entry. */ 1395 physmap[insert_idx] = base; 1396 physmap[insert_idx + 1] = base + length; 1397 return (1); 1398 } 1399 1400 static void 1401 add_smap_entries(struct bios_smap *smapbase, vm_paddr_t *physmap, 1402 int *physmap_idx) 1403 { 1404 struct bios_smap *smap, *smapend; 1405 u_int32_t smapsize; 1406 1407 /* 1408 * Memory map from INT 15:E820. 1409 * 1410 * subr_module.c says: 1411 * "Consumer may safely assume that size value precedes data." 1412 * ie: an int32_t immediately precedes smap. 1413 */ 1414 smapsize = *((u_int32_t *)smapbase - 1); 1415 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1416 1417 for (smap = smapbase; smap < smapend; smap++) { 1418 if (boothowto & RB_VERBOSE) 1419 printf("SMAP type=%02x base=%016lx len=%016lx\n", 1420 smap->type, smap->base, smap->length); 1421 1422 if (smap->type != SMAP_TYPE_MEMORY) 1423 continue; 1424 1425 if (!add_physmap_entry(smap->base, smap->length, physmap, 1426 physmap_idx)) 1427 break; 1428 } 1429 } 1430 1431 #define efi_next_descriptor(ptr, size) \ 1432 ((struct efi_md *)(((uint8_t *) ptr) + size)) 1433 1434 static void 1435 add_efi_map_entries(struct efi_map_header *efihdr, vm_paddr_t *physmap, 1436 int *physmap_idx) 1437 { 1438 struct efi_md *map, *p; 1439 const char *type; 1440 size_t efisz; 1441 int ndesc, i; 1442 1443 static const char *types[] = { 1444 "Reserved", 1445 "LoaderCode", 1446 "LoaderData", 1447 "BootServicesCode", 1448 "BootServicesData", 1449 "RuntimeServicesCode", 1450 "RuntimeServicesData", 1451 "ConventionalMemory", 1452 "UnusableMemory", 1453 "ACPIReclaimMemory", 1454 "ACPIMemoryNVS", 1455 "MemoryMappedIO", 1456 "MemoryMappedIOPortSpace", 1457 "PalCode" 1458 }; 1459 1460 /* 1461 * Memory map data provided by UEFI via the GetMemoryMap 1462 * Boot Services API. 1463 */ 1464 efisz = (sizeof(struct efi_map_header) + 0xf) & ~0xf; 1465 map = (struct efi_md *)((uint8_t *)efihdr + efisz); 1466 1467 if (efihdr->descriptor_size == 0) 1468 return; 1469 ndesc = efihdr->memory_size / efihdr->descriptor_size; 1470 1471 if (boothowto & RB_VERBOSE) 1472 printf("%23s %12s %12s %8s %4s\n", 1473 "Type", "Physical", "Virtual", "#Pages", "Attr"); 1474 1475 for (i = 0, p = map; i < ndesc; i++, 1476 p = efi_next_descriptor(p, efihdr->descriptor_size)) { 1477 if (boothowto & RB_VERBOSE) { 1478 if (p->md_type <= EFI_MD_TYPE_PALCODE) 1479 type = types[p->md_type]; 1480 else 1481 type = "<INVALID>"; 1482 printf("%23s %012lx %12p %08lx ", type, p->md_phys, 1483 p->md_virt, p->md_pages); 1484 if (p->md_attr & EFI_MD_ATTR_UC) 1485 printf("UC "); 1486 if (p->md_attr & EFI_MD_ATTR_WC) 1487 printf("WC "); 1488 if (p->md_attr & EFI_MD_ATTR_WT) 1489 printf("WT "); 1490 if (p->md_attr & EFI_MD_ATTR_WB) 1491 printf("WB "); 1492 if (p->md_attr & EFI_MD_ATTR_UCE) 1493 printf("UCE "); 1494 if (p->md_attr & EFI_MD_ATTR_WP) 1495 printf("WP "); 1496 if (p->md_attr & EFI_MD_ATTR_RP) 1497 printf("RP "); 1498 if (p->md_attr & EFI_MD_ATTR_XP) 1499 printf("XP "); 1500 if (p->md_attr & EFI_MD_ATTR_RT) 1501 printf("RUNTIME"); 1502 printf("\n"); 1503 } 1504 1505 switch (p->md_type) { 1506 case EFI_MD_TYPE_CODE: 1507 case EFI_MD_TYPE_DATA: 1508 case EFI_MD_TYPE_BS_CODE: 1509 case EFI_MD_TYPE_BS_DATA: 1510 case EFI_MD_TYPE_FREE: 1511 /* 1512 * We're allowed to use any entry with these types. 1513 */ 1514 break; 1515 default: 1516 continue; 1517 } 1518 1519 if (!add_physmap_entry(p->md_phys, (p->md_pages * PAGE_SIZE), 1520 physmap, physmap_idx)) 1521 break; 1522 } 1523 } 1524 1525 static char bootmethod[16] = ""; 1526 SYSCTL_STRING(_machdep, OID_AUTO, bootmethod, CTLFLAG_RD, bootmethod, 0, 1527 "System firmware boot method"); 1528 1529 /* 1530 * Populate the (physmap) array with base/bound pairs describing the 1531 * available physical memory in the system, then test this memory and 1532 * build the phys_avail array describing the actually-available memory. 1533 * 1534 * Total memory size may be set by the kernel environment variable 1535 * hw.physmem or the compile-time define MAXMEM. 1536 * 1537 * XXX first should be vm_paddr_t. 1538 */ 1539 static void 1540 getmemsize(caddr_t kmdp, u_int64_t first) 1541 { 1542 int i, physmap_idx, pa_indx, da_indx; 1543 vm_paddr_t pa, physmap[PHYSMAP_SIZE]; 1544 u_long physmem_start, physmem_tunable, memtest; 1545 pt_entry_t *pte; 1546 struct bios_smap *smapbase; 1547 struct efi_map_header *efihdr; 1548 quad_t dcons_addr, dcons_size; 1549 1550 bzero(physmap, sizeof(physmap)); 1551 basemem = 0; 1552 physmap_idx = 0; 1553 1554 efihdr = (struct efi_map_header *)preload_search_info(kmdp, 1555 MODINFO_METADATA | MODINFOMD_EFI_MAP); 1556 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1557 MODINFO_METADATA | MODINFOMD_SMAP); 1558 1559 if (efihdr != NULL) { 1560 add_efi_map_entries(efihdr, physmap, &physmap_idx); 1561 strlcpy(bootmethod, "UEFI", sizeof(bootmethod)); 1562 } else if (smapbase != NULL) { 1563 add_smap_entries(smapbase, physmap, &physmap_idx); 1564 strlcpy(bootmethod, "BIOS", sizeof(bootmethod)); 1565 } else { 1566 panic("No BIOS smap or EFI map info from loader!"); 1567 } 1568 1569 /* 1570 * Find the 'base memory' segment for SMP 1571 */ 1572 basemem = 0; 1573 for (i = 0; i <= physmap_idx; i += 2) { 1574 if (physmap[i] == 0x00000000) { 1575 basemem = physmap[i + 1] / 1024; 1576 break; 1577 } 1578 } 1579 if (basemem == 0) 1580 panic("BIOS smap did not include a basemem segment!"); 1581 1582 #ifdef SMP 1583 /* make hole for AP bootstrap code */ 1584 physmap[1] = mp_bootaddress(physmap[1] / 1024); 1585 #endif 1586 1587 /* 1588 * Maxmem isn't the "maximum memory", it's one larger than the 1589 * highest page of the physical address space. It should be 1590 * called something like "Maxphyspage". We may adjust this 1591 * based on ``hw.physmem'' and the results of the memory test. 1592 */ 1593 Maxmem = atop(physmap[physmap_idx + 1]); 1594 1595 #ifdef MAXMEM 1596 Maxmem = MAXMEM / 4; 1597 #endif 1598 1599 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1600 Maxmem = atop(physmem_tunable); 1601 1602 /* 1603 * By default enable the memory test on real hardware, and disable 1604 * it if we appear to be running in a VM. This avoids touching all 1605 * pages unnecessarily, which doesn't matter on real hardware but is 1606 * bad for shared VM hosts. Use a general name so that 1607 * one could eventually do more with the code than just disable it. 1608 */ 1609 memtest = (vm_guest > VM_GUEST_NO) ? 0 : 1; 1610 TUNABLE_ULONG_FETCH("hw.memtest.tests", &memtest); 1611 1612 /* 1613 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1614 * in the system. 1615 */ 1616 if (Maxmem > atop(physmap[physmap_idx + 1])) 1617 Maxmem = atop(physmap[physmap_idx + 1]); 1618 1619 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1620 (boothowto & RB_VERBOSE)) 1621 printf("Physical memory use set to %ldK\n", Maxmem * 4); 1622 1623 /* call pmap initialization to make new kernel address space */ 1624 pmap_bootstrap(&first); 1625 1626 /* 1627 * Size up each available chunk of physical memory. 1628 * 1629 * XXX Some BIOSes corrupt low 64KB between suspend and resume. 1630 * By default, mask off the first 16 pages unless we appear to be 1631 * running in a VM. 1632 */ 1633 physmem_start = (vm_guest > VM_GUEST_NO ? 1 : 16) << PAGE_SHIFT; 1634 TUNABLE_ULONG_FETCH("hw.physmem.start", &physmem_start); 1635 if (physmem_start < PAGE_SIZE) 1636 physmap[0] = PAGE_SIZE; 1637 else if (physmem_start >= physmap[1]) 1638 physmap[0] = round_page(physmap[1] - PAGE_SIZE); 1639 else 1640 physmap[0] = round_page(physmem_start); 1641 pa_indx = 0; 1642 da_indx = 1; 1643 phys_avail[pa_indx++] = physmap[0]; 1644 phys_avail[pa_indx] = physmap[0]; 1645 dump_avail[da_indx] = physmap[0]; 1646 pte = CMAP1; 1647 1648 /* 1649 * Get dcons buffer address 1650 */ 1651 if (getenv_quad("dcons.addr", &dcons_addr) == 0 || 1652 getenv_quad("dcons.size", &dcons_size) == 0) 1653 dcons_addr = 0; 1654 1655 /* 1656 * physmap is in bytes, so when converting to page boundaries, 1657 * round up the start address and round down the end address. 1658 */ 1659 for (i = 0; i <= physmap_idx; i += 2) { 1660 vm_paddr_t end; 1661 1662 end = ptoa((vm_paddr_t)Maxmem); 1663 if (physmap[i + 1] < end) 1664 end = trunc_page(physmap[i + 1]); 1665 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) { 1666 int tmp, page_bad, full; 1667 int *ptr = (int *)CADDR1; 1668 1669 full = FALSE; 1670 /* 1671 * block out kernel memory as not available. 1672 */ 1673 if (pa >= (vm_paddr_t)kernphys && pa < first) 1674 goto do_dump_avail; 1675 1676 /* 1677 * block out dcons buffer 1678 */ 1679 if (dcons_addr > 0 1680 && pa >= trunc_page(dcons_addr) 1681 && pa < dcons_addr + dcons_size) 1682 goto do_dump_avail; 1683 1684 page_bad = FALSE; 1685 if (memtest == 0) 1686 goto skip_memtest; 1687 1688 /* 1689 * map page into kernel: valid, read/write,non-cacheable 1690 */ 1691 *pte = pa | PG_V | PG_RW | PG_NC_PWT | PG_NC_PCD; 1692 invltlb(); 1693 1694 tmp = *(int *)ptr; 1695 /* 1696 * Test for alternating 1's and 0's 1697 */ 1698 *(volatile int *)ptr = 0xaaaaaaaa; 1699 if (*(volatile int *)ptr != 0xaaaaaaaa) 1700 page_bad = TRUE; 1701 /* 1702 * Test for alternating 0's and 1's 1703 */ 1704 *(volatile int *)ptr = 0x55555555; 1705 if (*(volatile int *)ptr != 0x55555555) 1706 page_bad = TRUE; 1707 /* 1708 * Test for all 1's 1709 */ 1710 *(volatile int *)ptr = 0xffffffff; 1711 if (*(volatile int *)ptr != 0xffffffff) 1712 page_bad = TRUE; 1713 /* 1714 * Test for all 0's 1715 */ 1716 *(volatile int *)ptr = 0x0; 1717 if (*(volatile int *)ptr != 0x0) 1718 page_bad = TRUE; 1719 /* 1720 * Restore original value. 1721 */ 1722 *(int *)ptr = tmp; 1723 1724 skip_memtest: 1725 /* 1726 * Adjust array of valid/good pages. 1727 */ 1728 if (page_bad == TRUE) 1729 continue; 1730 /* 1731 * If this good page is a continuation of the 1732 * previous set of good pages, then just increase 1733 * the end pointer. Otherwise start a new chunk. 1734 * Note that "end" points one higher than end, 1735 * making the range >= start and < end. 1736 * If we're also doing a speculative memory 1737 * test and we at or past the end, bump up Maxmem 1738 * so that we keep going. The first bad page 1739 * will terminate the loop. 1740 */ 1741 if (phys_avail[pa_indx] == pa) { 1742 phys_avail[pa_indx] += PAGE_SIZE; 1743 } else { 1744 pa_indx++; 1745 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 1746 printf( 1747 "Too many holes in the physical address space, giving up\n"); 1748 pa_indx--; 1749 full = TRUE; 1750 goto do_dump_avail; 1751 } 1752 phys_avail[pa_indx++] = pa; /* start */ 1753 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */ 1754 } 1755 physmem++; 1756 do_dump_avail: 1757 if (dump_avail[da_indx] == pa) { 1758 dump_avail[da_indx] += PAGE_SIZE; 1759 } else { 1760 da_indx++; 1761 if (da_indx == DUMP_AVAIL_ARRAY_END) { 1762 da_indx--; 1763 goto do_next; 1764 } 1765 dump_avail[da_indx++] = pa; /* start */ 1766 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */ 1767 } 1768 do_next: 1769 if (full) 1770 break; 1771 } 1772 } 1773 *pte = 0; 1774 invltlb(); 1775 1776 /* 1777 * XXX 1778 * The last chunk must contain at least one page plus the message 1779 * buffer to avoid complicating other code (message buffer address 1780 * calculation, etc.). 1781 */ 1782 while (phys_avail[pa_indx - 1] + PAGE_SIZE + 1783 round_page(msgbufsize) >= phys_avail[pa_indx]) { 1784 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1785 phys_avail[pa_indx--] = 0; 1786 phys_avail[pa_indx--] = 0; 1787 } 1788 1789 Maxmem = atop(phys_avail[pa_indx]); 1790 1791 /* Trim off space for the message buffer. */ 1792 phys_avail[pa_indx] -= round_page(msgbufsize); 1793 1794 /* Map the message buffer. */ 1795 msgbufp = (struct msgbuf *)PHYS_TO_DMAP(phys_avail[pa_indx]); 1796 } 1797 1798 u_int64_t 1799 hammer_time(u_int64_t modulep, u_int64_t physfree) 1800 { 1801 caddr_t kmdp; 1802 int gsel_tss, x; 1803 struct pcpu *pc; 1804 struct nmi_pcpu *np; 1805 struct xstate_hdr *xhdr; 1806 u_int64_t msr; 1807 char *env; 1808 size_t kstack0_sz; 1809 1810 thread0.td_kstack = physfree + KERNBASE; 1811 thread0.td_kstack_pages = KSTACK_PAGES; 1812 kstack0_sz = thread0.td_kstack_pages * PAGE_SIZE; 1813 bzero((void *)thread0.td_kstack, kstack0_sz); 1814 physfree += kstack0_sz; 1815 1816 /* 1817 * This may be done better later if it gets more high level 1818 * components in it. If so just link td->td_proc here. 1819 */ 1820 proc_linkup0(&proc0, &thread0); 1821 1822 preload_metadata = (caddr_t)(uintptr_t)(modulep + KERNBASE); 1823 preload_bootstrap_relocate(KERNBASE); 1824 kmdp = preload_search_by_type("elf kernel"); 1825 if (kmdp == NULL) 1826 kmdp = preload_search_by_type("elf64 kernel"); 1827 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 1828 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + KERNBASE; 1829 #ifdef DDB 1830 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 1831 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 1832 #endif 1833 1834 /* Init basic tunables, hz etc */ 1835 init_param1(); 1836 1837 /* 1838 * make gdt memory segments 1839 */ 1840 for (x = 0; x < NGDT; x++) { 1841 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) && 1842 x != GUSERLDT_SEL && x != (GUSERLDT_SEL) + 1) 1843 ssdtosd(&gdt_segs[x], &gdt[x]); 1844 } 1845 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&common_tss[0]; 1846 ssdtosyssd(&gdt_segs[GPROC0_SEL], 1847 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1848 1849 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 1850 r_gdt.rd_base = (long) gdt; 1851 lgdt(&r_gdt); 1852 pc = &__pcpu[0]; 1853 1854 wrmsr(MSR_FSBASE, 0); /* User value */ 1855 wrmsr(MSR_GSBASE, (u_int64_t)pc); 1856 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 1857 1858 pcpu_init(pc, 0, sizeof(struct pcpu)); 1859 dpcpu_init((void *)(physfree + KERNBASE), 0); 1860 physfree += DPCPU_SIZE; 1861 PCPU_SET(prvspace, pc); 1862 PCPU_SET(curthread, &thread0); 1863 PCPU_SET(tssp, &common_tss[0]); 1864 PCPU_SET(commontssp, &common_tss[0]); 1865 PCPU_SET(tss, (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1866 PCPU_SET(ldt, (struct system_segment_descriptor *)&gdt[GUSERLDT_SEL]); 1867 PCPU_SET(fs32p, &gdt[GUFS32_SEL]); 1868 PCPU_SET(gs32p, &gdt[GUGS32_SEL]); 1869 1870 /* 1871 * Initialize mutexes. 1872 * 1873 * icu_lock: in order to allow an interrupt to occur in a critical 1874 * section, to set pcpu->ipending (etc...) properly, we 1875 * must be able to get the icu lock, so it can't be 1876 * under witness. 1877 */ 1878 mutex_init(); 1879 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS); 1880 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_DEF); 1881 1882 /* exceptions */ 1883 for (x = 0; x < NIDT; x++) 1884 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 1885 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 1886 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 1887 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 2); 1888 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 1889 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 1890 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 1891 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 1892 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 1893 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 1894 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 1895 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 1896 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 1897 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 1898 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 1899 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 1900 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 1901 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 1902 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 1903 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 1904 #ifdef KDTRACE_HOOKS 1905 setidt(IDT_DTRACE_RET, &IDTVEC(dtrace_ret), SDT_SYSIGT, SEL_UPL, 0); 1906 #endif 1907 #ifdef XENHVM 1908 setidt(IDT_EVTCHN, &IDTVEC(xen_intr_upcall), SDT_SYSIGT, SEL_UPL, 0); 1909 #endif 1910 1911 r_idt.rd_limit = sizeof(idt0) - 1; 1912 r_idt.rd_base = (long) idt; 1913 lidt(&r_idt); 1914 1915 /* 1916 * Initialize the i8254 before the console so that console 1917 * initialization can use DELAY(). 1918 */ 1919 i8254_init(); 1920 1921 /* 1922 * Use vt(4) by default for UEFI boot (during the sc(4)/vt(4) 1923 * transition). 1924 */ 1925 if (kmdp != NULL && preload_search_info(kmdp, 1926 MODINFO_METADATA | MODINFOMD_EFI_MAP) != NULL) 1927 vty_set_preferred(VTY_VT); 1928 1929 /* 1930 * Initialize the console before we print anything out. 1931 */ 1932 cninit(); 1933 1934 #ifdef DEV_ISA 1935 #ifdef DEV_ATPIC 1936 elcr_probe(); 1937 atpic_startup(); 1938 #else 1939 /* Reset and mask the atpics and leave them shut down. */ 1940 atpic_reset(); 1941 1942 /* 1943 * Point the ICU spurious interrupt vectors at the APIC spurious 1944 * interrupt handler. 1945 */ 1946 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1947 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1948 #endif 1949 #else 1950 #error "have you forgotten the isa device?"; 1951 #endif 1952 1953 kdb_init(); 1954 1955 #ifdef KDB 1956 if (boothowto & RB_KDB) 1957 kdb_enter(KDB_WHY_BOOTFLAGS, 1958 "Boot flags requested debugger"); 1959 #endif 1960 1961 identify_cpu(); /* Final stage of CPU initialization */ 1962 initializecpu(); /* Initialize CPU registers */ 1963 initializecpucache(); 1964 1965 /* doublefault stack space, runs on ist1 */ 1966 common_tss[0].tss_ist1 = (long)&dblfault_stack[sizeof(dblfault_stack)]; 1967 1968 /* 1969 * NMI stack, runs on ist2. The pcpu pointer is stored just 1970 * above the start of the ist2 stack. 1971 */ 1972 np = ((struct nmi_pcpu *) &nmi0_stack[sizeof(nmi0_stack)]) - 1; 1973 np->np_pcpu = (register_t) pc; 1974 common_tss[0].tss_ist2 = (long) np; 1975 1976 /* Set the IO permission bitmap (empty due to tss seg limit) */ 1977 common_tss[0].tss_iobase = sizeof(struct amd64tss) + 1978 IOPAGES * PAGE_SIZE; 1979 1980 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 1981 ltr(gsel_tss); 1982 1983 /* Set up the fast syscall stuff */ 1984 msr = rdmsr(MSR_EFER) | EFER_SCE; 1985 wrmsr(MSR_EFER, msr); 1986 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 1987 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 1988 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1989 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 1990 wrmsr(MSR_STAR, msr); 1991 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 1992 1993 getmemsize(kmdp, physfree); 1994 init_param2(physmem); 1995 1996 /* now running on new page tables, configured,and u/iom is accessible */ 1997 1998 msgbufinit(msgbufp, msgbufsize); 1999 fpuinit(); 2000 2001 /* 2002 * Set up thread0 pcb after fpuinit calculated pcb + fpu save 2003 * area size. Zero out the extended state header in fpu save 2004 * area. 2005 */ 2006 thread0.td_pcb = get_pcb_td(&thread0); 2007 bzero(get_pcb_user_save_td(&thread0), cpu_max_ext_state_size); 2008 if (use_xsave) { 2009 xhdr = (struct xstate_hdr *)(get_pcb_user_save_td(&thread0) + 2010 1); 2011 xhdr->xstate_bv = xsave_mask; 2012 } 2013 /* make an initial tss so cpu can get interrupt stack on syscall! */ 2014 common_tss[0].tss_rsp0 = (vm_offset_t)thread0.td_pcb; 2015 /* Ensure the stack is aligned to 16 bytes */ 2016 common_tss[0].tss_rsp0 &= ~0xFul; 2017 PCPU_SET(rsp0, common_tss[0].tss_rsp0); 2018 PCPU_SET(curpcb, thread0.td_pcb); 2019 2020 /* transfer to user mode */ 2021 2022 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 2023 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 2024 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 2025 _ufssel = GSEL(GUFS32_SEL, SEL_UPL); 2026 _ugssel = GSEL(GUGS32_SEL, SEL_UPL); 2027 2028 load_ds(_udatasel); 2029 load_es(_udatasel); 2030 load_fs(_ufssel); 2031 2032 /* setup proc 0's pcb */ 2033 thread0.td_pcb->pcb_flags = 0; 2034 thread0.td_pcb->pcb_cr3 = KPML4phys; /* PCID 0 is reserved for kernel */ 2035 thread0.td_frame = &proc0_tf; 2036 2037 env = getenv("kernelname"); 2038 if (env != NULL) 2039 strlcpy(kernelname, env, sizeof(kernelname)); 2040 2041 cpu_probe_amdc1e(); 2042 2043 #ifdef FDT 2044 x86_init_fdt(); 2045 #endif 2046 2047 /* Location of kernel stack for locore */ 2048 return ((u_int64_t)thread0.td_pcb); 2049 } 2050 2051 void 2052 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) 2053 { 2054 2055 pcpu->pc_acpi_id = 0xffffffff; 2056 } 2057 2058 void 2059 spinlock_enter(void) 2060 { 2061 struct thread *td; 2062 register_t flags; 2063 2064 td = curthread; 2065 if (td->td_md.md_spinlock_count == 0) { 2066 flags = intr_disable(); 2067 td->td_md.md_spinlock_count = 1; 2068 td->td_md.md_saved_flags = flags; 2069 } else 2070 td->td_md.md_spinlock_count++; 2071 critical_enter(); 2072 } 2073 2074 void 2075 spinlock_exit(void) 2076 { 2077 struct thread *td; 2078 register_t flags; 2079 2080 td = curthread; 2081 critical_exit(); 2082 flags = td->td_md.md_saved_flags; 2083 td->td_md.md_spinlock_count--; 2084 if (td->td_md.md_spinlock_count == 0) 2085 intr_restore(flags); 2086 } 2087 2088 /* 2089 * Construct a PCB from a trapframe. This is called from kdb_trap() where 2090 * we want to start a backtrace from the function that caused us to enter 2091 * the debugger. We have the context in the trapframe, but base the trace 2092 * on the PCB. The PCB doesn't have to be perfect, as long as it contains 2093 * enough for a backtrace. 2094 */ 2095 void 2096 makectx(struct trapframe *tf, struct pcb *pcb) 2097 { 2098 2099 pcb->pcb_r12 = tf->tf_r12; 2100 pcb->pcb_r13 = tf->tf_r13; 2101 pcb->pcb_r14 = tf->tf_r14; 2102 pcb->pcb_r15 = tf->tf_r15; 2103 pcb->pcb_rbp = tf->tf_rbp; 2104 pcb->pcb_rbx = tf->tf_rbx; 2105 pcb->pcb_rip = tf->tf_rip; 2106 pcb->pcb_rsp = tf->tf_rsp; 2107 } 2108 2109 int 2110 ptrace_set_pc(struct thread *td, unsigned long addr) 2111 { 2112 2113 td->td_frame->tf_rip = addr; 2114 set_pcb_flags(td->td_pcb, PCB_FULL_IRET); 2115 return (0); 2116 } 2117 2118 int 2119 ptrace_single_step(struct thread *td) 2120 { 2121 td->td_frame->tf_rflags |= PSL_T; 2122 return (0); 2123 } 2124 2125 int 2126 ptrace_clear_single_step(struct thread *td) 2127 { 2128 td->td_frame->tf_rflags &= ~PSL_T; 2129 return (0); 2130 } 2131 2132 int 2133 fill_regs(struct thread *td, struct reg *regs) 2134 { 2135 struct trapframe *tp; 2136 2137 tp = td->td_frame; 2138 return (fill_frame_regs(tp, regs)); 2139 } 2140 2141 int 2142 fill_frame_regs(struct trapframe *tp, struct reg *regs) 2143 { 2144 regs->r_r15 = tp->tf_r15; 2145 regs->r_r14 = tp->tf_r14; 2146 regs->r_r13 = tp->tf_r13; 2147 regs->r_r12 = tp->tf_r12; 2148 regs->r_r11 = tp->tf_r11; 2149 regs->r_r10 = tp->tf_r10; 2150 regs->r_r9 = tp->tf_r9; 2151 regs->r_r8 = tp->tf_r8; 2152 regs->r_rdi = tp->tf_rdi; 2153 regs->r_rsi = tp->tf_rsi; 2154 regs->r_rbp = tp->tf_rbp; 2155 regs->r_rbx = tp->tf_rbx; 2156 regs->r_rdx = tp->tf_rdx; 2157 regs->r_rcx = tp->tf_rcx; 2158 regs->r_rax = tp->tf_rax; 2159 regs->r_rip = tp->tf_rip; 2160 regs->r_cs = tp->tf_cs; 2161 regs->r_rflags = tp->tf_rflags; 2162 regs->r_rsp = tp->tf_rsp; 2163 regs->r_ss = tp->tf_ss; 2164 if (tp->tf_flags & TF_HASSEGS) { 2165 regs->r_ds = tp->tf_ds; 2166 regs->r_es = tp->tf_es; 2167 regs->r_fs = tp->tf_fs; 2168 regs->r_gs = tp->tf_gs; 2169 } else { 2170 regs->r_ds = 0; 2171 regs->r_es = 0; 2172 regs->r_fs = 0; 2173 regs->r_gs = 0; 2174 } 2175 return (0); 2176 } 2177 2178 int 2179 set_regs(struct thread *td, struct reg *regs) 2180 { 2181 struct trapframe *tp; 2182 register_t rflags; 2183 2184 tp = td->td_frame; 2185 rflags = regs->r_rflags & 0xffffffff; 2186 if (!EFL_SECURE(rflags, tp->tf_rflags) || !CS_SECURE(regs->r_cs)) 2187 return (EINVAL); 2188 tp->tf_r15 = regs->r_r15; 2189 tp->tf_r14 = regs->r_r14; 2190 tp->tf_r13 = regs->r_r13; 2191 tp->tf_r12 = regs->r_r12; 2192 tp->tf_r11 = regs->r_r11; 2193 tp->tf_r10 = regs->r_r10; 2194 tp->tf_r9 = regs->r_r9; 2195 tp->tf_r8 = regs->r_r8; 2196 tp->tf_rdi = regs->r_rdi; 2197 tp->tf_rsi = regs->r_rsi; 2198 tp->tf_rbp = regs->r_rbp; 2199 tp->tf_rbx = regs->r_rbx; 2200 tp->tf_rdx = regs->r_rdx; 2201 tp->tf_rcx = regs->r_rcx; 2202 tp->tf_rax = regs->r_rax; 2203 tp->tf_rip = regs->r_rip; 2204 tp->tf_cs = regs->r_cs; 2205 tp->tf_rflags = rflags; 2206 tp->tf_rsp = regs->r_rsp; 2207 tp->tf_ss = regs->r_ss; 2208 if (0) { /* XXXKIB */ 2209 tp->tf_ds = regs->r_ds; 2210 tp->tf_es = regs->r_es; 2211 tp->tf_fs = regs->r_fs; 2212 tp->tf_gs = regs->r_gs; 2213 tp->tf_flags = TF_HASSEGS; 2214 } 2215 set_pcb_flags(td->td_pcb, PCB_FULL_IRET); 2216 return (0); 2217 } 2218 2219 /* XXX check all this stuff! */ 2220 /* externalize from sv_xmm */ 2221 static void 2222 fill_fpregs_xmm(struct savefpu *sv_xmm, struct fpreg *fpregs) 2223 { 2224 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 2225 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2226 int i; 2227 2228 /* pcb -> fpregs */ 2229 bzero(fpregs, sizeof(*fpregs)); 2230 2231 /* FPU control/status */ 2232 penv_fpreg->en_cw = penv_xmm->en_cw; 2233 penv_fpreg->en_sw = penv_xmm->en_sw; 2234 penv_fpreg->en_tw = penv_xmm->en_tw; 2235 penv_fpreg->en_opcode = penv_xmm->en_opcode; 2236 penv_fpreg->en_rip = penv_xmm->en_rip; 2237 penv_fpreg->en_rdp = penv_xmm->en_rdp; 2238 penv_fpreg->en_mxcsr = penv_xmm->en_mxcsr; 2239 penv_fpreg->en_mxcsr_mask = penv_xmm->en_mxcsr_mask; 2240 2241 /* FPU registers */ 2242 for (i = 0; i < 8; ++i) 2243 bcopy(sv_xmm->sv_fp[i].fp_acc.fp_bytes, fpregs->fpr_acc[i], 10); 2244 2245 /* SSE registers */ 2246 for (i = 0; i < 16; ++i) 2247 bcopy(sv_xmm->sv_xmm[i].xmm_bytes, fpregs->fpr_xacc[i], 16); 2248 } 2249 2250 /* internalize from fpregs into sv_xmm */ 2251 static void 2252 set_fpregs_xmm(struct fpreg *fpregs, struct savefpu *sv_xmm) 2253 { 2254 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2255 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 2256 int i; 2257 2258 /* fpregs -> pcb */ 2259 /* FPU control/status */ 2260 penv_xmm->en_cw = penv_fpreg->en_cw; 2261 penv_xmm->en_sw = penv_fpreg->en_sw; 2262 penv_xmm->en_tw = penv_fpreg->en_tw; 2263 penv_xmm->en_opcode = penv_fpreg->en_opcode; 2264 penv_xmm->en_rip = penv_fpreg->en_rip; 2265 penv_xmm->en_rdp = penv_fpreg->en_rdp; 2266 penv_xmm->en_mxcsr = penv_fpreg->en_mxcsr; 2267 penv_xmm->en_mxcsr_mask = penv_fpreg->en_mxcsr_mask & cpu_mxcsr_mask; 2268 2269 /* FPU registers */ 2270 for (i = 0; i < 8; ++i) 2271 bcopy(fpregs->fpr_acc[i], sv_xmm->sv_fp[i].fp_acc.fp_bytes, 10); 2272 2273 /* SSE registers */ 2274 for (i = 0; i < 16; ++i) 2275 bcopy(fpregs->fpr_xacc[i], sv_xmm->sv_xmm[i].xmm_bytes, 16); 2276 } 2277 2278 /* externalize from td->pcb */ 2279 int 2280 fill_fpregs(struct thread *td, struct fpreg *fpregs) 2281 { 2282 2283 KASSERT(td == curthread || TD_IS_SUSPENDED(td) || 2284 P_SHOULDSTOP(td->td_proc), 2285 ("not suspended thread %p", td)); 2286 fpugetregs(td); 2287 fill_fpregs_xmm(get_pcb_user_save_td(td), fpregs); 2288 return (0); 2289 } 2290 2291 /* internalize to td->pcb */ 2292 int 2293 set_fpregs(struct thread *td, struct fpreg *fpregs) 2294 { 2295 2296 set_fpregs_xmm(fpregs, get_pcb_user_save_td(td)); 2297 fpuuserinited(td); 2298 return (0); 2299 } 2300 2301 /* 2302 * Get machine context. 2303 */ 2304 int 2305 get_mcontext(struct thread *td, mcontext_t *mcp, int flags) 2306 { 2307 struct pcb *pcb; 2308 struct trapframe *tp; 2309 2310 pcb = td->td_pcb; 2311 tp = td->td_frame; 2312 PROC_LOCK(curthread->td_proc); 2313 mcp->mc_onstack = sigonstack(tp->tf_rsp); 2314 PROC_UNLOCK(curthread->td_proc); 2315 mcp->mc_r15 = tp->tf_r15; 2316 mcp->mc_r14 = tp->tf_r14; 2317 mcp->mc_r13 = tp->tf_r13; 2318 mcp->mc_r12 = tp->tf_r12; 2319 mcp->mc_r11 = tp->tf_r11; 2320 mcp->mc_r10 = tp->tf_r10; 2321 mcp->mc_r9 = tp->tf_r9; 2322 mcp->mc_r8 = tp->tf_r8; 2323 mcp->mc_rdi = tp->tf_rdi; 2324 mcp->mc_rsi = tp->tf_rsi; 2325 mcp->mc_rbp = tp->tf_rbp; 2326 mcp->mc_rbx = tp->tf_rbx; 2327 mcp->mc_rcx = tp->tf_rcx; 2328 mcp->mc_rflags = tp->tf_rflags; 2329 if (flags & GET_MC_CLEAR_RET) { 2330 mcp->mc_rax = 0; 2331 mcp->mc_rdx = 0; 2332 mcp->mc_rflags &= ~PSL_C; 2333 } else { 2334 mcp->mc_rax = tp->tf_rax; 2335 mcp->mc_rdx = tp->tf_rdx; 2336 } 2337 mcp->mc_rip = tp->tf_rip; 2338 mcp->mc_cs = tp->tf_cs; 2339 mcp->mc_rsp = tp->tf_rsp; 2340 mcp->mc_ss = tp->tf_ss; 2341 mcp->mc_ds = tp->tf_ds; 2342 mcp->mc_es = tp->tf_es; 2343 mcp->mc_fs = tp->tf_fs; 2344 mcp->mc_gs = tp->tf_gs; 2345 mcp->mc_flags = tp->tf_flags; 2346 mcp->mc_len = sizeof(*mcp); 2347 get_fpcontext(td, mcp, NULL, 0); 2348 mcp->mc_fsbase = pcb->pcb_fsbase; 2349 mcp->mc_gsbase = pcb->pcb_gsbase; 2350 mcp->mc_xfpustate = 0; 2351 mcp->mc_xfpustate_len = 0; 2352 bzero(mcp->mc_spare, sizeof(mcp->mc_spare)); 2353 return (0); 2354 } 2355 2356 /* 2357 * Set machine context. 2358 * 2359 * However, we don't set any but the user modifiable flags, and we won't 2360 * touch the cs selector. 2361 */ 2362 int 2363 set_mcontext(struct thread *td, const mcontext_t *mcp) 2364 { 2365 struct pcb *pcb; 2366 struct trapframe *tp; 2367 char *xfpustate; 2368 long rflags; 2369 int ret; 2370 2371 pcb = td->td_pcb; 2372 tp = td->td_frame; 2373 if (mcp->mc_len != sizeof(*mcp) || 2374 (mcp->mc_flags & ~_MC_FLAG_MASK) != 0) 2375 return (EINVAL); 2376 rflags = (mcp->mc_rflags & PSL_USERCHANGE) | 2377 (tp->tf_rflags & ~PSL_USERCHANGE); 2378 if (mcp->mc_flags & _MC_HASFPXSTATE) { 2379 if (mcp->mc_xfpustate_len > cpu_max_ext_state_size - 2380 sizeof(struct savefpu)) 2381 return (EINVAL); 2382 xfpustate = __builtin_alloca(mcp->mc_xfpustate_len); 2383 ret = copyin((void *)mcp->mc_xfpustate, xfpustate, 2384 mcp->mc_xfpustate_len); 2385 if (ret != 0) 2386 return (ret); 2387 } else 2388 xfpustate = NULL; 2389 ret = set_fpcontext(td, mcp, xfpustate, mcp->mc_xfpustate_len); 2390 if (ret != 0) 2391 return (ret); 2392 tp->tf_r15 = mcp->mc_r15; 2393 tp->tf_r14 = mcp->mc_r14; 2394 tp->tf_r13 = mcp->mc_r13; 2395 tp->tf_r12 = mcp->mc_r12; 2396 tp->tf_r11 = mcp->mc_r11; 2397 tp->tf_r10 = mcp->mc_r10; 2398 tp->tf_r9 = mcp->mc_r9; 2399 tp->tf_r8 = mcp->mc_r8; 2400 tp->tf_rdi = mcp->mc_rdi; 2401 tp->tf_rsi = mcp->mc_rsi; 2402 tp->tf_rbp = mcp->mc_rbp; 2403 tp->tf_rbx = mcp->mc_rbx; 2404 tp->tf_rdx = mcp->mc_rdx; 2405 tp->tf_rcx = mcp->mc_rcx; 2406 tp->tf_rax = mcp->mc_rax; 2407 tp->tf_rip = mcp->mc_rip; 2408 tp->tf_rflags = rflags; 2409 tp->tf_rsp = mcp->mc_rsp; 2410 tp->tf_ss = mcp->mc_ss; 2411 tp->tf_flags = mcp->mc_flags; 2412 if (tp->tf_flags & TF_HASSEGS) { 2413 tp->tf_ds = mcp->mc_ds; 2414 tp->tf_es = mcp->mc_es; 2415 tp->tf_fs = mcp->mc_fs; 2416 tp->tf_gs = mcp->mc_gs; 2417 } 2418 if (mcp->mc_flags & _MC_HASBASES) { 2419 pcb->pcb_fsbase = mcp->mc_fsbase; 2420 pcb->pcb_gsbase = mcp->mc_gsbase; 2421 } 2422 set_pcb_flags(pcb, PCB_FULL_IRET); 2423 return (0); 2424 } 2425 2426 static void 2427 get_fpcontext(struct thread *td, mcontext_t *mcp, char *xfpusave, 2428 size_t xfpusave_len) 2429 { 2430 size_t max_len, len; 2431 2432 mcp->mc_ownedfp = fpugetregs(td); 2433 bcopy(get_pcb_user_save_td(td), &mcp->mc_fpstate[0], 2434 sizeof(mcp->mc_fpstate)); 2435 mcp->mc_fpformat = fpuformat(); 2436 if (!use_xsave || xfpusave_len == 0) 2437 return; 2438 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 2439 len = xfpusave_len; 2440 if (len > max_len) { 2441 len = max_len; 2442 bzero(xfpusave + max_len, len - max_len); 2443 } 2444 mcp->mc_flags |= _MC_HASFPXSTATE; 2445 mcp->mc_xfpustate_len = len; 2446 bcopy(get_pcb_user_save_td(td) + 1, xfpusave, len); 2447 } 2448 2449 static int 2450 set_fpcontext(struct thread *td, const mcontext_t *mcp, char *xfpustate, 2451 size_t xfpustate_len) 2452 { 2453 struct savefpu *fpstate; 2454 int error; 2455 2456 if (mcp->mc_fpformat == _MC_FPFMT_NODEV) 2457 return (0); 2458 else if (mcp->mc_fpformat != _MC_FPFMT_XMM) 2459 return (EINVAL); 2460 else if (mcp->mc_ownedfp == _MC_FPOWNED_NONE) { 2461 /* We don't care what state is left in the FPU or PCB. */ 2462 fpstate_drop(td); 2463 error = 0; 2464 } else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU || 2465 mcp->mc_ownedfp == _MC_FPOWNED_PCB) { 2466 fpstate = (struct savefpu *)&mcp->mc_fpstate; 2467 fpstate->sv_env.en_mxcsr &= cpu_mxcsr_mask; 2468 error = fpusetregs(td, fpstate, xfpustate, xfpustate_len); 2469 } else 2470 return (EINVAL); 2471 return (error); 2472 } 2473 2474 void 2475 fpstate_drop(struct thread *td) 2476 { 2477 2478 KASSERT(PCB_USER_FPU(td->td_pcb), ("fpstate_drop: kernel-owned fpu")); 2479 critical_enter(); 2480 if (PCPU_GET(fpcurthread) == td) 2481 fpudrop(); 2482 /* 2483 * XXX force a full drop of the fpu. The above only drops it if we 2484 * owned it. 2485 * 2486 * XXX I don't much like fpugetuserregs()'s semantics of doing a full 2487 * drop. Dropping only to the pcb matches fnsave's behaviour. 2488 * We only need to drop to !PCB_INITDONE in sendsig(). But 2489 * sendsig() is the only caller of fpugetuserregs()... perhaps we just 2490 * have too many layers. 2491 */ 2492 clear_pcb_flags(curthread->td_pcb, 2493 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 2494 critical_exit(); 2495 } 2496 2497 int 2498 fill_dbregs(struct thread *td, struct dbreg *dbregs) 2499 { 2500 struct pcb *pcb; 2501 2502 if (td == NULL) { 2503 dbregs->dr[0] = rdr0(); 2504 dbregs->dr[1] = rdr1(); 2505 dbregs->dr[2] = rdr2(); 2506 dbregs->dr[3] = rdr3(); 2507 dbregs->dr[6] = rdr6(); 2508 dbregs->dr[7] = rdr7(); 2509 } else { 2510 pcb = td->td_pcb; 2511 dbregs->dr[0] = pcb->pcb_dr0; 2512 dbregs->dr[1] = pcb->pcb_dr1; 2513 dbregs->dr[2] = pcb->pcb_dr2; 2514 dbregs->dr[3] = pcb->pcb_dr3; 2515 dbregs->dr[6] = pcb->pcb_dr6; 2516 dbregs->dr[7] = pcb->pcb_dr7; 2517 } 2518 dbregs->dr[4] = 0; 2519 dbregs->dr[5] = 0; 2520 dbregs->dr[8] = 0; 2521 dbregs->dr[9] = 0; 2522 dbregs->dr[10] = 0; 2523 dbregs->dr[11] = 0; 2524 dbregs->dr[12] = 0; 2525 dbregs->dr[13] = 0; 2526 dbregs->dr[14] = 0; 2527 dbregs->dr[15] = 0; 2528 return (0); 2529 } 2530 2531 int 2532 set_dbregs(struct thread *td, struct dbreg *dbregs) 2533 { 2534 struct pcb *pcb; 2535 int i; 2536 2537 if (td == NULL) { 2538 load_dr0(dbregs->dr[0]); 2539 load_dr1(dbregs->dr[1]); 2540 load_dr2(dbregs->dr[2]); 2541 load_dr3(dbregs->dr[3]); 2542 load_dr6(dbregs->dr[6]); 2543 load_dr7(dbregs->dr[7]); 2544 } else { 2545 /* 2546 * Don't let an illegal value for dr7 get set. Specifically, 2547 * check for undefined settings. Setting these bit patterns 2548 * result in undefined behaviour and can lead to an unexpected 2549 * TRCTRAP or a general protection fault right here. 2550 * Upper bits of dr6 and dr7 must not be set 2551 */ 2552 for (i = 0; i < 4; i++) { 2553 if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02) 2554 return (EINVAL); 2555 if (td->td_frame->tf_cs == _ucode32sel && 2556 DBREG_DR7_LEN(dbregs->dr[7], i) == DBREG_DR7_LEN_8) 2557 return (EINVAL); 2558 } 2559 if ((dbregs->dr[6] & 0xffffffff00000000ul) != 0 || 2560 (dbregs->dr[7] & 0xffffffff00000000ul) != 0) 2561 return (EINVAL); 2562 2563 pcb = td->td_pcb; 2564 2565 /* 2566 * Don't let a process set a breakpoint that is not within the 2567 * process's address space. If a process could do this, it 2568 * could halt the system by setting a breakpoint in the kernel 2569 * (if ddb was enabled). Thus, we need to check to make sure 2570 * that no breakpoints are being enabled for addresses outside 2571 * process's address space. 2572 * 2573 * XXX - what about when the watched area of the user's 2574 * address space is written into from within the kernel 2575 * ... wouldn't that still cause a breakpoint to be generated 2576 * from within kernel mode? 2577 */ 2578 2579 if (DBREG_DR7_ENABLED(dbregs->dr[7], 0)) { 2580 /* dr0 is enabled */ 2581 if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS) 2582 return (EINVAL); 2583 } 2584 if (DBREG_DR7_ENABLED(dbregs->dr[7], 1)) { 2585 /* dr1 is enabled */ 2586 if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS) 2587 return (EINVAL); 2588 } 2589 if (DBREG_DR7_ENABLED(dbregs->dr[7], 2)) { 2590 /* dr2 is enabled */ 2591 if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS) 2592 return (EINVAL); 2593 } 2594 if (DBREG_DR7_ENABLED(dbregs->dr[7], 3)) { 2595 /* dr3 is enabled */ 2596 if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS) 2597 return (EINVAL); 2598 } 2599 2600 pcb->pcb_dr0 = dbregs->dr[0]; 2601 pcb->pcb_dr1 = dbregs->dr[1]; 2602 pcb->pcb_dr2 = dbregs->dr[2]; 2603 pcb->pcb_dr3 = dbregs->dr[3]; 2604 pcb->pcb_dr6 = dbregs->dr[6]; 2605 pcb->pcb_dr7 = dbregs->dr[7]; 2606 2607 set_pcb_flags(pcb, PCB_DBREGS); 2608 } 2609 2610 return (0); 2611 } 2612 2613 void 2614 reset_dbregs(void) 2615 { 2616 2617 load_dr7(0); /* Turn off the control bits first */ 2618 load_dr0(0); 2619 load_dr1(0); 2620 load_dr2(0); 2621 load_dr3(0); 2622 load_dr6(0); 2623 } 2624 2625 /* 2626 * Return > 0 if a hardware breakpoint has been hit, and the 2627 * breakpoint was in user space. Return 0, otherwise. 2628 */ 2629 int 2630 user_dbreg_trap(void) 2631 { 2632 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2633 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2634 int nbp; /* number of breakpoints that triggered */ 2635 caddr_t addr[4]; /* breakpoint addresses */ 2636 int i; 2637 2638 dr7 = rdr7(); 2639 if ((dr7 & 0x000000ff) == 0) { 2640 /* 2641 * all GE and LE bits in the dr7 register are zero, 2642 * thus the trap couldn't have been caused by the 2643 * hardware debug registers 2644 */ 2645 return 0; 2646 } 2647 2648 nbp = 0; 2649 dr6 = rdr6(); 2650 bp = dr6 & 0x0000000f; 2651 2652 if (!bp) { 2653 /* 2654 * None of the breakpoint bits are set meaning this 2655 * trap was not caused by any of the debug registers 2656 */ 2657 return 0; 2658 } 2659 2660 /* 2661 * at least one of the breakpoints were hit, check to see 2662 * which ones and if any of them are user space addresses 2663 */ 2664 2665 if (bp & 0x01) { 2666 addr[nbp++] = (caddr_t)rdr0(); 2667 } 2668 if (bp & 0x02) { 2669 addr[nbp++] = (caddr_t)rdr1(); 2670 } 2671 if (bp & 0x04) { 2672 addr[nbp++] = (caddr_t)rdr2(); 2673 } 2674 if (bp & 0x08) { 2675 addr[nbp++] = (caddr_t)rdr3(); 2676 } 2677 2678 for (i = 0; i < nbp; i++) { 2679 if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) { 2680 /* 2681 * addr[i] is in user space 2682 */ 2683 return nbp; 2684 } 2685 } 2686 2687 /* 2688 * None of the breakpoints are in user space. 2689 */ 2690 return 0; 2691 } 2692 2693 #ifdef KDB 2694 2695 /* 2696 * Provide inb() and outb() as functions. They are normally only available as 2697 * inline functions, thus cannot be called from the debugger. 2698 */ 2699 2700 /* silence compiler warnings */ 2701 u_char inb_(u_short); 2702 void outb_(u_short, u_char); 2703 2704 u_char 2705 inb_(u_short port) 2706 { 2707 return inb(port); 2708 } 2709 2710 void 2711 outb_(u_short port, u_char data) 2712 { 2713 outb(port, data); 2714 } 2715 2716 #endif /* KDB */
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